OPTIGA™ Trust M Host Library Documentation  v3.00.2490
XMC4800.h
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30 /****************************************************************************************************/
54 #ifndef XMC4800_H
55 #define XMC4800_H
56 
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60 
61 
62 /* ------------------------- Interrupt Number Definition ------------------------ */
63 
64 typedef enum {
65 /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
66  Reset_IRQn = -15,
67  NonMaskableInt_IRQn = -14,
68  HardFault_IRQn = -13,
69  MemoryManagement_IRQn = -12,
71  BusFault_IRQn = -11,
73  UsageFault_IRQn = -10,
74  SVCall_IRQn = -5,
75  DebugMonitor_IRQn = -4,
76  PendSV_IRQn = -2,
77  SysTick_IRQn = -1,
78 /* --------------------- XMC4800 Specific Interrupt Numbers --------------------- */
79  SCU_0_IRQn = 0,
80  ERU0_0_IRQn = 1,
81  ERU0_1_IRQn = 2,
82  ERU0_2_IRQn = 3,
83  ERU0_3_IRQn = 4,
84  ERU1_0_IRQn = 5,
85  ERU1_1_IRQn = 6,
86  ERU1_2_IRQn = 7,
87  ERU1_3_IRQn = 8,
88  PMU0_0_IRQn = 12,
89  VADC0_C0_0_IRQn = 14,
90  VADC0_C0_1_IRQn = 15,
91  VADC0_C0_2_IRQn = 16,
92  VADC0_C0_3_IRQn = 17,
93  VADC0_G0_0_IRQn = 18,
94  VADC0_G0_1_IRQn = 19,
95  VADC0_G0_2_IRQn = 20,
96  VADC0_G0_3_IRQn = 21,
97  VADC0_G1_0_IRQn = 22,
98  VADC0_G1_1_IRQn = 23,
99  VADC0_G1_2_IRQn = 24,
100  VADC0_G1_3_IRQn = 25,
101  VADC0_G2_0_IRQn = 26,
102  VADC0_G2_1_IRQn = 27,
103  VADC0_G2_2_IRQn = 28,
104  VADC0_G2_3_IRQn = 29,
105  VADC0_G3_0_IRQn = 30,
106  VADC0_G3_1_IRQn = 31,
107  VADC0_G3_2_IRQn = 32,
108  VADC0_G3_3_IRQn = 33,
109  DSD0_M_0_IRQn = 34,
110  DSD0_M_1_IRQn = 35,
111  DSD0_M_2_IRQn = 36,
112  DSD0_M_3_IRQn = 37,
113  DSD0_A_4_IRQn = 38,
114  DSD0_A_5_IRQn = 39,
115  DSD0_A_6_IRQn = 40,
116  DSD0_A_7_IRQn = 41,
117  DAC0_0_IRQn = 42,
118  DAC0_1_IRQn = 43,
119  CCU40_0_IRQn = 44,
120  CCU40_1_IRQn = 45,
121  CCU40_2_IRQn = 46,
122  CCU40_3_IRQn = 47,
123  CCU41_0_IRQn = 48,
124  CCU41_1_IRQn = 49,
125  CCU41_2_IRQn = 50,
126  CCU41_3_IRQn = 51,
127  CCU42_0_IRQn = 52,
128  CCU42_1_IRQn = 53,
129  CCU42_2_IRQn = 54,
130  CCU42_3_IRQn = 55,
131  CCU43_0_IRQn = 56,
132  CCU43_1_IRQn = 57,
133  CCU43_2_IRQn = 58,
134  CCU43_3_IRQn = 59,
135  CCU80_0_IRQn = 60,
136  CCU80_1_IRQn = 61,
137  CCU80_2_IRQn = 62,
138  CCU80_3_IRQn = 63,
139  CCU81_0_IRQn = 64,
140  CCU81_1_IRQn = 65,
141  CCU81_2_IRQn = 66,
142  CCU81_3_IRQn = 67,
143  POSIF0_0_IRQn = 68,
144  POSIF0_1_IRQn = 69,
145  POSIF1_0_IRQn = 70,
146  POSIF1_1_IRQn = 71,
147  CAN0_0_IRQn = 76,
148  CAN0_1_IRQn = 77,
149  CAN0_2_IRQn = 78,
150  CAN0_3_IRQn = 79,
151  CAN0_4_IRQn = 80,
152  CAN0_5_IRQn = 81,
153  CAN0_6_IRQn = 82,
154  CAN0_7_IRQn = 83,
155  USIC0_0_IRQn = 84,
156  USIC0_1_IRQn = 85,
157  USIC0_2_IRQn = 86,
158  USIC0_3_IRQn = 87,
159  USIC0_4_IRQn = 88,
160  USIC0_5_IRQn = 89,
161  USIC1_0_IRQn = 90,
162  USIC1_1_IRQn = 91,
163  USIC1_2_IRQn = 92,
164  USIC1_3_IRQn = 93,
165  USIC1_4_IRQn = 94,
166  USIC1_5_IRQn = 95,
167  USIC2_0_IRQn = 96,
168  USIC2_1_IRQn = 97,
169  USIC2_2_IRQn = 98,
170  USIC2_3_IRQn = 99,
171  USIC2_4_IRQn = 100,
172  USIC2_5_IRQn = 101,
173  LEDTS0_0_IRQn = 102,
174  FCE0_0_IRQn = 104,
175  GPDMA0_0_IRQn = 105,
176  SDMMC0_0_IRQn = 106,
177  USB0_0_IRQn = 107,
178  ETH0_0_IRQn = 108,
179  ECAT0_0_IRQn = 109,
180  GPDMA1_0_IRQn = 110
181 } IRQn_Type;
182 
183 
189 /* ================================================================================ */
190 /* ================ Processor and Core Peripheral Section ================ */
191 /* ================================================================================ */
192 
193 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
194 #define __CM4_REV 0x0200
195 #define __MPU_PRESENT 1
196 #define __NVIC_PRIO_BITS 6
197 #define __Vendor_SysTickConfig 0
198 #define __FPU_PRESENT 1 /* End of group Configuration_of_CMSIS */
200 
201 #include "core_cm4.h"
202 #include "system_XMC4800.h"
205 /* ================================================================================ */
206 /* ================ Device Specific Peripheral Section ================ */
207 /* ================================================================================ */
208 /* Macro to modify desired bitfields of a register */
209 #define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \
210  ((uint32_t)mask)) | \
211  (reg & ((uint32_t)~((uint32_t)mask)))
212 
213 /* Macro to modify desired bitfields of a register */
214 #define WR_REG_SIZE(reg, mask, pos, val, size) { \
215 uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \
216 uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \
217 uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \
218 uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \
219 reg = (uint##size##_t) (VAL2 | VAL4);\
220 }
221 
223 #define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos)
224 
226 #define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \
227  (uint32_t)mask) >> pos) )
228 
230 #define SET_BIT(reg, pos) (reg |= ((uint32_t)1<<pos))
231 
233 #define CLR_BIT(reg, pos) (reg = reg & (uint32_t)(~((uint32_t)1<<pos)) )
234 /*
235 * ==========================================================================
236 * ---------- Interrupt Handler Definition ----------------------------------
237 * ==========================================================================
238 */
239 #define IRQ_Hdlr_0 SCU_0_IRQHandler
240 #define IRQ_Hdlr_1 ERU0_0_IRQHandler
241 #define IRQ_Hdlr_2 ERU0_1_IRQHandler
242 #define IRQ_Hdlr_3 ERU0_2_IRQHandler
243 #define IRQ_Hdlr_4 ERU0_3_IRQHandler
244 #define IRQ_Hdlr_5 ERU1_0_IRQHandler
245 #define IRQ_Hdlr_6 ERU1_1_IRQHandler
246 #define IRQ_Hdlr_7 ERU1_2_IRQHandler
247 #define IRQ_Hdlr_8 ERU1_3_IRQHandler
248 #define IRQ_Hdlr_12 PMU0_0_IRQHandler
249 #define IRQ_Hdlr_14 VADC0_C0_0_IRQHandler
250 #define IRQ_Hdlr_15 VADC0_C0_1_IRQHandler
251 #define IRQ_Hdlr_16 VADC0_C0_2_IRQHandler
252 #define IRQ_Hdlr_17 VADC0_C0_3_IRQHandler
253 #define IRQ_Hdlr_18 VADC0_G0_0_IRQHandler
254 #define IRQ_Hdlr_19 VADC0_G0_1_IRQHandler
255 #define IRQ_Hdlr_20 VADC0_G0_2_IRQHandler
256 #define IRQ_Hdlr_21 VADC0_G0_3_IRQHandler
257 #define IRQ_Hdlr_22 VADC0_G1_0_IRQHandler
258 #define IRQ_Hdlr_23 VADC0_G1_1_IRQHandler
259 #define IRQ_Hdlr_24 VADC0_G1_2_IRQHandler
260 #define IRQ_Hdlr_25 VADC0_G1_3_IRQHandler
261 #define IRQ_Hdlr_26 VADC0_G2_0_IRQHandler
262 #define IRQ_Hdlr_27 VADC0_G2_1_IRQHandler
263 #define IRQ_Hdlr_28 VADC0_G2_2_IRQHandler
264 #define IRQ_Hdlr_29 VADC0_G2_3_IRQHandler
265 #define IRQ_Hdlr_30 VADC0_G3_0_IRQHandler
266 #define IRQ_Hdlr_31 VADC0_G3_1_IRQHandler
267 #define IRQ_Hdlr_32 VADC0_G3_2_IRQHandler
268 #define IRQ_Hdlr_33 VADC0_G3_3_IRQHandler
269 #define IRQ_Hdlr_34 DSD0_0_IRQHandler
270 #define IRQ_Hdlr_35 DSD0_1_IRQHandler
271 #define IRQ_Hdlr_36 DSD0_2_IRQHandler
272 #define IRQ_Hdlr_37 DSD0_3_IRQHandler
273 #define IRQ_Hdlr_38 DSD0_4_IRQHandler
274 #define IRQ_Hdlr_39 DSD0_5_IRQHandler
275 #define IRQ_Hdlr_40 DSD0_6_IRQHandler
276 #define IRQ_Hdlr_41 DSD0_7_IRQHandler
277 #define IRQ_Hdlr_42 DAC0_0_IRQHandler
278 #define IRQ_Hdlr_43 DAC0_1_IRQHandler
279 #define IRQ_Hdlr_44 CCU40_0_IRQHandler
280 #define IRQ_Hdlr_45 CCU40_1_IRQHandler
281 #define IRQ_Hdlr_46 CCU40_2_IRQHandler
282 #define IRQ_Hdlr_47 CCU40_3_IRQHandler
283 #define IRQ_Hdlr_48 CCU41_0_IRQHandler
284 #define IRQ_Hdlr_49 CCU41_1_IRQHandler
285 #define IRQ_Hdlr_50 CCU41_2_IRQHandler
286 #define IRQ_Hdlr_51 CCU41_3_IRQHandler
287 #define IRQ_Hdlr_52 CCU42_0_IRQHandler
288 #define IRQ_Hdlr_53 CCU42_1_IRQHandler
289 #define IRQ_Hdlr_54 CCU42_2_IRQHandler
290 #define IRQ_Hdlr_55 CCU42_3_IRQHandler
291 #define IRQ_Hdlr_56 CCU43_0_IRQHandler
292 #define IRQ_Hdlr_57 CCU43_1_IRQHandler
293 #define IRQ_Hdlr_58 CCU43_2_IRQHandler
294 #define IRQ_Hdlr_59 CCU43_3_IRQHandler
295 #define IRQ_Hdlr_60 CCU80_0_IRQHandler
296 #define IRQ_Hdlr_61 CCU80_1_IRQHandler
297 #define IRQ_Hdlr_62 CCU80_2_IRQHandler
298 #define IRQ_Hdlr_63 CCU80_3_IRQHandler
299 #define IRQ_Hdlr_64 CCU81_0_IRQHandler
300 #define IRQ_Hdlr_65 CCU81_1_IRQHandler
301 #define IRQ_Hdlr_66 CCU81_2_IRQHandler
302 #define IRQ_Hdlr_67 CCU81_3_IRQHandler
303 #define IRQ_Hdlr_68 POSIF0_0_IRQHandler
304 #define IRQ_Hdlr_69 POSIF0_1_IRQHandler
305 #define IRQ_Hdlr_70 POSIF1_0_IRQHandler
306 #define IRQ_Hdlr_71 POSIF1_1_IRQHandler
307 #define IRQ_Hdlr_76 CAN0_0_IRQHandler
308 #define IRQ_Hdlr_77 CAN0_1_IRQHandler
309 #define IRQ_Hdlr_78 CAN0_2_IRQHandler
310 #define IRQ_Hdlr_79 CAN0_3_IRQHandler
311 #define IRQ_Hdlr_80 CAN0_4_IRQHandler
312 #define IRQ_Hdlr_81 CAN0_5_IRQHandler
313 #define IRQ_Hdlr_82 CAN0_6_IRQHandler
314 #define IRQ_Hdlr_83 CAN0_7_IRQHandler
315 #define IRQ_Hdlr_84 USIC0_0_IRQHandler
316 #define IRQ_Hdlr_85 USIC0_1_IRQHandler
317 #define IRQ_Hdlr_86 USIC0_2_IRQHandler
318 #define IRQ_Hdlr_87 USIC0_3_IRQHandler
319 #define IRQ_Hdlr_88 USIC0_4_IRQHandler
320 #define IRQ_Hdlr_89 USIC0_5_IRQHandler
321 #define IRQ_Hdlr_90 USIC1_0_IRQHandler
322 #define IRQ_Hdlr_91 USIC1_1_IRQHandler
323 #define IRQ_Hdlr_92 USIC1_2_IRQHandler
324 #define IRQ_Hdlr_93 USIC1_3_IRQHandler
325 #define IRQ_Hdlr_94 USIC1_4_IRQHandler
326 #define IRQ_Hdlr_95 USIC1_5_IRQHandler
327 #define IRQ_Hdlr_96 USIC2_0_IRQHandler
328 #define IRQ_Hdlr_97 USIC2_1_IRQHandler
329 #define IRQ_Hdlr_98 USIC2_2_IRQHandler
330 #define IRQ_Hdlr_99 USIC2_3_IRQHandler
331 #define IRQ_Hdlr_100 USIC2_4_IRQHandler
332 #define IRQ_Hdlr_101 USIC2_5_IRQHandler
333 #define IRQ_Hdlr_102 LEDTS0_0_IRQHandler
334 #define IRQ_Hdlr_104 FCE0_0_IRQHandler
335 #define IRQ_Hdlr_105 GPDMA0_0_IRQHandler
336 #define IRQ_Hdlr_106 SDMMC0_0_IRQHandler
337 #define IRQ_Hdlr_107 USB0_0_IRQHandler
338 #define IRQ_Hdlr_108 ETH0_0_IRQHandler
339 #define IRQ_Hdlr_109 ECAT0_0_IRQHandler
340 #define IRQ_Hdlr_110 GPDMA1_0_IRQHandler
341 
342 /*
343 * ==========================================================================
344 * ---------- Interrupt Handler retrieval macro -----------------------------
345 * ==========================================================================
346 */
347 #define GET_IRQ_HANDLER(N) IRQ_Hdlr_##N
348 
354 /* ------------------- Start of section using anonymous unions ------------------ */
355 #if defined(__CC_ARM)
356  #pragma push
357  #pragma anon_unions
358 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
359  #pragma clang diagnostic push
360  #pragma clang diagnostic ignored "-Wc11-extensions"
361  #pragma clang diagnostic ignored "-Wreserved-id-macro"
362 #elif defined(__ICCARM__)
363  #pragma language=extended
364 #elif defined(__GNUC__)
365  /* anonymous unions are enabled by default */
366 #elif defined(__TMS470__)
367 /* anonymous unions are enabled by default */
368 #elif defined(__TASKING__)
369  #pragma warning 586
370 #else
371  #warning Not supported compiler type
372 #endif
373 
374 
375 typedef struct {
376  __IO uint32_t MOFCR;
377  __IO uint32_t MOFGPR;
378  __IO uint32_t MOIPR;
379  __IO uint32_t MOAMR;
380  __IO uint32_t MODATAL;
381  __IO uint32_t MODATAH;
382  __IO uint32_t MOAR;
384  union {
385  __I uint32_t MOSTAT;
386  __O uint32_t MOCTR;
387  };
388 } CAN_MO_TypeDef;
391 /* ================================================================================ */
392 /* ================ PPB ================ */
393 /* ================================================================================ */
394 
395 
400 typedef struct {
401  __I uint32_t RESERVED[2];
402  __IO uint32_t ACTLR;
403  __I uint32_t RESERVED1;
404  __IO uint32_t SYST_CSR;
405  __IO uint32_t SYST_RVR;
406  __IO uint32_t SYST_CVR;
407  __IO uint32_t SYST_CALIB;
408  __I uint32_t RESERVED2[56];
409  __IO uint32_t NVIC_ISER0;
410  __IO uint32_t NVIC_ISER1;
411  __IO uint32_t NVIC_ISER2;
412  __IO uint32_t NVIC_ISER3;
413  __I uint32_t RESERVED3[28];
414  __IO uint32_t NVIC_ICER0;
415  __IO uint32_t NVIC_ICER1;
416  __IO uint32_t NVIC_ICER2;
417  __IO uint32_t NVIC_ICER3;
418  __I uint32_t RESERVED4[28];
419  __IO uint32_t NVIC_ISPR0;
420  __IO uint32_t NVIC_ISPR1;
421  __IO uint32_t NVIC_ISPR2;
422  __IO uint32_t NVIC_ISPR3;
423  __I uint32_t RESERVED5[28];
424  __IO uint32_t NVIC_ICPR0;
425  __IO uint32_t NVIC_ICPR1;
426  __IO uint32_t NVIC_ICPR2;
427  __IO uint32_t NVIC_ICPR3;
428  __I uint32_t RESERVED6[28];
429  __IO uint32_t NVIC_IABR0;
430  __IO uint32_t NVIC_IABR1;
431  __IO uint32_t NVIC_IABR2;
432  __IO uint32_t NVIC_IABR3;
433  __I uint32_t RESERVED7[60];
434  __IO uint32_t NVIC_IPR0;
435  __IO uint32_t NVIC_IPR1;
436  __IO uint32_t NVIC_IPR2;
437  __IO uint32_t NVIC_IPR3;
438  __IO uint32_t NVIC_IPR4;
439  __IO uint32_t NVIC_IPR5;
440  __IO uint32_t NVIC_IPR6;
441  __IO uint32_t NVIC_IPR7;
442  __IO uint32_t NVIC_IPR8;
443  __IO uint32_t NVIC_IPR9;
444  __IO uint32_t NVIC_IPR10;
445  __IO uint32_t NVIC_IPR11;
446  __IO uint32_t NVIC_IPR12;
447  __IO uint32_t NVIC_IPR13;
448  __IO uint32_t NVIC_IPR14;
449  __IO uint32_t NVIC_IPR15;
450  __IO uint32_t NVIC_IPR16;
451  __IO uint32_t NVIC_IPR17;
452  __IO uint32_t NVIC_IPR18;
453  __IO uint32_t NVIC_IPR19;
454  __IO uint32_t NVIC_IPR20;
455  __IO uint32_t NVIC_IPR21;
456  __IO uint32_t NVIC_IPR22;
457  __IO uint32_t NVIC_IPR23;
458  __IO uint32_t NVIC_IPR24;
459  __IO uint32_t NVIC_IPR25;
460  __IO uint32_t NVIC_IPR26;
461  __IO uint32_t NVIC_IPR27;
462  __I uint32_t RESERVED8[548];
463  __I uint32_t CPUID;
464  __IO uint32_t ICSR;
465  __IO uint32_t VTOR;
466  __IO uint32_t AIRCR;
467  __IO uint32_t SCR;
468  __IO uint32_t CCR;
469  __IO uint32_t SHPR1;
470  __IO uint32_t SHPR2;
471  __IO uint32_t SHPR3;
472  __IO uint32_t SHCSR;
473  __IO uint32_t CFSR;
474  __IO uint32_t HFSR;
475  __I uint32_t RESERVED9;
476  __IO uint32_t MMFAR;
477  __IO uint32_t BFAR;
478  __IO uint32_t AFSR;
479  __I uint32_t RESERVED10[18];
480  __IO uint32_t CPACR;
481  __I uint32_t RESERVED11;
482  __I uint32_t MPU_TYPE;
483  __IO uint32_t MPU_CTRL;
484  __IO uint32_t MPU_RNR;
485  __IO uint32_t MPU_RBAR;
486  __IO uint32_t MPU_RASR;
487  __IO uint32_t MPU_RBAR_A1;
488  __IO uint32_t MPU_RASR_A1;
489  __IO uint32_t MPU_RBAR_A2;
490  __IO uint32_t MPU_RASR_A2;
491  __IO uint32_t MPU_RBAR_A3;
492  __IO uint32_t MPU_RASR_A3;
493  __I uint32_t RESERVED12[81];
494  __O uint32_t STIR;
495  __I uint32_t RESERVED13[12];
496  __IO uint32_t FPCCR;
497  __IO uint32_t FPCAR;
498  __IO uint32_t FPDSCR;
499 } PPB_Type;
500 
501 
502 /* ================================================================================ */
503 /* ================ DLR ================ */
504 /* ================================================================================ */
505 
506 
511 typedef struct {
512  __I uint32_t OVRSTAT;
513  __O uint32_t OVRCLR;
514  __IO uint32_t SRSEL0;
515  __IO uint32_t SRSEL1;
516  __IO uint32_t LNEN;
517 } DLR_GLOBAL_TypeDef;
518 
519 
520 /* ================================================================================ */
521 /* ================ ERU [ERU0] ================ */
522 /* ================================================================================ */
523 
524 
529 typedef struct {
530  __IO uint32_t EXISEL;
531  __I uint32_t RESERVED[3];
532  __IO uint32_t EXICON[4];
533  __IO uint32_t EXOCON[4];
534 } ERU_GLOBAL_TypeDef;
535 
536 
537 /* ================================================================================ */
538 /* ================ GPDMA0 ================ */
539 /* ================================================================================ */
540 
541 
546 typedef struct {
547  __IO uint32_t RAWTFR;
548  __I uint32_t RESERVED;
549  __IO uint32_t RAWBLOCK;
550  __I uint32_t RESERVED1;
551  __IO uint32_t RAWSRCTRAN;
552  __I uint32_t RESERVED2;
553  __IO uint32_t RAWDSTTRAN;
554  __I uint32_t RESERVED3;
555  __IO uint32_t RAWERR;
556  __I uint32_t RESERVED4;
557  __I uint32_t STATUSTFR;
558  __I uint32_t RESERVED5;
559  __I uint32_t STATUSBLOCK;
560  __I uint32_t RESERVED6;
561  __I uint32_t STATUSSRCTRAN;
562  __I uint32_t RESERVED7;
563  __I uint32_t STATUSDSTTRAN;
564  __I uint32_t RESERVED8;
565  __I uint32_t STATUSERR;
566  __I uint32_t RESERVED9;
567  __IO uint32_t MASKTFR;
568  __I uint32_t RESERVED10;
569  __IO uint32_t MASKBLOCK;
570  __I uint32_t RESERVED11;
571  __IO uint32_t MASKSRCTRAN;
572  __I uint32_t RESERVED12;
573  __IO uint32_t MASKDSTTRAN;
574  __I uint32_t RESERVED13;
575  __IO uint32_t MASKERR;
576  __I uint32_t RESERVED14;
577  __O uint32_t CLEARTFR;
578  __I uint32_t RESERVED15;
579  __O uint32_t CLEARBLOCK;
580  __I uint32_t RESERVED16;
581  __O uint32_t CLEARSRCTRAN;
582  __I uint32_t RESERVED17;
583  __O uint32_t CLEARDSTTRAN;
584  __I uint32_t RESERVED18;
585  __O uint32_t CLEARERR;
586  __I uint32_t RESERVED19;
587  __I uint32_t STATUSINT;
588  __I uint32_t RESERVED20;
589  __IO uint32_t REQSRCREG;
590  __I uint32_t RESERVED21;
591  __IO uint32_t REQDSTREG;
592  __I uint32_t RESERVED22;
593  __IO uint32_t SGLREQSRCREG;
594  __I uint32_t RESERVED23;
595  __IO uint32_t SGLREQDSTREG;
596  __I uint32_t RESERVED24;
597  __IO uint32_t LSTSRCREG;
598  __I uint32_t RESERVED25;
599  __IO uint32_t LSTDSTREG;
600  __I uint32_t RESERVED26;
601  __IO uint32_t DMACFGREG;
602  __I uint32_t RESERVED27;
603  __IO uint32_t CHENREG;
604  __I uint32_t RESERVED28;
605  __I uint32_t ID;
606  __I uint32_t RESERVED29[19];
607  __I uint32_t TYPE;
608  __I uint32_t VERSION;
609 } GPDMA0_GLOBAL_TypeDef;
610 
611 
612 /* ================================================================================ */
613 /* ================ GPDMA0_CH0_1 [GPDMA0_CH0] ================ */
614 /* ================================================================================ */
615 
616 
621 typedef struct {
622  __IO uint32_t SAR;
623  __I uint32_t RESERVED;
624  __IO uint32_t DAR;
625  __I uint32_t RESERVED1;
626  __IO uint32_t LLP;
627  __I uint32_t RESERVED2;
628  __IO uint32_t CTLL;
629  __IO uint32_t CTLH;
630  __IO uint32_t SSTAT;
631  __I uint32_t RESERVED3;
632  __IO uint32_t DSTAT;
633  __I uint32_t RESERVED4;
634  __IO uint32_t SSTATAR;
635  __I uint32_t RESERVED5;
636  __IO uint32_t DSTATAR;
637  __I uint32_t RESERVED6;
638  __IO uint32_t CFGL;
639  __IO uint32_t CFGH;
640  __IO uint32_t SGR;
641  __I uint32_t RESERVED7;
642  __IO uint32_t DSR;
643 } GPDMA0_CH_TypeDef;
644 
645 
646 /* ================================================================================ */
647 /* ================ GPDMA0_CH2_7 [GPDMA0_CH2] ================ */
648 /* ================================================================================ */
649 
650 
655 typedef struct {
656  __IO uint32_t SAR;
657  __I uint32_t RESERVED;
658  __IO uint32_t DAR;
659  __I uint32_t RESERVED1[3];
660  __IO uint32_t CTLL;
661  __IO uint32_t CTLH;
662  __I uint32_t RESERVED2[8];
663  __IO uint32_t CFGL;
664  __IO uint32_t CFGH;
665 } GPDMA0_CH2_7_Type;
666 
667 
668 /* ================================================================================ */
669 /* ================ GPDMA1 ================ */
670 /* ================================================================================ */
671 
672 
677 typedef struct {
678  __IO uint32_t RAWTFR;
679  __I uint32_t RESERVED;
680  __IO uint32_t RAWBLOCK;
681  __I uint32_t RESERVED1;
682  __IO uint32_t RAWSRCTRAN;
683  __I uint32_t RESERVED2;
684  __IO uint32_t RAWDSTTRAN;
685  __I uint32_t RESERVED3;
686  __IO uint32_t RAWERR;
687  __I uint32_t RESERVED4;
688  __I uint32_t STATUSTFR;
689  __I uint32_t RESERVED5;
690  __I uint32_t STATUSBLOCK;
691  __I uint32_t RESERVED6;
692  __I uint32_t STATUSSRCTRAN;
693  __I uint32_t RESERVED7;
694  __I uint32_t STATUSDSTTRAN;
695  __I uint32_t RESERVED8;
696  __I uint32_t STATUSERR;
697  __I uint32_t RESERVED9;
698  __IO uint32_t MASKTFR;
699  __I uint32_t RESERVED10;
700  __IO uint32_t MASKBLOCK;
701  __I uint32_t RESERVED11;
702  __IO uint32_t MASKSRCTRAN;
703  __I uint32_t RESERVED12;
704  __IO uint32_t MASKDSTTRAN;
705  __I uint32_t RESERVED13;
706  __IO uint32_t MASKERR;
707  __I uint32_t RESERVED14;
708  __O uint32_t CLEARTFR;
709  __I uint32_t RESERVED15;
710  __O uint32_t CLEARBLOCK;
711  __I uint32_t RESERVED16;
712  __O uint32_t CLEARSRCTRAN;
713  __I uint32_t RESERVED17;
714  __O uint32_t CLEARDSTTRAN;
715  __I uint32_t RESERVED18;
716  __O uint32_t CLEARERR;
717  __I uint32_t RESERVED19;
718  __I uint32_t STATUSINT;
719  __I uint32_t RESERVED20;
720  __IO uint32_t REQSRCREG;
721  __I uint32_t RESERVED21;
722  __IO uint32_t REQDSTREG;
723  __I uint32_t RESERVED22;
724  __IO uint32_t SGLREQSRCREG;
725  __I uint32_t RESERVED23;
726  __IO uint32_t SGLREQDSTREG;
727  __I uint32_t RESERVED24;
728  __IO uint32_t LSTSRCREG;
729  __I uint32_t RESERVED25;
730  __IO uint32_t LSTDSTREG;
731  __I uint32_t RESERVED26;
732  __IO uint32_t DMACFGREG;
733  __I uint32_t RESERVED27;
734  __IO uint32_t CHENREG;
735  __I uint32_t RESERVED28;
736  __I uint32_t ID;
737  __I uint32_t RESERVED29[19];
738  __I uint32_t TYPE;
739  __I uint32_t VERSION;
740 } GPDMA1_GLOBAL_TypeDef;
741 
742 
743 /* ================================================================================ */
744 /* ================ GPDMA1_CH [GPDMA1_CH0] ================ */
745 /* ================================================================================ */
746 
747 
752 typedef struct {
753  __IO uint32_t SAR;
754  __I uint32_t RESERVED;
755  __IO uint32_t DAR;
756  __I uint32_t RESERVED1[3];
757  __IO uint32_t CTLL;
758  __IO uint32_t CTLH;
759  __I uint32_t RESERVED2[8];
760  __IO uint32_t CFGL;
761  __IO uint32_t CFGH;
762 } GPDMA1_CH_TypeDef;
763 
764 
765 /* ================================================================================ */
766 /* ================ FCE ================ */
767 /* ================================================================================ */
768 
769 
774 typedef struct {
775  __IO uint32_t CLC;
776  __I uint32_t RESERVED;
777  __I uint32_t ID;
778 } FCE_GLOBAL_TypeDef;
779 
780 
781 /* ================================================================================ */
782 /* ================ FCE_KE [FCE_KE0] ================ */
783 /* ================================================================================ */
784 
785 
790 typedef struct {
791  __IO uint32_t IR;
792  __I uint32_t RES;
793  __IO uint32_t CFG;
794  __IO uint32_t STS;
795  __IO uint32_t LENGTH;
796  __IO uint32_t CHECK;
797  __IO uint32_t CRC;
798  __IO uint32_t CTR;
799 } FCE_KE_TypeDef;
800 
801 
802 /* ================================================================================ */
803 /* ================ PBA [PBA0] ================ */
804 /* ================================================================================ */
805 
806 
811 typedef struct {
812  __IO uint32_t STS;
813  __I uint32_t WADDR;
814 } PBA_GLOBAL_TypeDef;
815 
816 
817 /* ================================================================================ */
818 /* ================ FLASH [FLASH0] ================ */
819 /* ================================================================================ */
820 
821 
826 typedef struct {
827  __I uint32_t RESERVED[1026];
828  __I uint32_t ID;
829  __I uint32_t RESERVED1;
830  __I uint32_t FSR;
831  __IO uint32_t FCON;
832  __IO uint32_t MARP;
833  __I uint32_t RESERVED2;
834  __I uint32_t PROCON0;
836  __I uint32_t PROCON1;
838  __I uint32_t PROCON2;
840 } FLASH0_GLOBAL_TypeDef;
841 
842 
843 /* ================================================================================ */
844 /* ================ PREF ================ */
845 /* ================================================================================ */
846 
847 
852 typedef struct {
853  __IO uint32_t PCON;
854 } PREF_GLOBAL_TypeDef;
855 
856 
857 /* ================================================================================ */
858 /* ================ PMU [PMU0] ================ */
859 /* ================================================================================ */
860 
861 
866 typedef struct {
867  __I uint32_t ID;
868 } PMU0_GLOBAL_TypeDef;
869 
870 
871 /* ================================================================================ */
872 /* ================ WDT ================ */
873 /* ================================================================================ */
874 
875 
880 typedef struct {
881  __I uint32_t ID;
882  __IO uint32_t CTR;
883  __O uint32_t SRV;
884  __I uint32_t TIM;
885  __IO uint32_t WLB;
886  __IO uint32_t WUB;
887  __I uint32_t WDTSTS;
888  __O uint32_t WDTCLR;
889 } WDT_GLOBAL_TypeDef;
890 
891 
892 /* ================================================================================ */
893 /* ================ RTC ================ */
894 /* ================================================================================ */
895 
896 
901 typedef struct {
902  __I uint32_t ID;
903  __IO uint32_t CTR;
904  __I uint32_t RAWSTAT;
905  __I uint32_t STSSR;
906  __IO uint32_t MSKSR;
907  __O uint32_t CLRSR;
908  __IO uint32_t ATIM0;
909  __IO uint32_t ATIM1;
910  __IO uint32_t TIM0;
911  __IO uint32_t TIM1;
912 } RTC_GLOBAL_TypeDef;
913 
914 
915 /* ================================================================================ */
916 /* ================ SCU_CLK ================ */
917 /* ================================================================================ */
918 
919 
924 typedef struct {
925  __I uint32_t CLKSTAT;
926  __O uint32_t CLKSET;
927  __O uint32_t CLKCLR;
928  __IO uint32_t SYSCLKCR;
929  __IO uint32_t CPUCLKCR;
930  __IO uint32_t PBCLKCR;
931  __IO uint32_t USBCLKCR;
932  __IO uint32_t EBUCLKCR;
933  __IO uint32_t CCUCLKCR;
934  __IO uint32_t WDTCLKCR;
935  __IO uint32_t EXTCLKCR;
936  __IO uint32_t MLINKCLKCR;
937  __IO uint32_t SLEEPCR;
938  __IO uint32_t DSLEEPCR;
939  __IO uint32_t ECATCLKCR;
940  __I uint32_t RESERVED;
941  __I uint32_t CGATSTAT0;
942  __O uint32_t CGATSET0;
943  __O uint32_t CGATCLR0;
944  __I uint32_t CGATSTAT1;
945  __O uint32_t CGATSET1;
946  __O uint32_t CGATCLR1;
947  __I uint32_t CGATSTAT2;
948  __O uint32_t CGATSET2;
949  __O uint32_t CGATCLR2;
950  __I uint32_t CGATSTAT3;
951  __O uint32_t CGATSET3;
952  __O uint32_t CGATCLR3;
953 } SCU_CLK_TypeDef;
954 
955 
956 /* ================================================================================ */
957 /* ================ SCU_OSC ================ */
958 /* ================================================================================ */
959 
960 
965 typedef struct {
966  __I uint32_t OSCHPSTAT;
967  __IO uint32_t OSCHPCTRL;
968  __I uint32_t RESERVED;
969  __IO uint32_t CLKCALCONST;
970 } SCU_OSC_TypeDef;
971 
972 
973 /* ================================================================================ */
974 /* ================ SCU_PLL ================ */
975 /* ================================================================================ */
976 
977 
982 typedef struct {
983  __I uint32_t PLLSTAT;
984  __IO uint32_t PLLCON0;
985  __IO uint32_t PLLCON1;
986  __IO uint32_t PLLCON2;
987  __I uint32_t USBPLLSTAT;
988  __IO uint32_t USBPLLCON;
989  __I uint32_t RESERVED[4];
990  __I uint32_t CLKMXSTAT;
991 } SCU_PLL_TypeDef;
992 
993 
994 /* ================================================================================ */
995 /* ================ SCU_GENERAL ================ */
996 /* ================================================================================ */
997 
998 
1003 typedef struct {
1004  __I uint32_t ID;
1005  __I uint32_t IDCHIP;
1006  __I uint32_t IDMANUF;
1007  __I uint32_t RESERVED;
1008  __IO uint32_t STCON;
1009  __I uint32_t RESERVED1[6];
1010  __IO uint32_t GPR[2];
1011  __I uint32_t RESERVED2[6];
1012  __IO uint32_t CCUCON;
1013  __I uint32_t RESERVED3[15];
1014  __IO uint32_t DTSCON;
1015  __I uint32_t DTSSTAT;
1016  __I uint32_t RESERVED4[2];
1017  __IO uint32_t SDMMCDEL;
1018  __IO uint32_t GORCEN[2];
1019  __I uint32_t RESERVED5[7];
1020  __I uint32_t MIRRSTS;
1021  __IO uint32_t RMACR;
1022  __IO uint32_t RMDATA;
1023 } SCU_GENERAL_TypeDef;
1024 
1025 
1026 /* ================================================================================ */
1027 /* ================ SCU_INTERRUPT ================ */
1028 /* ================================================================================ */
1029 
1030 
1035 typedef struct {
1036  __I uint32_t SRSTAT;
1037  __I uint32_t SRRAW;
1038  __IO uint32_t SRMSK;
1039  __O uint32_t SRCLR;
1040  __O uint32_t SRSET;
1041  __IO uint32_t NMIREQEN;
1042 } SCU_INTERRUPT_TypeDef;
1043 
1044 
1045 /* ================================================================================ */
1046 /* ================ SCU_PARITY ================ */
1047 /* ================================================================================ */
1048 
1049 
1054 typedef struct {
1055  __IO uint32_t PEEN;
1056  __IO uint32_t MCHKCON;
1057  __IO uint32_t PETE;
1058  __IO uint32_t PERSTEN;
1059  __I uint32_t RESERVED;
1060  __IO uint32_t PEFLAG;
1061  __IO uint32_t PMTPR;
1062  __IO uint32_t PMTSR;
1063 } SCU_PARITY_TypeDef;
1064 
1065 
1066 /* ================================================================================ */
1067 /* ================ SCU_TRAP ================ */
1068 /* ================================================================================ */
1069 
1070 
1075 typedef struct {
1076  __I uint32_t TRAPSTAT;
1077  __I uint32_t TRAPRAW;
1078  __IO uint32_t TRAPDIS;
1079  __O uint32_t TRAPCLR;
1080  __O uint32_t TRAPSET;
1081 } SCU_TRAP_TypeDef;
1082 
1083 
1084 /* ================================================================================ */
1085 /* ================ SCU_HIBERNATE ================ */
1086 /* ================================================================================ */
1087 
1088 
1093 typedef struct {
1094  __I uint32_t HDSTAT;
1095  __O uint32_t HDCLR;
1096  __O uint32_t HDSET;
1097  __IO uint32_t HDCR;
1098  __I uint32_t RESERVED;
1099  __IO uint32_t OSCSICTRL;
1100  __I uint32_t OSCULSTAT;
1101  __IO uint32_t OSCULCTRL;
1102 } SCU_HIBERNATE_TypeDef;
1103 
1104 
1105 /* ================================================================================ */
1106 /* ================ SCU_POWER ================ */
1107 /* ================================================================================ */
1108 
1109 
1114 typedef struct {
1115  __I uint32_t PWRSTAT;
1116  __O uint32_t PWRSET;
1117  __O uint32_t PWRCLR;
1118  __I uint32_t RESERVED;
1119  __I uint32_t EVRSTAT;
1120  __I uint32_t EVRVADCSTAT;
1121  __I uint32_t RESERVED1[5];
1122  __IO uint32_t PWRMON;
1123 } SCU_POWER_TypeDef;
1124 
1125 
1126 /* ================================================================================ */
1127 /* ================ SCU_RESET ================ */
1128 /* ================================================================================ */
1129 
1130 
1135 typedef struct {
1136  __I uint32_t RSTSTAT;
1137  __O uint32_t RSTSET;
1138  __O uint32_t RSTCLR;
1139  __I uint32_t PRSTAT0;
1140  __O uint32_t PRSET0;
1141  __O uint32_t PRCLR0;
1142  __I uint32_t PRSTAT1;
1143  __O uint32_t PRSET1;
1144  __O uint32_t PRCLR1;
1145  __I uint32_t PRSTAT2;
1146  __O uint32_t PRSET2;
1147  __O uint32_t PRCLR2;
1148  __I uint32_t PRSTAT3;
1149  __O uint32_t PRSET3;
1150  __O uint32_t PRCLR3;
1151 } SCU_RESET_TypeDef;
1152 
1153 
1154 /* ================================================================================ */
1155 /* ================ LEDTS [LEDTS0] ================ */
1156 /* ================================================================================ */
1157 
1158 
1163 typedef struct {
1164  __I uint32_t ID;
1165  __IO uint32_t GLOBCTL;
1166  __IO uint32_t FNCTL;
1167  __O uint32_t EVFR;
1168  __IO uint32_t TSVAL;
1169  __IO uint32_t LINE0;
1170  __IO uint32_t LINE1;
1171  __IO uint32_t LDCMP0;
1172  __IO uint32_t LDCMP1;
1173  __IO uint32_t TSCMP0;
1174  __IO uint32_t TSCMP1;
1175 } LEDTS0_GLOBAL_TypeDef;
1176 
1177 
1178 /* ================================================================================ */
1179 /* ================ SDMMC_CON ================ */
1180 /* ================================================================================ */
1181 
1182 
1187 typedef struct {
1188  __IO uint32_t SDMMC_CON;
1189 } SDMMC_CON_Type;
1190 
1191 
1192 /* ================================================================================ */
1193 /* ================ SDMMC ================ */
1194 /* ================================================================================ */
1195 
1196 
1201 typedef struct {
1202  __I uint32_t RESERVED;
1203  __IO uint16_t BLOCK_SIZE;
1204  __IO uint16_t BLOCK_COUNT;
1205  __IO uint32_t ARGUMENT1;
1206  __IO uint16_t TRANSFER_MODE;
1207  __IO uint16_t COMMAND;
1208  __I uint32_t RESPONSE0;
1209  __I uint32_t RESPONSE2;
1210  __I uint32_t RESPONSE4;
1211  __I uint32_t RESPONSE6;
1212  __IO uint32_t DATA_BUFFER;
1213  __I uint32_t PRESENT_STATE;
1214  __IO uint8_t HOST_CTRL;
1215  __IO uint8_t POWER_CTRL;
1216  __IO uint8_t BLOCK_GAP_CTRL;
1217  __IO uint8_t WAKEUP_CTRL;
1218  __IO uint16_t CLOCK_CTRL;
1219  __IO uint8_t TIMEOUT_CTRL;
1220  __IO uint8_t SW_RESET;
1221  __IO uint16_t INT_STATUS_NORM;
1222  __IO uint16_t INT_STATUS_ERR;
1223  __IO uint16_t EN_INT_STATUS_NORM;
1224  __IO uint16_t EN_INT_STATUS_ERR;
1225  __IO uint16_t EN_INT_SIGNAL_NORM;
1226  __IO uint16_t EN_INT_SIGNAL_ERR;
1227  __I uint16_t ACMD_ERR_STATUS;
1228  __I uint16_t RESERVED1;
1229  __I uint32_t CAPABILITIES;
1230  __I uint32_t CAPABILITIES_HI;
1231  __I uint32_t MAX_CURRENT_CAP;
1232  __I uint32_t RESERVED2;
1233  __O uint16_t FORCE_EVENT_ACMD_ERR_STATUS;
1234  __O uint16_t FORCE_EVENT_ERR_STATUS;
1235  __I uint32_t RESERVED3[8];
1236  __O uint32_t DEBUG_SEL;
1237  __I uint32_t RESERVED4[33];
1238  __I uint16_t SLOT_INT_STATUS;
1239 } SDMMC_GLOBAL_TypeDef;
1240 
1241 
1242 /* ================================================================================ */
1243 /* ================ EBU ================ */
1244 /* ================================================================================ */
1245 
1246 
1251 typedef struct {
1252  __IO uint32_t CLC;
1253  __IO uint32_t MODCON;
1254  __I uint32_t ID;
1255  __IO uint32_t USERCON;
1256  __I uint32_t RESERVED[2];
1257  __IO uint32_t ADDRSEL0;
1258  __IO uint32_t ADDRSEL1;
1259  __IO uint32_t ADDRSEL2;
1260  __IO uint32_t ADDRSEL3;
1261  __IO uint32_t BUSRCON0;
1262  __IO uint32_t BUSRAP0;
1263  __IO uint32_t BUSWCON0;
1264  __IO uint32_t BUSWAP0;
1265  __IO uint32_t BUSRCON1;
1266  __IO uint32_t BUSRAP1;
1267  __IO uint32_t BUSWCON1;
1268  __IO uint32_t BUSWAP1;
1269  __IO uint32_t BUSRCON2;
1270  __IO uint32_t BUSRAP2;
1271  __IO uint32_t BUSWCON2;
1272  __IO uint32_t BUSWAP2;
1273  __IO uint32_t BUSRCON3;
1274  __IO uint32_t BUSRAP3;
1275  __IO uint32_t BUSWCON3;
1276  __IO uint32_t BUSWAP3;
1277  __IO uint32_t SDRMCON;
1278  __IO uint32_t SDRMOD;
1279  __IO uint32_t SDRMREF;
1280  __I uint32_t SDRSTAT;
1281 } EBU_Type;
1282 
1283 
1284 /* ================================================================================ */
1285 /* ================ ETH0_CON ================ */
1286 /* ================================================================================ */
1287 
1288 
1293 typedef struct {
1294  __IO uint32_t CON;
1295 } ETH0_CON_GLOBAL_TypeDef;
1296 
1297 
1298 /* ================================================================================ */
1299 /* ================ ETH [ETH0] ================ */
1300 /* ================================================================================ */
1301 
1302 
1307 typedef struct {
1308  __IO uint32_t MAC_CONFIGURATION;
1309  __IO uint32_t MAC_FRAME_FILTER;
1310  __IO uint32_t HASH_TABLE_HIGH;
1311  __IO uint32_t HASH_TABLE_LOW;
1312  __IO uint32_t GMII_ADDRESS;
1313  __IO uint32_t GMII_DATA;
1314  __IO uint32_t FLOW_CONTROL;
1315  __IO uint32_t VLAN_TAG;
1316  __I uint32_t VERSION;
1317  __I uint32_t DEBUG;
1318  __IO uint32_t REMOTE_WAKE_UP_FRAME_FILTER;
1319  __IO uint32_t PMT_CONTROL_STATUS;
1320  __I uint32_t RESERVED[2];
1321  __I uint32_t INTERRUPT_STATUS;
1322  __IO uint32_t INTERRUPT_MASK;
1323  __IO uint32_t MAC_ADDRESS0_HIGH;
1324  __IO uint32_t MAC_ADDRESS0_LOW;
1325  __IO uint32_t MAC_ADDRESS1_HIGH;
1326  __IO uint32_t MAC_ADDRESS1_LOW;
1327  __IO uint32_t MAC_ADDRESS2_HIGH;
1328  __IO uint32_t MAC_ADDRESS2_LOW;
1329  __IO uint32_t MAC_ADDRESS3_HIGH;
1330  __IO uint32_t MAC_ADDRESS3_LOW;
1331  __I uint32_t RESERVED1[40];
1332  __IO uint32_t MMC_CONTROL;
1333  __I uint32_t MMC_RECEIVE_INTERRUPT;
1334  __I uint32_t MMC_TRANSMIT_INTERRUPT;
1335  __IO uint32_t MMC_RECEIVE_INTERRUPT_MASK;
1336  __IO uint32_t MMC_TRANSMIT_INTERRUPT_MASK;
1337  __I uint32_t TX_OCTET_COUNT_GOOD_BAD;
1339  __I uint32_t TX_FRAME_COUNT_GOOD_BAD;
1340  __I uint32_t TX_BROADCAST_FRAMES_GOOD;
1341  __I uint32_t TX_MULTICAST_FRAMES_GOOD;
1342  __I uint32_t TX_64OCTETS_FRAMES_GOOD_BAD;
1344  __I uint32_t TX_65TO127OCTETS_FRAMES_GOOD_BAD;
1346  __I uint32_t TX_128TO255OCTETS_FRAMES_GOOD_BAD;
1348  __I uint32_t TX_256TO511OCTETS_FRAMES_GOOD_BAD;
1350  __I uint32_t TX_512TO1023OCTETS_FRAMES_GOOD_BAD;
1352  __I uint32_t TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;
1354  __I uint32_t TX_UNICAST_FRAMES_GOOD_BAD;
1356  __I uint32_t TX_MULTICAST_FRAMES_GOOD_BAD;
1358  __I uint32_t TX_BROADCAST_FRAMES_GOOD_BAD;
1360  __I uint32_t TX_UNDERFLOW_ERROR_FRAMES;
1361  __I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES;
1363  __I uint32_t TX_MULTIPLE_COLLISION_GOOD_FRAMES;
1365  __I uint32_t TX_DEFERRED_FRAMES;
1366  __I uint32_t TX_LATE_COLLISION_FRAMES;
1368  __I uint32_t TX_EXCESSIVE_COLLISION_FRAMES;
1370  __I uint32_t TX_CARRIER_ERROR_FRAMES;
1372  __I uint32_t TX_OCTET_COUNT_GOOD;
1373  __I uint32_t TX_FRAME_COUNT_GOOD;
1374  __I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR;
1376  __I uint32_t TX_PAUSE_FRAMES;
1377  __I uint32_t TX_VLAN_FRAMES_GOOD;
1378  __I uint32_t TX_OSIZE_FRAMES_GOOD;
1379  __I uint32_t RESERVED2;
1380  __I uint32_t RX_FRAMES_COUNT_GOOD_BAD;
1381  __I uint32_t RX_OCTET_COUNT_GOOD_BAD;
1382  __I uint32_t RX_OCTET_COUNT_GOOD;
1383  __I uint32_t RX_BROADCAST_FRAMES_GOOD;
1384  __I uint32_t RX_MULTICAST_FRAMES_GOOD;
1385  __I uint32_t RX_CRC_ERROR_FRAMES;
1386  __I uint32_t RX_ALIGNMENT_ERROR_FRAMES;
1387  __I uint32_t RX_RUNT_ERROR_FRAMES;
1388  __I uint32_t RX_JABBER_ERROR_FRAMES;
1389  __I uint32_t RX_UNDERSIZE_FRAMES_GOOD;
1390  __I uint32_t RX_OVERSIZE_FRAMES_GOOD;
1391  __I uint32_t RX_64OCTETS_FRAMES_GOOD_BAD;
1393  __I uint32_t RX_65TO127OCTETS_FRAMES_GOOD_BAD;
1395  __I uint32_t RX_128TO255OCTETS_FRAMES_GOOD_BAD;
1397  __I uint32_t RX_256TO511OCTETS_FRAMES_GOOD_BAD;
1399  __I uint32_t RX_512TO1023OCTETS_FRAMES_GOOD_BAD;
1401  __I uint32_t RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD;
1403  __I uint32_t RX_UNICAST_FRAMES_GOOD;
1404  __I uint32_t RX_LENGTH_ERROR_FRAMES;
1405  __I uint32_t RX_OUT_OF_RANGE_TYPE_FRAMES;
1406  __I uint32_t RX_PAUSE_FRAMES;
1407  __I uint32_t RX_FIFO_OVERFLOW_FRAMES;
1408  __I uint32_t RX_VLAN_FRAMES_GOOD_BAD;
1409  __I uint32_t RX_WATCHDOG_ERROR_FRAMES;
1410  __I uint32_t RX_RECEIVE_ERROR_FRAMES;
1411  __I uint32_t RX_CONTROL_FRAMES_GOOD;
1412  __I uint32_t RESERVED3[6];
1413  __IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK;
1414  __I uint32_t RESERVED4;
1415  __I uint32_t MMC_IPC_RECEIVE_INTERRUPT;
1416  __I uint32_t RESERVED5;
1417  __I uint32_t RXIPV4_GOOD_FRAMES;
1418  __I uint32_t RXIPV4_HEADER_ERROR_FRAMES;
1419  __I uint32_t RXIPV4_NO_PAYLOAD_FRAMES;
1420  __I uint32_t RXIPV4_FRAGMENTED_FRAMES;
1421  __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES;
1423  __I uint32_t RXIPV6_GOOD_FRAMES;
1424  __I uint32_t RXIPV6_HEADER_ERROR_FRAMES;
1425  __I uint32_t RXIPV6_NO_PAYLOAD_FRAMES;
1426  __I uint32_t RXUDP_GOOD_FRAMES;
1427  __I uint32_t RXUDP_ERROR_FRAMES;
1428  __I uint32_t RXTCP_GOOD_FRAMES;
1429  __I uint32_t RXTCP_ERROR_FRAMES;
1430  __I uint32_t RXICMP_GOOD_FRAMES;
1431  __I uint32_t RXICMP_ERROR_FRAMES;
1432  __I uint32_t RESERVED6[2];
1433  __I uint32_t RXIPV4_GOOD_OCTETS;
1434  __I uint32_t RXIPV4_HEADER_ERROR_OCTETS;
1435  __I uint32_t RXIPV4_NO_PAYLOAD_OCTETS;
1436  __I uint32_t RXIPV4_FRAGMENTED_OCTETS;
1437  __I uint32_t RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS;
1438  __I uint32_t RXIPV6_GOOD_OCTETS;
1439  __I uint32_t RXIPV6_HEADER_ERROR_OCTETS;
1440  __I uint32_t RXIPV6_NO_PAYLOAD_OCTETS;
1441  __I uint32_t RXUDP_GOOD_OCTETS;
1442  __I uint32_t RXUDP_ERROR_OCTETS;
1443  __I uint32_t RXTCP_GOOD_OCTETS;
1444  __I uint32_t RXTCP_ERROR_OCTETS;
1445  __I uint32_t RXICMP_GOOD_OCTETS;
1446  __I uint32_t RXICMP_ERROR_OCTETS;
1447  __I uint32_t RESERVED7[286];
1448  __IO uint32_t TIMESTAMP_CONTROL;
1449  __IO uint32_t SUB_SECOND_INCREMENT;
1450  __I uint32_t SYSTEM_TIME_SECONDS;
1451  __I uint32_t SYSTEM_TIME_NANOSECONDS;
1452  __IO uint32_t SYSTEM_TIME_SECONDS_UPDATE;
1453  __IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE;
1454  __IO uint32_t TIMESTAMP_ADDEND;
1455  __IO uint32_t TARGET_TIME_SECONDS;
1456  __IO uint32_t TARGET_TIME_NANOSECONDS;
1457  __IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS;
1458  __I uint32_t TIMESTAMP_STATUS;
1459  __I uint32_t RESERVED8[565];
1460  __IO uint32_t BUS_MODE;
1461  __IO uint32_t TRANSMIT_POLL_DEMAND;
1462  __IO uint32_t RECEIVE_POLL_DEMAND;
1463  __IO uint32_t RECEIVE_DESCRIPTOR_LIST_ADDRESS;
1464  __IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS;
1465  __IO uint32_t STATUS;
1466  __IO uint32_t OPERATION_MODE;
1467  __IO uint32_t INTERRUPT_ENABLE;
1468  __I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER;
1469  __IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER;
1470  __I uint32_t RESERVED9;
1471  __I uint32_t AHB_STATUS;
1472  __I uint32_t RESERVED10[6];
1473  __I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR;
1474  __I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR;
1475  __I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS;
1476  __I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS;
1477  __IO uint32_t HW_FEATURE;
1478 } ETH_GLOBAL_TypeDef;
1479 
1480 
1481 /* ================================================================================ */
1482 /* ================ ECAT0_CON ================ */
1483 /* ================================================================================ */
1484 
1485 
1490 typedef struct {
1491  __IO uint32_t CON;
1492  __IO uint32_t CONP0;
1493  __IO uint32_t CONP1;
1494 } ECAT0_CON_Type;
1495 
1496 
1497 /* ================================================================================ */
1498 /* ================ ECAT [ECAT0] ================ */
1499 /* ================================================================================ */
1500 
1501 
1506 typedef struct {
1507  __I uint8_t TYPE;
1508  __I uint8_t REVISION;
1509  __I uint16_t BUILD;
1510  __I uint8_t FMMU_NUM;
1511  __I uint8_t SYNC_MANAGER;
1512  __I uint8_t RAM_SIZE;
1513  __I uint8_t PORT_DESC;
1514  __I uint16_t FEATURE;
1515  __I uint16_t RESERVED[3];
1516  __I uint16_t STATION_ADR;
1517  __IO uint16_t STATION_ALIAS;
1518  __I uint32_t RESERVED1[3];
1519  __I uint8_t WR_REG_ENABLE;
1520  __I uint8_t WR_REG_PROTECT;
1521  __I uint16_t RESERVED2[7];
1522  __I uint8_t ESC_WR_ENABLE;
1523  __I uint8_t ESC_WR_PROTECT;
1524  __I uint16_t RESERVED3[7];
1525 
1526  union {
1527  __I uint8_t ESC_RESET_ECAT_READMode;
1528  __I uint8_t ESC_RESET_ECAT_WRITEMode;
1529  };
1530 
1531  union {
1532  __I uint8_t ESC_RESET_PDI_READMode;
1533  __I uint8_t ESC_RESET_PDI_WRITEMode;
1534  };
1535  __I uint16_t RESERVED4[95];
1536  __I uint32_t ESC_DL_CONTROL;
1537  __I uint32_t RESERVED5;
1538  __I uint16_t PHYSICAL_RW_OFFSET;
1539  __I uint16_t RESERVED6[3];
1540  __I uint16_t ESC_DL_STATUS;
1541  __I uint16_t RESERVED7[7];
1542  __I uint16_t AL_CONTROL;
1543  __I uint16_t RESERVED8[7];
1544  __IO uint16_t AL_STATUS;
1545  __I uint16_t RESERVED9;
1546  __IO uint16_t AL_STATUS_CODE;
1547  __I uint16_t RESERVED10;
1548  __IO uint8_t RUN_LED;
1549  __IO uint8_t ERR_LED;
1550  __I uint16_t RESERVED11[3];
1551  __I uint8_t PDI_CONTROL;
1552  __I uint8_t ESC_CONFIG;
1553  __I uint16_t RESERVED12[7];
1554  __I uint8_t PDI_CONFIG;
1555  __I uint8_t SYNC_LATCH_CONFIG;
1556  __I uint16_t PDI_EXT_CONFIG;
1557  __I uint32_t RESERVED13[43];
1558  __I uint16_t EVENT_MASK;
1559  __I uint16_t RESERVED14;
1560  __IO uint32_t AL_EVENT_MASK;
1561  __I uint32_t RESERVED15[2];
1562  __I uint16_t EVENT_REQ;
1563  __I uint16_t RESERVED16[7];
1564  __IO uint32_t AL_EVENT_REQ;
1565  __I uint32_t RESERVED17[55];
1566  __I uint16_t RX_ERR_COUNT0;
1567  __I uint16_t RX_ERR_COUNT1;
1568  __I uint32_t RESERVED18;
1569  __I uint8_t FWD_RX_ERR_COUNT0;
1570  __I uint8_t FWD_RX_ERR_COUNT1;
1571  __I uint16_t RESERVED19;
1572  __I uint8_t PROC_ERR_COUNT;
1573  __I uint8_t PDI_ERR_COUNT;
1574  __I uint16_t RESERVED20;
1575  __I uint8_t LOST_LINK_COUNT0;
1576  __I uint8_t LOST_LINK_COUNT1;
1577  __I uint16_t RESERVED21[119];
1578  __IO uint16_t WD_DIVIDE;
1579  __I uint16_t RESERVED22[7];
1580  __IO uint16_t WD_TIME_PDI;
1581  __I uint16_t RESERVED23[7];
1582  __IO uint16_t WD_TIME_PDATA;
1583  __I uint16_t RESERVED24[15];
1584  __I uint16_t WD_STAT_PDATA;
1585  __I uint8_t WD_COUNT_PDATA;
1586  __I uint8_t WD_COUNT_PDI;
1587  __I uint32_t RESERVED25[47];
1588  __I uint8_t EEP_CONF;
1589  __IO uint8_t EEP_STATE;
1590  __IO uint16_t EEP_CONT_STAT;
1591  __IO uint32_t EEP_ADR;
1592  __IO uint32_t EEP_DATA[2];
1593  __IO uint16_t MII_CONT_STAT;
1594  __IO uint8_t MII_PHY_ADR;
1595  __IO uint8_t MII_PHY_REG_ADR;
1596  __IO uint16_t MII_PHY_DATA;
1597  __I uint8_t MII_ECAT_ACS_STATE;
1598  __IO uint8_t MII_PDI_ACS_STATE;
1599  __I uint32_t RESERVED26[250];
1600  __I uint32_t DC_RCV_TIME_PORT0;
1601  __I uint32_t DC_RCV_TIME_PORT1;
1602  __I uint32_t RESERVED27[2];
1603 
1604  union {
1605  __I uint32_t READMode_DC_SYS_TIME[2];
1606  __O uint32_t DC_SYS_TIME_WRITEMode;
1607  };
1608  __I uint32_t RECEIVE_TIME_PU[2];
1609  __IO uint32_t DC_SYS_TIME_OFFSET[2];
1610  __IO uint32_t DC_SYS_TIME_DELAY;
1611  __I uint32_t DC_SYS_TIME_DIFF;
1612  __IO uint16_t DC_SPEED_COUNT_START;
1613  __I uint16_t DC_SPEED_COUNT_DIFF;
1614  __IO uint8_t DC_SYS_TIME_FIL_DEPTH;
1615  __IO uint8_t DC_SPEED_COUNT_FIL_DEPTH;
1616  __I uint16_t RESERVED28[37];
1617  __I uint8_t DC_CYC_CONT;
1618  __IO uint8_t DC_ACT;
1619  __I uint16_t DC_PULSE_LEN;
1620  __I uint8_t DC_ACT_STAT;
1621  __I uint8_t RESERVED29[9];
1622  __I uint8_t DC_SYNC0_STAT;
1623  __I uint8_t DC_SYNC1_STAT;
1624  __IO uint32_t DC_CYC_START_TIME[2];
1625  __I uint32_t DC_NEXT_SYNC1_PULSE[2];
1626  __IO uint32_t DC_SYNC0_CYC_TIME;
1627  __IO uint32_t DC_SYNC1_CYC_TIME;
1628  __IO uint8_t DC_LATCH0_CONT;
1629  __IO uint8_t DC_LATCH1_CONT;
1630  __I uint32_t RESERVED30;
1631  __I uint8_t DC_LATCH0_STAT;
1632  __I uint8_t DC_LATCH1_STAT;
1633  __I uint32_t DC_LATCH0_TIME_POS[2];
1635  __I uint32_t DC_LATCH0_TIME_NEG[2];
1637  __I uint32_t DC_LATCH1_TIME_POS[2];
1639  __I uint32_t DC_LATCH1_TIME_NEG[2];
1641  __I uint32_t RESERVED31[8];
1642  __I uint32_t DC_ECAT_CNG_EV_TIME;
1643  __I uint32_t RESERVED32;
1644  __I uint32_t DC_PDI_START_EV_TIME;
1645  __I uint32_t DC_PDI_CNG_EV_TIME;
1646  __I uint32_t RESERVED33[256];
1647  __I uint32_t ID;
1648  __I uint32_t RESERVED34;
1649  __I uint32_t STATUS;
1650 } ECAT_Type;
1651 
1652 
1653 /* ================================================================================ */
1654 /* ================ ECAT0_FMMU [ECAT0_FMMU0] ================ */
1655 /* ================================================================================ */
1656 
1657 
1662 typedef struct {
1663  __I uint32_t FMMU_L_START_ADR;
1664  __I uint16_t FMMU_LEN;
1665  __I uint8_t FMMU_L_START_BIT;
1666  __I uint8_t FMMU_L_STOP_BIT;
1667  __I uint16_t FMMU_P_START_ADR;
1668  __I uint8_t FMMU_P_START_BIT;
1669  __I uint8_t FMMU_TYPE;
1670  __I uint8_t FMMU_ACT;
1671 } ECAT0_FMMU_Type;
1672 
1673 
1674 /* ================================================================================ */
1675 /* ================ ECAT0_SM [ECAT0_SM0] ================ */
1676 /* ================================================================================ */
1677 
1678 
1683 typedef struct {
1684  __I uint16_t SM_P_START_ADR;
1685  __I uint16_t SM_LEN;
1686  __I uint8_t SM_CONTROL;
1687  __I uint8_t SM_STATUS;
1688  __I uint8_t SM_ACT;
1689  __IO uint8_t SM_PDI_CTR;
1690 } ECAT0_SM_Type;
1691 
1692 
1693 /* ================================================================================ */
1694 /* ================ USB [USB0] ================ */
1695 /* ================================================================================ */
1696 
1697 
1702 typedef struct {
1703  __IO uint32_t GOTGCTL;
1704  __IO uint32_t GOTGINT;
1705  __IO uint32_t GAHBCFG;
1706  __IO uint32_t GUSBCFG;
1707  __IO uint32_t GRSTCTL;
1709  union {
1710  __IO uint32_t GINTSTS_DEVICEMODE;
1711  __IO uint32_t GINTSTS_HOSTMODE;
1712  };
1713 
1714  union {
1715  __IO uint32_t GINTMSK_DEVICEMODE;
1716  __IO uint32_t GINTMSK_HOSTMODE;
1717  };
1718 
1719  union {
1720  __I uint32_t GRXSTSR_DEVICEMODE;
1721  __I uint32_t GRXSTSR_HOSTMODE;
1722  };
1723 
1724  union {
1725  __I uint32_t GRXSTSP_HOSTMODE;
1726  __I uint32_t GRXSTSP_DEVICEMODE;
1727  };
1728  __IO uint32_t GRXFSIZ;
1730  union {
1731  __IO uint32_t GNPTXFSIZ_DEVICEMODE;
1732  __IO uint32_t GNPTXFSIZ_HOSTMODE;
1733  };
1734  __I uint32_t GNPTXSTS;
1735  __I uint32_t RESERVED[3];
1736  __IO uint32_t GUID;
1737  __I uint32_t RESERVED1[7];
1738  __IO uint32_t GDFIFOCFG;
1739  __I uint32_t RESERVED2[40];
1740  __IO uint32_t HPTXFSIZ;
1741  __IO uint32_t DIEPTXF1;
1742  __IO uint32_t DIEPTXF2;
1743  __IO uint32_t DIEPTXF3;
1744  __IO uint32_t DIEPTXF4;
1745  __IO uint32_t DIEPTXF5;
1746  __IO uint32_t DIEPTXF6;
1747  __I uint32_t RESERVED3[185];
1748  __IO uint32_t HCFG;
1749  __IO uint32_t HFIR;
1750  __IO uint32_t HFNUM;
1751  __I uint32_t RESERVED4;
1752  __IO uint32_t HPTXSTS;
1753  __I uint32_t HAINT;
1754  __IO uint32_t HAINTMSK;
1755  __IO uint32_t HFLBADDR;
1756  __I uint32_t RESERVED5[8];
1757  __IO uint32_t HPRT;
1758  __I uint32_t RESERVED6[239];
1759  __IO uint32_t DCFG;
1760  __IO uint32_t DCTL;
1761  __I uint32_t DSTS;
1762  __I uint32_t RESERVED7;
1763  __IO uint32_t DIEPMSK;
1764  __IO uint32_t DOEPMSK;
1765  __I uint32_t DAINT;
1766  __IO uint32_t DAINTMSK;
1767  __I uint32_t RESERVED8[2];
1768  __IO uint32_t DVBUSDIS;
1769  __IO uint32_t DVBUSPULSE;
1770  __I uint32_t RESERVED9;
1771  __IO uint32_t DIEPEMPMSK;
1773  __I uint32_t RESERVED10[370];
1774  __IO uint32_t PCGCCTL;
1775 } USB0_GLOBAL_TypeDef;
1776 
1777 
1778 /* ================================================================================ */
1779 /* ================ USB0_EP0 ================ */
1780 /* ================================================================================ */
1781 
1782 
1787 typedef struct {
1788  __IO uint32_t DIEPCTL0;
1789  __I uint32_t RESERVED;
1790  __IO uint32_t DIEPINT0;
1791  __I uint32_t RESERVED1;
1792  __IO uint32_t DIEPTSIZ0;
1793  __IO uint32_t DIEPDMA0;
1794  __I uint32_t DTXFSTS0;
1795  __I uint32_t DIEPDMAB0;
1796  __I uint32_t RESERVED2[120];
1797  __IO uint32_t DOEPCTL0;
1798  __I uint32_t RESERVED3;
1799  __IO uint32_t DOEPINT0;
1800  __I uint32_t RESERVED4;
1801  __IO uint32_t DOEPTSIZ0;
1802  __IO uint32_t DOEPDMA0;
1803  __I uint32_t RESERVED5;
1804  __I uint32_t DOEPDMAB0;
1805 } USB0_EP0_TypeDef;
1806 
1807 
1808 /* ================================================================================ */
1809 /* ================ USB_EP [USB0_EP1] ================ */
1810 /* ================================================================================ */
1811 
1812 
1817 typedef struct {
1819  union {
1820  __IO uint32_t DIEPCTL_INTBULK;
1821  __IO uint32_t DIEPCTL_ISOCONT;
1822  };
1823  __I uint32_t RESERVED;
1824  __IO uint32_t DIEPINT;
1825  __I uint32_t RESERVED1;
1826  __IO uint32_t DIEPTSIZ;
1827  __IO uint32_t DIEPDMA;
1828  __I uint32_t DTXFSTS;
1829  __I uint32_t DIEPDMAB;
1830  __I uint32_t RESERVED2[120];
1831 
1832  union {
1833  __IO uint32_t DOEPCTL_INTBULK;
1834  __IO uint32_t DOEPCTL_ISOCONT;
1835  };
1836  __I uint32_t RESERVED3;
1837  __IO uint32_t DOEPINT;
1838  __I uint32_t RESERVED4;
1839 
1840  union {
1841  __IO uint32_t DOEPTSIZ_CONTROL;
1842  __IO uint32_t DOEPTSIZ_ISO;
1843  };
1844  __IO uint32_t DOEPDMA;
1845  __I uint32_t RESERVED5;
1846  __I uint32_t DOEPDMAB;
1847 } USB0_EP_TypeDef;
1848 
1849 
1850 /* ================================================================================ */
1851 /* ================ USB_CH [USB0_CH0] ================ */
1852 /* ================================================================================ */
1853 
1854 
1859 typedef struct {
1860  __IO uint32_t HCCHAR;
1861  __I uint32_t RESERVED;
1862  __IO uint32_t HCINT;
1863  __IO uint32_t HCINTMSK;
1865  union {
1866  __IO uint32_t HCTSIZ_SCATGATHER;
1867  __IO uint32_t HCTSIZ_BUFFERMODE;
1868  };
1869 
1870  union {
1871  __IO uint32_t HCDMA_SCATGATHER;
1872  __IO uint32_t HCDMA_BUFFERMODE;
1873  };
1874  __I uint32_t RESERVED1;
1875  __I uint32_t HCDMAB;
1876 } USB0_CH_TypeDef;
1877 
1878 
1879 /* ================================================================================ */
1880 /* ================ USIC [USIC0] ================ */
1881 /* ================================================================================ */
1882 
1883 
1888 typedef struct {
1889  __I uint32_t ID;
1890 } USIC_GLOBAL_TypeDef;
1891 
1892 
1893 /* ================================================================================ */
1894 /* ================ USIC_CH [USIC0_CH0] ================ */
1895 /* ================================================================================ */
1896 
1897 
1902 typedef struct {
1903  __I uint32_t RESERVED;
1904  __I uint32_t CCFG;
1905  __I uint32_t RESERVED1;
1906  __IO uint32_t KSCFG;
1907  __IO uint32_t FDR;
1908  __IO uint32_t BRG;
1909  __IO uint32_t INPR;
1910  __IO uint32_t DX0CR;
1911  __IO uint32_t DX1CR;
1912  __IO uint32_t DX2CR;
1913  __IO uint32_t DX3CR;
1914  __IO uint32_t DX4CR;
1915  __IO uint32_t DX5CR;
1916  __IO uint32_t SCTR;
1917  __IO uint32_t TCSR;
1919  union {
1920  __IO uint32_t PCR_IICMode;
1921  __IO uint32_t PCR_IISMode;
1922  __IO uint32_t PCR_SSCMode;
1923  __IO uint32_t PCR;
1924  __IO uint32_t PCR_ASCMode;
1925  };
1926  __IO uint32_t CCR;
1927  __IO uint32_t CMTR;
1929  union {
1930  __IO uint32_t PSR_IICMode;
1931  __IO uint32_t PSR_IISMode;
1932  __IO uint32_t PSR_SSCMode;
1933  __IO uint32_t PSR;
1934  __IO uint32_t PSR_ASCMode;
1935  };
1936  __O uint32_t PSCR;
1937  __I uint32_t RBUFSR;
1938  __I uint32_t RBUF;
1939  __I uint32_t RBUFD;
1940  __I uint32_t RBUF0;
1941  __I uint32_t RBUF1;
1942  __I uint32_t RBUF01SR;
1943  __O uint32_t FMR;
1944  __I uint32_t RESERVED2[5];
1945  __IO uint32_t TBUF[32];
1946  __IO uint32_t BYP;
1947  __IO uint32_t BYPCR;
1948  __IO uint32_t TBCTR;
1949  __IO uint32_t RBCTR;
1950  __I uint32_t TRBPTR;
1951  __IO uint32_t TRBSR;
1952  __O uint32_t TRBSCR;
1953  __I uint32_t OUTR;
1954  __I uint32_t OUTDR;
1955  __I uint32_t RESERVED3[23];
1956  __O uint32_t IN[32];
1957 } USIC_CH_TypeDef;
1958 
1959 
1960 /* ================================================================================ */
1961 /* ================ CAN ================ */
1962 /* ================================================================================ */
1963 
1964 
1969 typedef struct {
1970  __IO uint32_t CLC;
1971  __I uint32_t RESERVED;
1972  __I uint32_t ID;
1973  __IO uint32_t FDR;
1974  __I uint32_t RESERVED1[60];
1975  __I uint32_t LIST[16];
1976  __IO uint32_t MSPND[8];
1977  __I uint32_t RESERVED2[8];
1978  __I uint32_t MSID[8];
1979  __I uint32_t RESERVED3[8];
1980  __IO uint32_t MSIMASK;
1981  __IO uint32_t PANCTR;
1982  __IO uint32_t MCR;
1983  __O uint32_t MITR;
1984 } CAN_GLOBAL_TypeDef;
1985 
1986 
1987 /* ================================================================================ */
1988 /* ================ CAN_NODE [CAN_NODE0] ================ */
1989 /* ================================================================================ */
1990 
1991 
1996 typedef struct {
1997  __IO uint32_t NCR;
1998  __IO uint32_t NSR;
1999  __IO uint32_t NIPR;
2000  __IO uint32_t NPCR;
2001  __IO uint32_t NBTR;
2002  __IO uint32_t NECNT;
2003  __IO uint32_t NFCR;
2004 } CAN_NODE_TypeDef;
2005 
2006 
2007 /* ================================================================================ */
2008 /* ================ CAN_MO_CLUSTER [CAN_MO] ================ */
2009 /* ================================================================================ */
2010 
2011 
2016 typedef struct {
2017  CAN_MO_TypeDef MO[256];
2018 } CAN_MO_CLUSTER_Type;
2019 
2020 
2021 /* ================================================================================ */
2022 /* ================ VADC ================ */
2023 /* ================================================================================ */
2024 
2025 
2030 typedef struct {
2031  __IO uint32_t CLC;
2032  __I uint32_t RESERVED;
2033  __I uint32_t ID;
2034  __I uint32_t RESERVED1[7];
2035  __IO uint32_t OCS;
2036  __I uint32_t RESERVED2[21];
2037  __IO uint32_t GLOBCFG;
2038  __I uint32_t RESERVED3[7];
2039  __IO uint32_t GLOBICLASS[2];
2040  __I uint32_t RESERVED4[4];
2041  __IO uint32_t GLOBBOUND;
2042  __I uint32_t RESERVED5[9];
2043  __IO uint32_t GLOBEFLAG;
2044  __I uint32_t RESERVED6[23];
2045  __IO uint32_t GLOBEVNP;
2046  __I uint32_t RESERVED7[7];
2047  __IO uint32_t GLOBTF;
2048  __I uint32_t RESERVED8[7];
2049  __IO uint32_t BRSSEL[4];
2050  __I uint32_t RESERVED9[12];
2051  __IO uint32_t BRSPND[4];
2052  __I uint32_t RESERVED10[12];
2053  __IO uint32_t BRSCTRL;
2054  __IO uint32_t BRSMR;
2055  __I uint32_t RESERVED11[30];
2056  __IO uint32_t GLOBRCR;
2057  __I uint32_t RESERVED12[31];
2058  __IO uint32_t GLOBRES;
2059  __I uint32_t RESERVED13[31];
2060  __IO uint32_t GLOBRESD;
2061  __I uint32_t RESERVED14[27];
2062  __IO uint32_t EMUXSEL;
2063 } VADC_GLOBAL_TypeDef;
2064 
2065 
2066 /* ================================================================================ */
2067 /* ================ VADC_G [VADC_G0] ================ */
2068 /* ================================================================================ */
2069 
2070 
2075 typedef struct {
2076  __I uint32_t RESERVED[32];
2077  __IO uint32_t ARBCFG;
2078  __IO uint32_t ARBPR;
2079  __IO uint32_t CHASS;
2080  __I uint32_t RESERVED1[5];
2081  __IO uint32_t ICLASS[2];
2082  __I uint32_t RESERVED2[2];
2083  __IO uint32_t ALIAS;
2084  __I uint32_t RESERVED3;
2085  __IO uint32_t BOUND;
2086  __I uint32_t RESERVED4;
2087  __IO uint32_t SYNCTR;
2088  __I uint32_t RESERVED5;
2089  __IO uint32_t BFL;
2090  __O uint32_t BFLS;
2091  __IO uint32_t BFLC;
2092  __IO uint32_t BFLNP;
2093  __I uint32_t RESERVED6[10];
2094  __IO uint32_t QCTRL0;
2095  __IO uint32_t QMR0;
2096  __I uint32_t QSR0;
2097  __I uint32_t Q0R0;
2099  union {
2100  __I uint32_t QBUR0;
2101  __O uint32_t QINR0;
2102  };
2103  __I uint32_t RESERVED7[3];
2104  __IO uint32_t ASCTRL;
2105  __IO uint32_t ASMR;
2106  __IO uint32_t ASSEL;
2107  __IO uint32_t ASPND;
2108  __I uint32_t RESERVED8[20];
2109  __IO uint32_t CEFLAG;
2110  __IO uint32_t REFLAG;
2111  __IO uint32_t SEFLAG;
2112  __I uint32_t RESERVED9;
2113  __O uint32_t CEFCLR;
2114  __O uint32_t REFCLR;
2115  __O uint32_t SEFCLR;
2116  __I uint32_t RESERVED10;
2117  __IO uint32_t CEVNP0;
2118  __I uint32_t RESERVED11[3];
2119  __IO uint32_t REVNP0;
2120  __IO uint32_t REVNP1;
2121  __I uint32_t RESERVED12[2];
2122  __IO uint32_t SEVNP;
2123  __I uint32_t RESERVED13;
2124  __O uint32_t SRACT;
2125  __I uint32_t RESERVED14[9];
2126  __IO uint32_t EMUXCTR;
2127  __I uint32_t RESERVED15;
2128  __IO uint32_t VFR;
2129  __I uint32_t RESERVED16;
2130  __IO uint32_t CHCTR[8];
2131  __I uint32_t RESERVED17[24];
2132  __IO uint32_t RCR[16];
2133  __I uint32_t RESERVED18[16];
2134  __IO uint32_t RES[16];
2135  __I uint32_t RESERVED19[16];
2136  __I uint32_t RESD[16];
2137 } VADC_G_TypeDef;
2138 
2139 
2140 /* ================================================================================ */
2141 /* ================ DSD ================ */
2142 /* ================================================================================ */
2143 
2144 
2149 typedef struct {
2150  __IO uint32_t CLC;
2151  __I uint32_t RESERVED;
2152  __I uint32_t ID;
2153  __I uint32_t RESERVED1[7];
2154  __IO uint32_t OCS;
2155  __I uint32_t RESERVED2[21];
2156  __IO uint32_t GLOBCFG;
2157  __I uint32_t RESERVED3;
2158  __IO uint32_t GLOBRC;
2159  __I uint32_t RESERVED4[5];
2160  __IO uint32_t CGCFG;
2161  __I uint32_t RESERVED5[15];
2162  __IO uint32_t EVFLAG;
2163  __O uint32_t EVFLAGCLR;
2164 } DSD_GLOBAL_TypeDef;
2165 
2166 
2167 /* ================================================================================ */
2168 /* ================ DSD_CH [DSD_CH0] ================ */
2169 /* ================================================================================ */
2170 
2171 
2176 typedef struct {
2177  __IO uint32_t MODCFG;
2178  __I uint32_t RESERVED;
2179  __IO uint32_t DICFG;
2180  __I uint32_t RESERVED1[2];
2181  __IO uint32_t FCFGC;
2182  __IO uint32_t FCFGA;
2183  __I uint32_t RESERVED2;
2184  __IO uint32_t IWCTR;
2185  __I uint32_t RESERVED3;
2186  __IO uint32_t BOUNDSEL;
2187  __I uint32_t RESERVED4;
2188  __I uint32_t RESM;
2189  __I uint32_t RESERVED5;
2190  __IO uint32_t OFFM;
2191  __I uint32_t RESERVED6;
2192  __I uint32_t RESA;
2193  __I uint32_t RESERVED7[3];
2194  __I uint32_t TSTMP;
2195  __I uint32_t RESERVED8[19];
2196  __IO uint32_t CGSYNC;
2197  __I uint32_t RESERVED9;
2198  __IO uint32_t RECTCFG;
2199 } DSD_CH_TypeDef;
2200 
2201 
2202 /* ================================================================================ */
2203 /* ================ DAC ================ */
2204 /* ================================================================================ */
2205 
2206 
2211 typedef struct {
2212  __I uint32_t ID;
2213  __IO uint32_t DAC0CFG0;
2214  __IO uint32_t DAC0CFG1;
2215  __IO uint32_t DAC1CFG0;
2216  __IO uint32_t DAC1CFG1;
2217  __IO uint32_t DAC0DATA;
2218  __IO uint32_t DAC1DATA;
2219  __IO uint32_t DAC01DATA;
2220  __IO uint32_t DAC0PATL;
2221  __IO uint32_t DAC0PATH;
2222  __IO uint32_t DAC1PATL;
2223  __IO uint32_t DAC1PATH;
2224 } DAC_GLOBAL_TypeDef;
2225 
2226 
2227 /* ================================================================================ */
2228 /* ================ CCU4 [CCU40] ================ */
2229 /* ================================================================================ */
2230 
2231 
2236 typedef struct {
2237  __IO uint32_t GCTRL;
2238  __I uint32_t GSTAT;
2239  __O uint32_t GIDLS;
2240  __O uint32_t GIDLC;
2241  __O uint32_t GCSS;
2242  __O uint32_t GCSC;
2243  __I uint32_t GCST;
2244  __I uint32_t RESERVED[25];
2245  __I uint32_t MIDR;
2246 } CCU4_GLOBAL_TypeDef;
2247 
2248 
2249 /* ================================================================================ */
2250 /* ================ CCU4_CC4 [CCU40_CC40] ================ */
2251 /* ================================================================================ */
2252 
2253 
2258 typedef struct {
2259  __IO uint32_t INS;
2260  __IO uint32_t CMC;
2261  __I uint32_t TCST;
2262  __O uint32_t TCSET;
2263  __O uint32_t TCCLR;
2264  __IO uint32_t TC;
2265  __IO uint32_t PSL;
2266  __I uint32_t DIT;
2267  __IO uint32_t DITS;
2268  __IO uint32_t PSC;
2269  __IO uint32_t FPC;
2270  __IO uint32_t FPCS;
2271  __I uint32_t PR;
2272  __IO uint32_t PRS;
2273  __I uint32_t CR;
2274  __IO uint32_t CRS;
2275  __I uint32_t RESERVED[12];
2276  __IO uint32_t TIMER;
2277  __I uint32_t CV[4];
2278  __I uint32_t RESERVED1[7];
2279  __I uint32_t INTS;
2280  __IO uint32_t INTE;
2281  __IO uint32_t SRS;
2282  __O uint32_t SWS;
2283  __O uint32_t SWR;
2284  __I uint32_t RESERVED2;
2285  __I uint32_t ECRD0;
2286  __I uint32_t ECRD1;
2287 } CCU4_CC4_TypeDef;
2288 
2289 
2290 /* ================================================================================ */
2291 /* ================ CCU8 [CCU80] ================ */
2292 /* ================================================================================ */
2293 
2294 
2299 typedef struct {
2300  __IO uint32_t GCTRL;
2301  __I uint32_t GSTAT;
2302  __O uint32_t GIDLS;
2303  __O uint32_t GIDLC;
2304  __O uint32_t GCSS;
2305  __O uint32_t GCSC;
2306  __I uint32_t GCST;
2307  __IO uint32_t GPCHK;
2308  __I uint32_t RESERVED[24];
2309  __I uint32_t MIDR;
2310 } CCU8_GLOBAL_TypeDef;
2311 
2312 
2313 /* ================================================================================ */
2314 /* ================ CCU8_CC8 [CCU80_CC80] ================ */
2315 /* ================================================================================ */
2316 
2317 
2322 typedef struct {
2323  __IO uint32_t INS;
2324  __IO uint32_t CMC;
2325  __I uint32_t TCST;
2326  __O uint32_t TCSET;
2327  __O uint32_t TCCLR;
2328  __IO uint32_t TC;
2329  __IO uint32_t PSL;
2330  __I uint32_t DIT;
2331  __IO uint32_t DITS;
2332  __IO uint32_t PSC;
2333  __IO uint32_t FPC;
2334  __IO uint32_t FPCS;
2335  __I uint32_t PR;
2336  __IO uint32_t PRS;
2337  __I uint32_t CR1;
2338  __IO uint32_t CR1S;
2339  __I uint32_t CR2;
2340  __IO uint32_t CR2S;
2341  __IO uint32_t CHC;
2342  __IO uint32_t DTC;
2343  __IO uint32_t DC1R;
2344  __IO uint32_t DC2R;
2345  __I uint32_t RESERVED[6];
2346  __IO uint32_t TIMER;
2347  __I uint32_t CV[4];
2348  __I uint32_t RESERVED1[7];
2349  __I uint32_t INTS;
2350  __IO uint32_t INTE;
2351  __IO uint32_t SRS;
2352  __O uint32_t SWS;
2353  __O uint32_t SWR;
2354  __IO uint32_t STC;
2355  __I uint32_t ECRD0;
2356  __I uint32_t ECRD1;
2357 } CCU8_CC8_TypeDef;
2358 
2359 
2360 /* ================================================================================ */
2361 /* ================ POSIF [POSIF0] ================ */
2362 /* ================================================================================ */
2363 
2364 
2369 typedef struct {
2370  __IO uint32_t PCONF;
2371  __IO uint32_t PSUS;
2372  __O uint32_t PRUNS;
2373  __O uint32_t PRUNC;
2374  __I uint32_t PRUN;
2375  __I uint32_t RESERVED[3];
2376  __I uint32_t MIDR;
2377  __I uint32_t RESERVED1[3];
2378  __I uint32_t HALP;
2379  __IO uint32_t HALPS;
2380  __I uint32_t RESERVED2[2];
2381  __I uint32_t MCM;
2382  __IO uint32_t MCSM;
2383  __O uint32_t MCMS;
2384  __O uint32_t MCMC;
2385  __I uint32_t MCMF;
2386  __I uint32_t RESERVED3[3];
2387  __IO uint32_t QDC;
2388  __I uint32_t RESERVED4[3];
2389  __I uint32_t PFLG;
2390  __IO uint32_t PFLGE;
2391  __O uint32_t SPFLG;
2392  __O uint32_t RPFLG;
2393  __I uint32_t RESERVED5[32];
2394  __I uint32_t PDBG;
2395 } POSIF_GLOBAL_TypeDef;
2396 
2397 
2398 /* ================================================================================ */
2399 /* ================ PORT0 ================ */
2400 /* ================================================================================ */
2401 
2402 
2407 typedef struct {
2408  __IO uint32_t OUT;
2409  __O uint32_t OMR;
2410  __I uint32_t RESERVED[2];
2411  __IO uint32_t IOCR0;
2412  __IO uint32_t IOCR4;
2413  __IO uint32_t IOCR8;
2414  __IO uint32_t IOCR12;
2415  __I uint32_t RESERVED1;
2416  __I uint32_t IN;
2417  __I uint32_t RESERVED2[6];
2418  __IO uint32_t PDR0;
2419  __IO uint32_t PDR1;
2420  __I uint32_t RESERVED3[6];
2421  __I uint32_t PDISC;
2422  __I uint32_t RESERVED4[3];
2423  __IO uint32_t PPS;
2424  __IO uint32_t HWSEL;
2425 } PORT0_Type;
2426 
2427 
2428 /* ================================================================================ */
2429 /* ================ PORT1 ================ */
2430 /* ================================================================================ */
2431 
2432 
2437 typedef struct {
2438  __IO uint32_t OUT;
2439  __O uint32_t OMR;
2440  __I uint32_t RESERVED[2];
2441  __IO uint32_t IOCR0;
2442  __IO uint32_t IOCR4;
2443  __IO uint32_t IOCR8;
2444  __IO uint32_t IOCR12;
2445  __I uint32_t RESERVED1;
2446  __I uint32_t IN;
2447  __I uint32_t RESERVED2[6];
2448  __IO uint32_t PDR0;
2449  __IO uint32_t PDR1;
2450  __I uint32_t RESERVED3[6];
2451  __I uint32_t PDISC;
2452  __I uint32_t RESERVED4[3];
2453  __IO uint32_t PPS;
2454  __IO uint32_t HWSEL;
2455 } PORT1_Type;
2456 
2457 
2458 /* ================================================================================ */
2459 /* ================ PORT2 ================ */
2460 /* ================================================================================ */
2461 
2462 
2467 typedef struct {
2468  __IO uint32_t OUT;
2469  __O uint32_t OMR;
2470  __I uint32_t RESERVED[2];
2471  __IO uint32_t IOCR0;
2472  __IO uint32_t IOCR4;
2473  __IO uint32_t IOCR8;
2474  __IO uint32_t IOCR12;
2475  __I uint32_t RESERVED1;
2476  __I uint32_t IN;
2477  __I uint32_t RESERVED2[6];
2478  __IO uint32_t PDR0;
2479  __IO uint32_t PDR1;
2480  __I uint32_t RESERVED3[6];
2481  __I uint32_t PDISC;
2482  __I uint32_t RESERVED4[3];
2483  __IO uint32_t PPS;
2484  __IO uint32_t HWSEL;
2485 } PORT2_Type;
2486 
2487 
2488 /* ================================================================================ */
2489 /* ================ PORT3 ================ */
2490 /* ================================================================================ */
2491 
2492 
2497 typedef struct {
2498  __IO uint32_t OUT;
2499  __O uint32_t OMR;
2500  __I uint32_t RESERVED[2];
2501  __IO uint32_t IOCR0;
2502  __IO uint32_t IOCR4;
2503  __IO uint32_t IOCR8;
2504  __IO uint32_t IOCR12;
2505  __I uint32_t RESERVED1;
2506  __I uint32_t IN;
2507  __I uint32_t RESERVED2[6];
2508  __IO uint32_t PDR0;
2509  __IO uint32_t PDR1;
2510  __I uint32_t RESERVED3[6];
2511  __I uint32_t PDISC;
2512  __I uint32_t RESERVED4[3];
2513  __IO uint32_t PPS;
2514  __IO uint32_t HWSEL;
2515 } PORT3_Type;
2516 
2517 
2518 /* ================================================================================ */
2519 /* ================ PORT4 ================ */
2520 /* ================================================================================ */
2521 
2522 
2527 typedef struct {
2528  __IO uint32_t OUT;
2529  __O uint32_t OMR;
2530  __I uint32_t RESERVED[2];
2531  __IO uint32_t IOCR0;
2532  __IO uint32_t IOCR4;
2533  __I uint32_t RESERVED1[3];
2534  __I uint32_t IN;
2535  __I uint32_t RESERVED2[6];
2536  __IO uint32_t PDR0;
2537  __I uint32_t RESERVED3[7];
2538  __I uint32_t PDISC;
2539  __I uint32_t RESERVED4[3];
2540  __IO uint32_t PPS;
2541  __IO uint32_t HWSEL;
2542 } PORT4_Type;
2543 
2544 
2545 /* ================================================================================ */
2546 /* ================ PORT5 ================ */
2547 /* ================================================================================ */
2548 
2549 
2554 typedef struct {
2555  __IO uint32_t OUT;
2556  __O uint32_t OMR;
2557  __I uint32_t RESERVED[2];
2558  __IO uint32_t IOCR0;
2559  __IO uint32_t IOCR4;
2560  __IO uint32_t IOCR8;
2561  __I uint32_t RESERVED1[2];
2562  __I uint32_t IN;
2563  __I uint32_t RESERVED2[6];
2564  __IO uint32_t PDR0;
2565  __IO uint32_t PDR1;
2566  __I uint32_t RESERVED3[6];
2567  __I uint32_t PDISC;
2568  __I uint32_t RESERVED4[3];
2569  __IO uint32_t PPS;
2570  __IO uint32_t HWSEL;
2571 } PORT5_Type;
2572 
2573 
2574 /* ================================================================================ */
2575 /* ================ PORT6 ================ */
2576 /* ================================================================================ */
2577 
2578 
2583 typedef struct {
2584  __IO uint32_t OUT;
2585  __O uint32_t OMR;
2586  __I uint32_t RESERVED[2];
2587  __IO uint32_t IOCR0;
2588  __IO uint32_t IOCR4;
2589  __I uint32_t RESERVED1[3];
2590  __I uint32_t IN;
2591  __I uint32_t RESERVED2[6];
2592  __IO uint32_t PDR0;
2593  __I uint32_t RESERVED3[7];
2594  __I uint32_t PDISC;
2595  __I uint32_t RESERVED4[3];
2596  __IO uint32_t PPS;
2597  __IO uint32_t HWSEL;
2598 } PORT6_Type;
2599 
2600 
2601 /* ================================================================================ */
2602 /* ================ PORT7 ================ */
2603 /* ================================================================================ */
2604 
2605 
2610 typedef struct {
2611  __IO uint32_t OUT;
2612  __O uint32_t OMR;
2613  __I uint32_t RESERVED[2];
2614  __IO uint32_t IOCR0;
2615  __IO uint32_t IOCR4;
2616  __IO uint32_t IOCR8;
2617  __I uint32_t RESERVED1[2];
2618  __I uint32_t IN;
2619  __I uint32_t RESERVED2[6];
2620  __IO uint32_t PDR0;
2621  __IO uint32_t PDR1;
2622  __I uint32_t RESERVED3[6];
2623  __I uint32_t PDISC;
2624  __I uint32_t RESERVED4[3];
2625  __IO uint32_t PPS;
2626  __IO uint32_t HWSEL;
2627 } PORT7_Type;
2628 
2629 
2630 /* ================================================================================ */
2631 /* ================ PORT8 ================ */
2632 /* ================================================================================ */
2633 
2634 
2639 typedef struct {
2640  __IO uint32_t OUT;
2641  __O uint32_t OMR;
2642  __I uint32_t RESERVED[2];
2643  __IO uint32_t IOCR0;
2644  __IO uint32_t IOCR4;
2645  __IO uint32_t IOCR8;
2646  __I uint32_t RESERVED1[2];
2647  __I uint32_t IN;
2648  __I uint32_t RESERVED2[6];
2649  __IO uint32_t PDR0;
2650  __IO uint32_t PDR1;
2651  __I uint32_t RESERVED3[6];
2652  __I uint32_t PDISC;
2653  __I uint32_t RESERVED4[3];
2654  __IO uint32_t PPS;
2655  __IO uint32_t HWSEL;
2656 } PORT8_Type;
2657 
2658 
2659 /* ================================================================================ */
2660 /* ================ PORT9 ================ */
2661 /* ================================================================================ */
2662 
2663 
2668 typedef struct {
2669  __IO uint32_t OUT;
2670  __O uint32_t OMR;
2671  __I uint32_t RESERVED[2];
2672  __IO uint32_t IOCR0;
2673  __IO uint32_t IOCR4;
2674  __IO uint32_t IOCR8;
2675  __I uint32_t RESERVED1[2];
2676  __I uint32_t IN;
2677  __I uint32_t RESERVED2[6];
2678  __IO uint32_t PDR0;
2679  __IO uint32_t PDR1;
2680  __I uint32_t RESERVED3[6];
2681  __I uint32_t PDISC;
2682  __I uint32_t RESERVED4[3];
2683  __IO uint32_t PPS;
2684  __IO uint32_t HWSEL;
2685 } PORT9_Type;
2686 
2687 
2688 /* ================================================================================ */
2689 /* ================ PORT14 ================ */
2690 /* ================================================================================ */
2691 
2692 
2697 typedef struct {
2698  __IO uint32_t OUT;
2699  __O uint32_t OMR;
2700  __I uint32_t RESERVED[2];
2701  __IO uint32_t IOCR0;
2702  __IO uint32_t IOCR4;
2703  __IO uint32_t IOCR8;
2704  __IO uint32_t IOCR12;
2705  __I uint32_t RESERVED1;
2706  __I uint32_t IN;
2707  __I uint32_t RESERVED2[14];
2708  __IO uint32_t PDISC;
2709  __I uint32_t RESERVED3[3];
2710  __IO uint32_t PPS;
2711  __IO uint32_t HWSEL;
2712 } PORT14_Type;
2713 
2714 
2715 /* ================================================================================ */
2716 /* ================ PORT15 ================ */
2717 /* ================================================================================ */
2718 
2719 
2724 typedef struct {
2725  __IO uint32_t OUT;
2726  __O uint32_t OMR;
2727  __I uint32_t RESERVED[2];
2728  __IO uint32_t IOCR0;
2729  __IO uint32_t IOCR4;
2730  __IO uint32_t IOCR8;
2731  __IO uint32_t IOCR12;
2732  __I uint32_t RESERVED1;
2733  __I uint32_t IN;
2734  __I uint32_t RESERVED2[14];
2735  __IO uint32_t PDISC;
2736  __I uint32_t RESERVED3[3];
2737  __IO uint32_t PPS;
2738  __IO uint32_t HWSEL;
2739 } PORT15_Type;
2740 
2741 
2742 /* -------------------- End of section using anonymous unions ------------------- */
2743 #if defined(__CC_ARM)
2744  #pragma pop
2745 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
2746  #pragma clang diagnostic pop
2747 #elif defined(__ICCARM__)
2748  /* leave anonymous unions enabled */
2749 #elif defined(__GNUC__)
2750  /* anonymous unions are enabled by default */
2751 #elif defined(__TMS470__)
2752  /* anonymous unions are enabled by default */
2753 #elif defined(__TASKING__)
2754  #pragma warning restore
2755 #else
2756  #warning Not supported compiler type
2757 #endif
2758 
2759 
2760 
2761 /* ================================================================================ */
2762 /* ================ struct 'PPB' Position & Mask ================ */
2763 /* ================================================================================ */
2764 
2765 
2766 /* ---------------------------------- PPB_ACTLR --------------------------------- */
2767 #define PPB_ACTLR_DISMCYCINT_Pos (0UL)
2768 #define PPB_ACTLR_DISMCYCINT_Msk (0x1UL)
2769 #define PPB_ACTLR_DISDEFWBUF_Pos (1UL)
2770 #define PPB_ACTLR_DISDEFWBUF_Msk (0x2UL)
2771 #define PPB_ACTLR_DISFOLD_Pos (2UL)
2772 #define PPB_ACTLR_DISFOLD_Msk (0x4UL)
2773 #define PPB_ACTLR_DISFPCA_Pos (8UL)
2774 #define PPB_ACTLR_DISFPCA_Msk (0x100UL)
2775 #define PPB_ACTLR_DISOOFP_Pos (9UL)
2776 #define PPB_ACTLR_DISOOFP_Msk (0x200UL)
2778 /* -------------------------------- PPB_SYST_CSR -------------------------------- */
2779 #define PPB_SYST_CSR_ENABLE_Pos (0UL)
2780 #define PPB_SYST_CSR_ENABLE_Msk (0x1UL)
2781 #define PPB_SYST_CSR_TICKINT_Pos (1UL)
2782 #define PPB_SYST_CSR_TICKINT_Msk (0x2UL)
2783 #define PPB_SYST_CSR_CLKSOURCE_Pos (2UL)
2784 #define PPB_SYST_CSR_CLKSOURCE_Msk (0x4UL)
2785 #define PPB_SYST_CSR_COUNTFLAG_Pos (16UL)
2786 #define PPB_SYST_CSR_COUNTFLAG_Msk (0x10000UL)
2788 /* -------------------------------- PPB_SYST_RVR -------------------------------- */
2789 #define PPB_SYST_RVR_RELOAD_Pos (0UL)
2790 #define PPB_SYST_RVR_RELOAD_Msk (0xffffffUL)
2792 /* -------------------------------- PPB_SYST_CVR -------------------------------- */
2793 #define PPB_SYST_CVR_CURRENT_Pos (0UL)
2794 #define PPB_SYST_CVR_CURRENT_Msk (0xffffffUL)
2796 /* ------------------------------- PPB_SYST_CALIB ------------------------------- */
2797 #define PPB_SYST_CALIB_TENMS_Pos (0UL)
2798 #define PPB_SYST_CALIB_TENMS_Msk (0xffffffUL)
2799 #define PPB_SYST_CALIB_SKEW_Pos (30UL)
2800 #define PPB_SYST_CALIB_SKEW_Msk (0x40000000UL)
2801 #define PPB_SYST_CALIB_NOREF_Pos (31UL)
2802 #define PPB_SYST_CALIB_NOREF_Msk (0x80000000UL)
2804 /* ------------------------------- PPB_NVIC_ISER0 ------------------------------- */
2805 #define PPB_NVIC_ISER0_SETENA_Pos (0UL)
2806 #define PPB_NVIC_ISER0_SETENA_Msk (0xffffffffUL)
2808 /* ------------------------------- PPB_NVIC_ISER1 ------------------------------- */
2809 #define PPB_NVIC_ISER1_SETENA_Pos (0UL)
2810 #define PPB_NVIC_ISER1_SETENA_Msk (0xffffffffUL)
2812 /* ------------------------------- PPB_NVIC_ISER2 ------------------------------- */
2813 #define PPB_NVIC_ISER2_SETENA_Pos (0UL)
2814 #define PPB_NVIC_ISER2_SETENA_Msk (0xffffffffUL)
2816 /* ------------------------------- PPB_NVIC_ISER3 ------------------------------- */
2817 #define PPB_NVIC_ISER3_SETENA_Pos (0UL)
2818 #define PPB_NVIC_ISER3_SETENA_Msk (0xffffffffUL)
2820 /* ------------------------------- PPB_NVIC_ICER0 ------------------------------- */
2821 #define PPB_NVIC_ICER0_CLRENA_Pos (0UL)
2822 #define PPB_NVIC_ICER0_CLRENA_Msk (0xffffffffUL)
2824 /* ------------------------------- PPB_NVIC_ICER1 ------------------------------- */
2825 #define PPB_NVIC_ICER1_CLRENA_Pos (0UL)
2826 #define PPB_NVIC_ICER1_CLRENA_Msk (0xffffffffUL)
2828 /* ------------------------------- PPB_NVIC_ICER2 ------------------------------- */
2829 #define PPB_NVIC_ICER2_CLRENA_Pos (0UL)
2830 #define PPB_NVIC_ICER2_CLRENA_Msk (0xffffffffUL)
2832 /* ------------------------------- PPB_NVIC_ICER3 ------------------------------- */
2833 #define PPB_NVIC_ICER3_CLRENA_Pos (0UL)
2834 #define PPB_NVIC_ICER3_CLRENA_Msk (0xffffffffUL)
2836 /* ------------------------------- PPB_NVIC_ISPR0 ------------------------------- */
2837 #define PPB_NVIC_ISPR0_SETPEND_Pos (0UL)
2838 #define PPB_NVIC_ISPR0_SETPEND_Msk (0xffffffffUL)
2840 /* ------------------------------- PPB_NVIC_ISPR1 ------------------------------- */
2841 #define PPB_NVIC_ISPR1_SETPEND_Pos (0UL)
2842 #define PPB_NVIC_ISPR1_SETPEND_Msk (0xffffffffUL)
2844 /* ------------------------------- PPB_NVIC_ISPR2 ------------------------------- */
2845 #define PPB_NVIC_ISPR2_SETPEND_Pos (0UL)
2846 #define PPB_NVIC_ISPR2_SETPEND_Msk (0xffffffffUL)
2848 /* ------------------------------- PPB_NVIC_ISPR3 ------------------------------- */
2849 #define PPB_NVIC_ISPR3_SETPEND_Pos (0UL)
2850 #define PPB_NVIC_ISPR3_SETPEND_Msk (0xffffffffUL)
2852 /* ------------------------------- PPB_NVIC_ICPR0 ------------------------------- */
2853 #define PPB_NVIC_ICPR0_CLRPEND_Pos (0UL)
2854 #define PPB_NVIC_ICPR0_CLRPEND_Msk (0xffffffffUL)
2856 /* ------------------------------- PPB_NVIC_ICPR1 ------------------------------- */
2857 #define PPB_NVIC_ICPR1_CLRPEND_Pos (0UL)
2858 #define PPB_NVIC_ICPR1_CLRPEND_Msk (0xffffffffUL)
2860 /* ------------------------------- PPB_NVIC_ICPR2 ------------------------------- */
2861 #define PPB_NVIC_ICPR2_CLRPEND_Pos (0UL)
2862 #define PPB_NVIC_ICPR2_CLRPEND_Msk (0xffffffffUL)
2864 /* ------------------------------- PPB_NVIC_ICPR3 ------------------------------- */
2865 #define PPB_NVIC_ICPR3_CLRPEND_Pos (0UL)
2866 #define PPB_NVIC_ICPR3_CLRPEND_Msk (0xffffffffUL)
2868 /* ------------------------------- PPB_NVIC_IABR0 ------------------------------- */
2869 #define PPB_NVIC_IABR0_ACTIVE_Pos (0UL)
2870 #define PPB_NVIC_IABR0_ACTIVE_Msk (0xffffffffUL)
2872 /* ------------------------------- PPB_NVIC_IABR1 ------------------------------- */
2873 #define PPB_NVIC_IABR1_ACTIVE_Pos (0UL)
2874 #define PPB_NVIC_IABR1_ACTIVE_Msk (0xffffffffUL)
2876 /* ------------------------------- PPB_NVIC_IABR2 ------------------------------- */
2877 #define PPB_NVIC_IABR2_ACTIVE_Pos (0UL)
2878 #define PPB_NVIC_IABR2_ACTIVE_Msk (0xffffffffUL)
2880 /* ------------------------------- PPB_NVIC_IABR3 ------------------------------- */
2881 #define PPB_NVIC_IABR3_ACTIVE_Pos (0UL)
2882 #define PPB_NVIC_IABR3_ACTIVE_Msk (0xffffffffUL)
2884 /* -------------------------------- PPB_NVIC_IPR0 ------------------------------- */
2885 #define PPB_NVIC_IPR0_PRI_0_Pos (0UL)
2886 #define PPB_NVIC_IPR0_PRI_0_Msk (0xffUL)
2887 #define PPB_NVIC_IPR0_PRI_1_Pos (8UL)
2888 #define PPB_NVIC_IPR0_PRI_1_Msk (0xff00UL)
2889 #define PPB_NVIC_IPR0_PRI_2_Pos (16UL)
2890 #define PPB_NVIC_IPR0_PRI_2_Msk (0xff0000UL)
2891 #define PPB_NVIC_IPR0_PRI_3_Pos (24UL)
2892 #define PPB_NVIC_IPR0_PRI_3_Msk (0xff000000UL)
2894 /* -------------------------------- PPB_NVIC_IPR1 ------------------------------- */
2895 #define PPB_NVIC_IPR1_PRI_0_Pos (0UL)
2896 #define PPB_NVIC_IPR1_PRI_0_Msk (0xffUL)
2897 #define PPB_NVIC_IPR1_PRI_1_Pos (8UL)
2898 #define PPB_NVIC_IPR1_PRI_1_Msk (0xff00UL)
2899 #define PPB_NVIC_IPR1_PRI_2_Pos (16UL)
2900 #define PPB_NVIC_IPR1_PRI_2_Msk (0xff0000UL)
2901 #define PPB_NVIC_IPR1_PRI_3_Pos (24UL)
2902 #define PPB_NVIC_IPR1_PRI_3_Msk (0xff000000UL)
2904 /* -------------------------------- PPB_NVIC_IPR2 ------------------------------- */
2905 #define PPB_NVIC_IPR2_PRI_0_Pos (0UL)
2906 #define PPB_NVIC_IPR2_PRI_0_Msk (0xffUL)
2907 #define PPB_NVIC_IPR2_PRI_1_Pos (8UL)
2908 #define PPB_NVIC_IPR2_PRI_1_Msk (0xff00UL)
2909 #define PPB_NVIC_IPR2_PRI_2_Pos (16UL)
2910 #define PPB_NVIC_IPR2_PRI_2_Msk (0xff0000UL)
2911 #define PPB_NVIC_IPR2_PRI_3_Pos (24UL)
2912 #define PPB_NVIC_IPR2_PRI_3_Msk (0xff000000UL)
2914 /* -------------------------------- PPB_NVIC_IPR3 ------------------------------- */
2915 #define PPB_NVIC_IPR3_PRI_0_Pos (0UL)
2916 #define PPB_NVIC_IPR3_PRI_0_Msk (0xffUL)
2917 #define PPB_NVIC_IPR3_PRI_1_Pos (8UL)
2918 #define PPB_NVIC_IPR3_PRI_1_Msk (0xff00UL)
2919 #define PPB_NVIC_IPR3_PRI_2_Pos (16UL)
2920 #define PPB_NVIC_IPR3_PRI_2_Msk (0xff0000UL)
2921 #define PPB_NVIC_IPR3_PRI_3_Pos (24UL)
2922 #define PPB_NVIC_IPR3_PRI_3_Msk (0xff000000UL)
2924 /* -------------------------------- PPB_NVIC_IPR4 ------------------------------- */
2925 #define PPB_NVIC_IPR4_PRI_0_Pos (0UL)
2926 #define PPB_NVIC_IPR4_PRI_0_Msk (0xffUL)
2927 #define PPB_NVIC_IPR4_PRI_1_Pos (8UL)
2928 #define PPB_NVIC_IPR4_PRI_1_Msk (0xff00UL)
2929 #define PPB_NVIC_IPR4_PRI_2_Pos (16UL)
2930 #define PPB_NVIC_IPR4_PRI_2_Msk (0xff0000UL)
2931 #define PPB_NVIC_IPR4_PRI_3_Pos (24UL)
2932 #define PPB_NVIC_IPR4_PRI_3_Msk (0xff000000UL)
2934 /* -------------------------------- PPB_NVIC_IPR5 ------------------------------- */
2935 #define PPB_NVIC_IPR5_PRI_0_Pos (0UL)
2936 #define PPB_NVIC_IPR5_PRI_0_Msk (0xffUL)
2937 #define PPB_NVIC_IPR5_PRI_1_Pos (8UL)
2938 #define PPB_NVIC_IPR5_PRI_1_Msk (0xff00UL)
2939 #define PPB_NVIC_IPR5_PRI_2_Pos (16UL)
2940 #define PPB_NVIC_IPR5_PRI_2_Msk (0xff0000UL)
2941 #define PPB_NVIC_IPR5_PRI_3_Pos (24UL)
2942 #define PPB_NVIC_IPR5_PRI_3_Msk (0xff000000UL)
2944 /* -------------------------------- PPB_NVIC_IPR6 ------------------------------- */
2945 #define PPB_NVIC_IPR6_PRI_0_Pos (0UL)
2946 #define PPB_NVIC_IPR6_PRI_0_Msk (0xffUL)
2947 #define PPB_NVIC_IPR6_PRI_1_Pos (8UL)
2948 #define PPB_NVIC_IPR6_PRI_1_Msk (0xff00UL)
2949 #define PPB_NVIC_IPR6_PRI_2_Pos (16UL)
2950 #define PPB_NVIC_IPR6_PRI_2_Msk (0xff0000UL)
2951 #define PPB_NVIC_IPR6_PRI_3_Pos (24UL)
2952 #define PPB_NVIC_IPR6_PRI_3_Msk (0xff000000UL)
2954 /* -------------------------------- PPB_NVIC_IPR7 ------------------------------- */
2955 #define PPB_NVIC_IPR7_PRI_0_Pos (0UL)
2956 #define PPB_NVIC_IPR7_PRI_0_Msk (0xffUL)
2957 #define PPB_NVIC_IPR7_PRI_1_Pos (8UL)
2958 #define PPB_NVIC_IPR7_PRI_1_Msk (0xff00UL)
2959 #define PPB_NVIC_IPR7_PRI_2_Pos (16UL)
2960 #define PPB_NVIC_IPR7_PRI_2_Msk (0xff0000UL)
2961 #define PPB_NVIC_IPR7_PRI_3_Pos (24UL)
2962 #define PPB_NVIC_IPR7_PRI_3_Msk (0xff000000UL)
2964 /* -------------------------------- PPB_NVIC_IPR8 ------------------------------- */
2965 #define PPB_NVIC_IPR8_PRI_0_Pos (0UL)
2966 #define PPB_NVIC_IPR8_PRI_0_Msk (0xffUL)
2967 #define PPB_NVIC_IPR8_PRI_1_Pos (8UL)
2968 #define PPB_NVIC_IPR8_PRI_1_Msk (0xff00UL)
2969 #define PPB_NVIC_IPR8_PRI_2_Pos (16UL)
2970 #define PPB_NVIC_IPR8_PRI_2_Msk (0xff0000UL)
2971 #define PPB_NVIC_IPR8_PRI_3_Pos (24UL)
2972 #define PPB_NVIC_IPR8_PRI_3_Msk (0xff000000UL)
2974 /* -------------------------------- PPB_NVIC_IPR9 ------------------------------- */
2975 #define PPB_NVIC_IPR9_PRI_0_Pos (0UL)
2976 #define PPB_NVIC_IPR9_PRI_0_Msk (0xffUL)
2977 #define PPB_NVIC_IPR9_PRI_1_Pos (8UL)
2978 #define PPB_NVIC_IPR9_PRI_1_Msk (0xff00UL)
2979 #define PPB_NVIC_IPR9_PRI_2_Pos (16UL)
2980 #define PPB_NVIC_IPR9_PRI_2_Msk (0xff0000UL)
2981 #define PPB_NVIC_IPR9_PRI_3_Pos (24UL)
2982 #define PPB_NVIC_IPR9_PRI_3_Msk (0xff000000UL)
2984 /* ------------------------------- PPB_NVIC_IPR10 ------------------------------- */
2985 #define PPB_NVIC_IPR10_PRI_0_Pos (0UL)
2986 #define PPB_NVIC_IPR10_PRI_0_Msk (0xffUL)
2987 #define PPB_NVIC_IPR10_PRI_1_Pos (8UL)
2988 #define PPB_NVIC_IPR10_PRI_1_Msk (0xff00UL)
2989 #define PPB_NVIC_IPR10_PRI_2_Pos (16UL)
2990 #define PPB_NVIC_IPR10_PRI_2_Msk (0xff0000UL)
2991 #define PPB_NVIC_IPR10_PRI_3_Pos (24UL)
2992 #define PPB_NVIC_IPR10_PRI_3_Msk (0xff000000UL)
2994 /* ------------------------------- PPB_NVIC_IPR11 ------------------------------- */
2995 #define PPB_NVIC_IPR11_PRI_0_Pos (0UL)
2996 #define PPB_NVIC_IPR11_PRI_0_Msk (0xffUL)
2997 #define PPB_NVIC_IPR11_PRI_1_Pos (8UL)
2998 #define PPB_NVIC_IPR11_PRI_1_Msk (0xff00UL)
2999 #define PPB_NVIC_IPR11_PRI_2_Pos (16UL)
3000 #define PPB_NVIC_IPR11_PRI_2_Msk (0xff0000UL)
3001 #define PPB_NVIC_IPR11_PRI_3_Pos (24UL)
3002 #define PPB_NVIC_IPR11_PRI_3_Msk (0xff000000UL)
3004 /* ------------------------------- PPB_NVIC_IPR12 ------------------------------- */
3005 #define PPB_NVIC_IPR12_PRI_0_Pos (0UL)
3006 #define PPB_NVIC_IPR12_PRI_0_Msk (0xffUL)
3007 #define PPB_NVIC_IPR12_PRI_1_Pos (8UL)
3008 #define PPB_NVIC_IPR12_PRI_1_Msk (0xff00UL)
3009 #define PPB_NVIC_IPR12_PRI_2_Pos (16UL)
3010 #define PPB_NVIC_IPR12_PRI_2_Msk (0xff0000UL)
3011 #define PPB_NVIC_IPR12_PRI_3_Pos (24UL)
3012 #define PPB_NVIC_IPR12_PRI_3_Msk (0xff000000UL)
3014 /* ------------------------------- PPB_NVIC_IPR13 ------------------------------- */
3015 #define PPB_NVIC_IPR13_PRI_0_Pos (0UL)
3016 #define PPB_NVIC_IPR13_PRI_0_Msk (0xffUL)
3017 #define PPB_NVIC_IPR13_PRI_1_Pos (8UL)
3018 #define PPB_NVIC_IPR13_PRI_1_Msk (0xff00UL)
3019 #define PPB_NVIC_IPR13_PRI_2_Pos (16UL)
3020 #define PPB_NVIC_IPR13_PRI_2_Msk (0xff0000UL)
3021 #define PPB_NVIC_IPR13_PRI_3_Pos (24UL)
3022 #define PPB_NVIC_IPR13_PRI_3_Msk (0xff000000UL)
3024 /* ------------------------------- PPB_NVIC_IPR14 ------------------------------- */
3025 #define PPB_NVIC_IPR14_PRI_0_Pos (0UL)
3026 #define PPB_NVIC_IPR14_PRI_0_Msk (0xffUL)
3027 #define PPB_NVIC_IPR14_PRI_1_Pos (8UL)
3028 #define PPB_NVIC_IPR14_PRI_1_Msk (0xff00UL)
3029 #define PPB_NVIC_IPR14_PRI_2_Pos (16UL)
3030 #define PPB_NVIC_IPR14_PRI_2_Msk (0xff0000UL)
3031 #define PPB_NVIC_IPR14_PRI_3_Pos (24UL)
3032 #define PPB_NVIC_IPR14_PRI_3_Msk (0xff000000UL)
3034 /* ------------------------------- PPB_NVIC_IPR15 ------------------------------- */
3035 #define PPB_NVIC_IPR15_PRI_0_Pos (0UL)
3036 #define PPB_NVIC_IPR15_PRI_0_Msk (0xffUL)
3037 #define PPB_NVIC_IPR15_PRI_1_Pos (8UL)
3038 #define PPB_NVIC_IPR15_PRI_1_Msk (0xff00UL)
3039 #define PPB_NVIC_IPR15_PRI_2_Pos (16UL)
3040 #define PPB_NVIC_IPR15_PRI_2_Msk (0xff0000UL)
3041 #define PPB_NVIC_IPR15_PRI_3_Pos (24UL)
3042 #define PPB_NVIC_IPR15_PRI_3_Msk (0xff000000UL)
3044 /* ------------------------------- PPB_NVIC_IPR16 ------------------------------- */
3045 #define PPB_NVIC_IPR16_PRI_0_Pos (0UL)
3046 #define PPB_NVIC_IPR16_PRI_0_Msk (0xffUL)
3047 #define PPB_NVIC_IPR16_PRI_1_Pos (8UL)
3048 #define PPB_NVIC_IPR16_PRI_1_Msk (0xff00UL)
3049 #define PPB_NVIC_IPR16_PRI_2_Pos (16UL)
3050 #define PPB_NVIC_IPR16_PRI_2_Msk (0xff0000UL)
3051 #define PPB_NVIC_IPR16_PRI_3_Pos (24UL)
3052 #define PPB_NVIC_IPR16_PRI_3_Msk (0xff000000UL)
3054 /* ------------------------------- PPB_NVIC_IPR17 ------------------------------- */
3055 #define PPB_NVIC_IPR17_PRI_0_Pos (0UL)
3056 #define PPB_NVIC_IPR17_PRI_0_Msk (0xffUL)
3057 #define PPB_NVIC_IPR17_PRI_1_Pos (8UL)
3058 #define PPB_NVIC_IPR17_PRI_1_Msk (0xff00UL)
3059 #define PPB_NVIC_IPR17_PRI_2_Pos (16UL)
3060 #define PPB_NVIC_IPR17_PRI_2_Msk (0xff0000UL)
3061 #define PPB_NVIC_IPR17_PRI_3_Pos (24UL)
3062 #define PPB_NVIC_IPR17_PRI_3_Msk (0xff000000UL)
3064 /* ------------------------------- PPB_NVIC_IPR18 ------------------------------- */
3065 #define PPB_NVIC_IPR18_PRI_0_Pos (0UL)
3066 #define PPB_NVIC_IPR18_PRI_0_Msk (0xffUL)
3067 #define PPB_NVIC_IPR18_PRI_1_Pos (8UL)
3068 #define PPB_NVIC_IPR18_PRI_1_Msk (0xff00UL)
3069 #define PPB_NVIC_IPR18_PRI_2_Pos (16UL)
3070 #define PPB_NVIC_IPR18_PRI_2_Msk (0xff0000UL)
3071 #define PPB_NVIC_IPR18_PRI_3_Pos (24UL)
3072 #define PPB_NVIC_IPR18_PRI_3_Msk (0xff000000UL)
3074 /* ------------------------------- PPB_NVIC_IPR19 ------------------------------- */
3075 #define PPB_NVIC_IPR19_PRI_0_Pos (0UL)
3076 #define PPB_NVIC_IPR19_PRI_0_Msk (0xffUL)
3077 #define PPB_NVIC_IPR19_PRI_1_Pos (8UL)
3078 #define PPB_NVIC_IPR19_PRI_1_Msk (0xff00UL)
3079 #define PPB_NVIC_IPR19_PRI_2_Pos (16UL)
3080 #define PPB_NVIC_IPR19_PRI_2_Msk (0xff0000UL)
3081 #define PPB_NVIC_IPR19_PRI_3_Pos (24UL)
3082 #define PPB_NVIC_IPR19_PRI_3_Msk (0xff000000UL)
3084 /* ------------------------------- PPB_NVIC_IPR20 ------------------------------- */
3085 #define PPB_NVIC_IPR20_PRI_0_Pos (0UL)
3086 #define PPB_NVIC_IPR20_PRI_0_Msk (0xffUL)
3087 #define PPB_NVIC_IPR20_PRI_1_Pos (8UL)
3088 #define PPB_NVIC_IPR20_PRI_1_Msk (0xff00UL)
3089 #define PPB_NVIC_IPR20_PRI_2_Pos (16UL)
3090 #define PPB_NVIC_IPR20_PRI_2_Msk (0xff0000UL)
3091 #define PPB_NVIC_IPR20_PRI_3_Pos (24UL)
3092 #define PPB_NVIC_IPR20_PRI_3_Msk (0xff000000UL)
3094 /* ------------------------------- PPB_NVIC_IPR21 ------------------------------- */
3095 #define PPB_NVIC_IPR21_PRI_0_Pos (0UL)
3096 #define PPB_NVIC_IPR21_PRI_0_Msk (0xffUL)
3097 #define PPB_NVIC_IPR21_PRI_1_Pos (8UL)
3098 #define PPB_NVIC_IPR21_PRI_1_Msk (0xff00UL)
3099 #define PPB_NVIC_IPR21_PRI_2_Pos (16UL)
3100 #define PPB_NVIC_IPR21_PRI_2_Msk (0xff0000UL)
3101 #define PPB_NVIC_IPR21_PRI_3_Pos (24UL)
3102 #define PPB_NVIC_IPR21_PRI_3_Msk (0xff000000UL)
3104 /* ------------------------------- PPB_NVIC_IPR22 ------------------------------- */
3105 #define PPB_NVIC_IPR22_PRI_0_Pos (0UL)
3106 #define PPB_NVIC_IPR22_PRI_0_Msk (0xffUL)
3107 #define PPB_NVIC_IPR22_PRI_1_Pos (8UL)
3108 #define PPB_NVIC_IPR22_PRI_1_Msk (0xff00UL)
3109 #define PPB_NVIC_IPR22_PRI_2_Pos (16UL)
3110 #define PPB_NVIC_IPR22_PRI_2_Msk (0xff0000UL)
3111 #define PPB_NVIC_IPR22_PRI_3_Pos (24UL)
3112 #define PPB_NVIC_IPR22_PRI_3_Msk (0xff000000UL)
3114 /* ------------------------------- PPB_NVIC_IPR23 ------------------------------- */
3115 #define PPB_NVIC_IPR23_PRI_0_Pos (0UL)
3116 #define PPB_NVIC_IPR23_PRI_0_Msk (0xffUL)
3117 #define PPB_NVIC_IPR23_PRI_1_Pos (8UL)
3118 #define PPB_NVIC_IPR23_PRI_1_Msk (0xff00UL)
3119 #define PPB_NVIC_IPR23_PRI_2_Pos (16UL)
3120 #define PPB_NVIC_IPR23_PRI_2_Msk (0xff0000UL)
3121 #define PPB_NVIC_IPR23_PRI_3_Pos (24UL)
3122 #define PPB_NVIC_IPR23_PRI_3_Msk (0xff000000UL)
3124 /* ------------------------------- PPB_NVIC_IPR24 ------------------------------- */
3125 #define PPB_NVIC_IPR24_PRI_0_Pos (0UL)
3126 #define PPB_NVIC_IPR24_PRI_0_Msk (0xffUL)
3127 #define PPB_NVIC_IPR24_PRI_1_Pos (8UL)
3128 #define PPB_NVIC_IPR24_PRI_1_Msk (0xff00UL)
3129 #define PPB_NVIC_IPR24_PRI_2_Pos (16UL)
3130 #define PPB_NVIC_IPR24_PRI_2_Msk (0xff0000UL)
3131 #define PPB_NVIC_IPR24_PRI_3_Pos (24UL)
3132 #define PPB_NVIC_IPR24_PRI_3_Msk (0xff000000UL)
3134 /* ------------------------------- PPB_NVIC_IPR25 ------------------------------- */
3135 #define PPB_NVIC_IPR25_PRI_0_Pos (0UL)
3136 #define PPB_NVIC_IPR25_PRI_0_Msk (0xffUL)
3137 #define PPB_NVIC_IPR25_PRI_1_Pos (8UL)
3138 #define PPB_NVIC_IPR25_PRI_1_Msk (0xff00UL)
3139 #define PPB_NVIC_IPR25_PRI_2_Pos (16UL)
3140 #define PPB_NVIC_IPR25_PRI_2_Msk (0xff0000UL)
3141 #define PPB_NVIC_IPR25_PRI_3_Pos (24UL)
3142 #define PPB_NVIC_IPR25_PRI_3_Msk (0xff000000UL)
3144 /* ------------------------------- PPB_NVIC_IPR26 ------------------------------- */
3145 #define PPB_NVIC_IPR26_PRI_0_Pos (0UL)
3146 #define PPB_NVIC_IPR26_PRI_0_Msk (0xffUL)
3147 #define PPB_NVIC_IPR26_PRI_1_Pos (8UL)
3148 #define PPB_NVIC_IPR26_PRI_1_Msk (0xff00UL)
3149 #define PPB_NVIC_IPR26_PRI_2_Pos (16UL)
3150 #define PPB_NVIC_IPR26_PRI_2_Msk (0xff0000UL)
3151 #define PPB_NVIC_IPR26_PRI_3_Pos (24UL)
3152 #define PPB_NVIC_IPR26_PRI_3_Msk (0xff000000UL)
3154 /* ------------------------------- PPB_NVIC_IPR27 ------------------------------- */
3155 #define PPB_NVIC_IPR27_PRI_0_Pos (0UL)
3156 #define PPB_NVIC_IPR27_PRI_0_Msk (0xffUL)
3157 #define PPB_NVIC_IPR27_PRI_1_Pos (8UL)
3158 #define PPB_NVIC_IPR27_PRI_1_Msk (0xff00UL)
3159 #define PPB_NVIC_IPR27_PRI_2_Pos (16UL)
3160 #define PPB_NVIC_IPR27_PRI_2_Msk (0xff0000UL)
3161 #define PPB_NVIC_IPR27_PRI_3_Pos (24UL)
3162 #define PPB_NVIC_IPR27_PRI_3_Msk (0xff000000UL)
3164 /* ---------------------------------- PPB_CPUID --------------------------------- */
3165 #define PPB_CPUID_Revision_Pos (0UL)
3166 #define PPB_CPUID_Revision_Msk (0xfUL)
3167 #define PPB_CPUID_PartNo_Pos (4UL)
3168 #define PPB_CPUID_PartNo_Msk (0xfff0UL)
3169 #define PPB_CPUID_Constant_Pos (16UL)
3170 #define PPB_CPUID_Constant_Msk (0xf0000UL)
3171 #define PPB_CPUID_Variant_Pos (20UL)
3172 #define PPB_CPUID_Variant_Msk (0xf00000UL)
3173 #define PPB_CPUID_Implementer_Pos (24UL)
3174 #define PPB_CPUID_Implementer_Msk (0xff000000UL)
3176 /* ---------------------------------- PPB_ICSR ---------------------------------- */
3177 #define PPB_ICSR_VECTACTIVE_Pos (0UL)
3178 #define PPB_ICSR_VECTACTIVE_Msk (0x1ffUL)
3179 #define PPB_ICSR_RETTOBASE_Pos (11UL)
3180 #define PPB_ICSR_RETTOBASE_Msk (0x800UL)
3181 #define PPB_ICSR_VECTPENDING_Pos (12UL)
3182 #define PPB_ICSR_VECTPENDING_Msk (0x3f000UL)
3183 #define PPB_ICSR_ISRPENDING_Pos (22UL)
3184 #define PPB_ICSR_ISRPENDING_Msk (0x400000UL)
3185 #define PPB_ICSR_PENDSTCLR_Pos (25UL)
3186 #define PPB_ICSR_PENDSTCLR_Msk (0x2000000UL)
3187 #define PPB_ICSR_PENDSTSET_Pos (26UL)
3188 #define PPB_ICSR_PENDSTSET_Msk (0x4000000UL)
3189 #define PPB_ICSR_PENDSVCLR_Pos (27UL)
3190 #define PPB_ICSR_PENDSVCLR_Msk (0x8000000UL)
3191 #define PPB_ICSR_PENDSVSET_Pos (28UL)
3192 #define PPB_ICSR_PENDSVSET_Msk (0x10000000UL)
3193 #define PPB_ICSR_NMIPENDSET_Pos (31UL)
3194 #define PPB_ICSR_NMIPENDSET_Msk (0x80000000UL)
3196 /* ---------------------------------- PPB_VTOR ---------------------------------- */
3197 #define PPB_VTOR_TBLOFF_Pos (10UL)
3198 #define PPB_VTOR_TBLOFF_Msk (0xfffffc00UL)
3200 /* ---------------------------------- PPB_AIRCR --------------------------------- */
3201 #define PPB_AIRCR_VECTRESET_Pos (0UL)
3202 #define PPB_AIRCR_VECTRESET_Msk (0x1UL)
3203 #define PPB_AIRCR_VECTCLRACTIVE_Pos (1UL)
3204 #define PPB_AIRCR_VECTCLRACTIVE_Msk (0x2UL)
3205 #define PPB_AIRCR_SYSRESETREQ_Pos (2UL)
3206 #define PPB_AIRCR_SYSRESETREQ_Msk (0x4UL)
3207 #define PPB_AIRCR_PRIGROUP_Pos (8UL)
3208 #define PPB_AIRCR_PRIGROUP_Msk (0x700UL)
3209 #define PPB_AIRCR_ENDIANNESS_Pos (15UL)
3210 #define PPB_AIRCR_ENDIANNESS_Msk (0x8000UL)
3211 #define PPB_AIRCR_VECTKEY_Pos (16UL)
3212 #define PPB_AIRCR_VECTKEY_Msk (0xffff0000UL)
3214 /* ----------------------------------- PPB_SCR ---------------------------------- */
3215 #define PPB_SCR_SLEEPONEXIT_Pos (1UL)
3216 #define PPB_SCR_SLEEPONEXIT_Msk (0x2UL)
3217 #define PPB_SCR_SLEEPDEEP_Pos (2UL)
3218 #define PPB_SCR_SLEEPDEEP_Msk (0x4UL)
3219 #define PPB_SCR_SEVONPEND_Pos (4UL)
3220 #define PPB_SCR_SEVONPEND_Msk (0x10UL)
3222 /* ----------------------------------- PPB_CCR ---------------------------------- */
3223 #define PPB_CCR_NONBASETHRDENA_Pos (0UL)
3224 #define PPB_CCR_NONBASETHRDENA_Msk (0x1UL)
3225 #define PPB_CCR_USERSETMPEND_Pos (1UL)
3226 #define PPB_CCR_USERSETMPEND_Msk (0x2UL)
3227 #define PPB_CCR_UNALIGN_TRP_Pos (3UL)
3228 #define PPB_CCR_UNALIGN_TRP_Msk (0x8UL)
3229 #define PPB_CCR_DIV_0_TRP_Pos (4UL)
3230 #define PPB_CCR_DIV_0_TRP_Msk (0x10UL)
3231 #define PPB_CCR_BFHFNMIGN_Pos (8UL)
3232 #define PPB_CCR_BFHFNMIGN_Msk (0x100UL)
3233 #define PPB_CCR_STKALIGN_Pos (9UL)
3234 #define PPB_CCR_STKALIGN_Msk (0x200UL)
3236 /* ---------------------------------- PPB_SHPR1 --------------------------------- */
3237 #define PPB_SHPR1_PRI_4_Pos (0UL)
3238 #define PPB_SHPR1_PRI_4_Msk (0xffUL)
3239 #define PPB_SHPR1_PRI_5_Pos (8UL)
3240 #define PPB_SHPR1_PRI_5_Msk (0xff00UL)
3241 #define PPB_SHPR1_PRI_6_Pos (16UL)
3242 #define PPB_SHPR1_PRI_6_Msk (0xff0000UL)
3244 /* ---------------------------------- PPB_SHPR2 --------------------------------- */
3245 #define PPB_SHPR2_PRI_11_Pos (24UL)
3246 #define PPB_SHPR2_PRI_11_Msk (0xff000000UL)
3248 /* ---------------------------------- PPB_SHPR3 --------------------------------- */
3249 #define PPB_SHPR3_PRI_14_Pos (16UL)
3250 #define PPB_SHPR3_PRI_14_Msk (0xff0000UL)
3251 #define PPB_SHPR3_PRI_15_Pos (24UL)
3252 #define PPB_SHPR3_PRI_15_Msk (0xff000000UL)
3254 /* ---------------------------------- PPB_SHCSR --------------------------------- */
3255 #define PPB_SHCSR_MEMFAULTACT_Pos (0UL)
3256 #define PPB_SHCSR_MEMFAULTACT_Msk (0x1UL)
3257 #define PPB_SHCSR_BUSFAULTACT_Pos (1UL)
3258 #define PPB_SHCSR_BUSFAULTACT_Msk (0x2UL)
3259 #define PPB_SHCSR_USGFAULTACT_Pos (3UL)
3260 #define PPB_SHCSR_USGFAULTACT_Msk (0x8UL)
3261 #define PPB_SHCSR_SVCALLACT_Pos (7UL)
3262 #define PPB_SHCSR_SVCALLACT_Msk (0x80UL)
3263 #define PPB_SHCSR_MONITORACT_Pos (8UL)
3264 #define PPB_SHCSR_MONITORACT_Msk (0x100UL)
3265 #define PPB_SHCSR_PENDSVACT_Pos (10UL)
3266 #define PPB_SHCSR_PENDSVACT_Msk (0x400UL)
3267 #define PPB_SHCSR_SYSTICKACT_Pos (11UL)
3268 #define PPB_SHCSR_SYSTICKACT_Msk (0x800UL)
3269 #define PPB_SHCSR_USGFAULTPENDED_Pos (12UL)
3270 #define PPB_SHCSR_USGFAULTPENDED_Msk (0x1000UL)
3271 #define PPB_SHCSR_MEMFAULTPENDED_Pos (13UL)
3272 #define PPB_SHCSR_MEMFAULTPENDED_Msk (0x2000UL)
3273 #define PPB_SHCSR_BUSFAULTPENDED_Pos (14UL)
3274 #define PPB_SHCSR_BUSFAULTPENDED_Msk (0x4000UL)
3275 #define PPB_SHCSR_SVCALLPENDED_Pos (15UL)
3276 #define PPB_SHCSR_SVCALLPENDED_Msk (0x8000UL)
3277 #define PPB_SHCSR_MEMFAULTENA_Pos (16UL)
3278 #define PPB_SHCSR_MEMFAULTENA_Msk (0x10000UL)
3279 #define PPB_SHCSR_BUSFAULTENA_Pos (17UL)
3280 #define PPB_SHCSR_BUSFAULTENA_Msk (0x20000UL)
3281 #define PPB_SHCSR_USGFAULTENA_Pos (18UL)
3282 #define PPB_SHCSR_USGFAULTENA_Msk (0x40000UL)
3284 /* ---------------------------------- PPB_CFSR ---------------------------------- */
3285 #define PPB_CFSR_IACCVIOL_Pos (0UL)
3286 #define PPB_CFSR_IACCVIOL_Msk (0x1UL)
3287 #define PPB_CFSR_DACCVIOL_Pos (1UL)
3288 #define PPB_CFSR_DACCVIOL_Msk (0x2UL)
3289 #define PPB_CFSR_MUNSTKERR_Pos (3UL)
3290 #define PPB_CFSR_MUNSTKERR_Msk (0x8UL)
3291 #define PPB_CFSR_MSTKERR_Pos (4UL)
3292 #define PPB_CFSR_MSTKERR_Msk (0x10UL)
3293 #define PPB_CFSR_MLSPERR_Pos (5UL)
3294 #define PPB_CFSR_MLSPERR_Msk (0x20UL)
3295 #define PPB_CFSR_MMARVALID_Pos (7UL)
3296 #define PPB_CFSR_MMARVALID_Msk (0x80UL)
3297 #define PPB_CFSR_IBUSERR_Pos (8UL)
3298 #define PPB_CFSR_IBUSERR_Msk (0x100UL)
3299 #define PPB_CFSR_PRECISERR_Pos (9UL)
3300 #define PPB_CFSR_PRECISERR_Msk (0x200UL)
3301 #define PPB_CFSR_IMPRECISERR_Pos (10UL)
3302 #define PPB_CFSR_IMPRECISERR_Msk (0x400UL)
3303 #define PPB_CFSR_UNSTKERR_Pos (11UL)
3304 #define PPB_CFSR_UNSTKERR_Msk (0x800UL)
3305 #define PPB_CFSR_STKERR_Pos (12UL)
3306 #define PPB_CFSR_STKERR_Msk (0x1000UL)
3307 #define PPB_CFSR_LSPERR_Pos (13UL)
3308 #define PPB_CFSR_LSPERR_Msk (0x2000UL)
3309 #define PPB_CFSR_BFARVALID_Pos (15UL)
3310 #define PPB_CFSR_BFARVALID_Msk (0x8000UL)
3311 #define PPB_CFSR_UNDEFINSTR_Pos (16UL)
3312 #define PPB_CFSR_UNDEFINSTR_Msk (0x10000UL)
3313 #define PPB_CFSR_INVSTATE_Pos (17UL)
3314 #define PPB_CFSR_INVSTATE_Msk (0x20000UL)
3315 #define PPB_CFSR_INVPC_Pos (18UL)
3316 #define PPB_CFSR_INVPC_Msk (0x40000UL)
3317 #define PPB_CFSR_NOCP_Pos (19UL)
3318 #define PPB_CFSR_NOCP_Msk (0x80000UL)
3319 #define PPB_CFSR_UNALIGNED_Pos (24UL)
3320 #define PPB_CFSR_UNALIGNED_Msk (0x1000000UL)
3321 #define PPB_CFSR_DIVBYZERO_Pos (25UL)
3322 #define PPB_CFSR_DIVBYZERO_Msk (0x2000000UL)
3324 /* ---------------------------------- PPB_HFSR ---------------------------------- */
3325 #define PPB_HFSR_VECTTBL_Pos (1UL)
3326 #define PPB_HFSR_VECTTBL_Msk (0x2UL)
3327 #define PPB_HFSR_FORCED_Pos (30UL)
3328 #define PPB_HFSR_FORCED_Msk (0x40000000UL)
3329 #define PPB_HFSR_DEBUGEVT_Pos (31UL)
3330 #define PPB_HFSR_DEBUGEVT_Msk (0x80000000UL)
3332 /* ---------------------------------- PPB_MMFAR --------------------------------- */
3333 #define PPB_MMFAR_ADDRESS_Pos (0UL)
3334 #define PPB_MMFAR_ADDRESS_Msk (0xffffffffUL)
3336 /* ---------------------------------- PPB_BFAR ---------------------------------- */
3337 #define PPB_BFAR_ADDRESS_Pos (0UL)
3338 #define PPB_BFAR_ADDRESS_Msk (0xffffffffUL)
3340 /* ---------------------------------- PPB_AFSR ---------------------------------- */
3341 #define PPB_AFSR_VALUE_Pos (0UL)
3342 #define PPB_AFSR_VALUE_Msk (0xffffffffUL)
3344 /* ---------------------------------- PPB_CPACR --------------------------------- */
3345 #define PPB_CPACR_CP10_Pos (20UL)
3346 #define PPB_CPACR_CP10_Msk (0x300000UL)
3347 #define PPB_CPACR_CP11_Pos (22UL)
3348 #define PPB_CPACR_CP11_Msk (0xc00000UL)
3350 /* -------------------------------- PPB_MPU_TYPE -------------------------------- */
3351 #define PPB_MPU_TYPE_SEPARATE_Pos (0UL)
3352 #define PPB_MPU_TYPE_SEPARATE_Msk (0x1UL)
3353 #define PPB_MPU_TYPE_DREGION_Pos (8UL)
3354 #define PPB_MPU_TYPE_DREGION_Msk (0xff00UL)
3355 #define PPB_MPU_TYPE_IREGION_Pos (16UL)
3356 #define PPB_MPU_TYPE_IREGION_Msk (0xff0000UL)
3358 /* -------------------------------- PPB_MPU_CTRL -------------------------------- */
3359 #define PPB_MPU_CTRL_ENABLE_Pos (0UL)
3360 #define PPB_MPU_CTRL_ENABLE_Msk (0x1UL)
3361 #define PPB_MPU_CTRL_HFNMIENA_Pos (1UL)
3362 #define PPB_MPU_CTRL_HFNMIENA_Msk (0x2UL)
3363 #define PPB_MPU_CTRL_PRIVDEFENA_Pos (2UL)
3364 #define PPB_MPU_CTRL_PRIVDEFENA_Msk (0x4UL)
3366 /* --------------------------------- PPB_MPU_RNR -------------------------------- */
3367 #define PPB_MPU_RNR_REGION_Pos (0UL)
3368 #define PPB_MPU_RNR_REGION_Msk (0xffUL)
3370 /* -------------------------------- PPB_MPU_RBAR -------------------------------- */
3371 #define PPB_MPU_RBAR_REGION_Pos (0UL)
3372 #define PPB_MPU_RBAR_REGION_Msk (0xfUL)
3373 #define PPB_MPU_RBAR_VALID_Pos (4UL)
3374 #define PPB_MPU_RBAR_VALID_Msk (0x10UL)
3375 #define PPB_MPU_RBAR_ADDR_Pos (9UL)
3376 #define PPB_MPU_RBAR_ADDR_Msk (0xfffffe00UL)
3378 /* -------------------------------- PPB_MPU_RASR -------------------------------- */
3379 #define PPB_MPU_RASR_ENABLE_Pos (0UL)
3380 #define PPB_MPU_RASR_ENABLE_Msk (0x1UL)
3381 #define PPB_MPU_RASR_SIZE_Pos (1UL)
3382 #define PPB_MPU_RASR_SIZE_Msk (0x3eUL)
3383 #define PPB_MPU_RASR_SRD_Pos (8UL)
3384 #define PPB_MPU_RASR_SRD_Msk (0xff00UL)
3385 #define PPB_MPU_RASR_B_Pos (16UL)
3386 #define PPB_MPU_RASR_B_Msk (0x10000UL)
3387 #define PPB_MPU_RASR_C_Pos (17UL)
3388 #define PPB_MPU_RASR_C_Msk (0x20000UL)
3389 #define PPB_MPU_RASR_S_Pos (18UL)
3390 #define PPB_MPU_RASR_S_Msk (0x40000UL)
3391 #define PPB_MPU_RASR_TEX_Pos (19UL)
3392 #define PPB_MPU_RASR_TEX_Msk (0x380000UL)
3393 #define PPB_MPU_RASR_AP_Pos (24UL)
3394 #define PPB_MPU_RASR_AP_Msk (0x7000000UL)
3395 #define PPB_MPU_RASR_XN_Pos (28UL)
3396 #define PPB_MPU_RASR_XN_Msk (0x10000000UL)
3398 /* ------------------------------- PPB_MPU_RBAR_A1 ------------------------------ */
3399 #define PPB_MPU_RBAR_A1_REGION_Pos (0UL)
3400 #define PPB_MPU_RBAR_A1_REGION_Msk (0xfUL)
3401 #define PPB_MPU_RBAR_A1_VALID_Pos (4UL)
3402 #define PPB_MPU_RBAR_A1_VALID_Msk (0x10UL)
3403 #define PPB_MPU_RBAR_A1_ADDR_Pos (9UL)
3404 #define PPB_MPU_RBAR_A1_ADDR_Msk (0xfffffe00UL)
3406 /* ------------------------------- PPB_MPU_RASR_A1 ------------------------------ */
3407 #define PPB_MPU_RASR_A1_ENABLE_Pos (0UL)
3408 #define PPB_MPU_RASR_A1_ENABLE_Msk (0x1UL)
3409 #define PPB_MPU_RASR_A1_SIZE_Pos (1UL)
3410 #define PPB_MPU_RASR_A1_SIZE_Msk (0x3eUL)
3411 #define PPB_MPU_RASR_A1_SRD_Pos (8UL)
3412 #define PPB_MPU_RASR_A1_SRD_Msk (0xff00UL)
3413 #define PPB_MPU_RASR_A1_B_Pos (16UL)
3414 #define PPB_MPU_RASR_A1_B_Msk (0x10000UL)
3415 #define PPB_MPU_RASR_A1_C_Pos (17UL)
3416 #define PPB_MPU_RASR_A1_C_Msk (0x20000UL)
3417 #define PPB_MPU_RASR_A1_S_Pos (18UL)
3418 #define PPB_MPU_RASR_A1_S_Msk (0x40000UL)
3419 #define PPB_MPU_RASR_A1_TEX_Pos (19UL)
3420 #define PPB_MPU_RASR_A1_TEX_Msk (0x380000UL)
3421 #define PPB_MPU_RASR_A1_AP_Pos (24UL)
3422 #define PPB_MPU_RASR_A1_AP_Msk (0x7000000UL)
3423 #define PPB_MPU_RASR_A1_XN_Pos (28UL)
3424 #define PPB_MPU_RASR_A1_XN_Msk (0x10000000UL)
3426 /* ------------------------------- PPB_MPU_RBAR_A2 ------------------------------ */
3427 #define PPB_MPU_RBAR_A2_REGION_Pos (0UL)
3428 #define PPB_MPU_RBAR_A2_REGION_Msk (0xfUL)
3429 #define PPB_MPU_RBAR_A2_VALID_Pos (4UL)
3430 #define PPB_MPU_RBAR_A2_VALID_Msk (0x10UL)
3431 #define PPB_MPU_RBAR_A2_ADDR_Pos (9UL)
3432 #define PPB_MPU_RBAR_A2_ADDR_Msk (0xfffffe00UL)
3434 /* ------------------------------- PPB_MPU_RASR_A2 ------------------------------ */
3435 #define PPB_MPU_RASR_A2_ENABLE_Pos (0UL)
3436 #define PPB_MPU_RASR_A2_ENABLE_Msk (0x1UL)
3437 #define PPB_MPU_RASR_A2_SIZE_Pos (1UL)
3438 #define PPB_MPU_RASR_A2_SIZE_Msk (0x3eUL)
3439 #define PPB_MPU_RASR_A2_SRD_Pos (8UL)
3440 #define PPB_MPU_RASR_A2_SRD_Msk (0xff00UL)
3441 #define PPB_MPU_RASR_A2_B_Pos (16UL)
3442 #define PPB_MPU_RASR_A2_B_Msk (0x10000UL)
3443 #define PPB_MPU_RASR_A2_C_Pos (17UL)
3444 #define PPB_MPU_RASR_A2_C_Msk (0x20000UL)
3445 #define PPB_MPU_RASR_A2_S_Pos (18UL)
3446 #define PPB_MPU_RASR_A2_S_Msk (0x40000UL)
3447 #define PPB_MPU_RASR_A2_TEX_Pos (19UL)
3448 #define PPB_MPU_RASR_A2_TEX_Msk (0x380000UL)
3449 #define PPB_MPU_RASR_A2_AP_Pos (24UL)
3450 #define PPB_MPU_RASR_A2_AP_Msk (0x7000000UL)
3451 #define PPB_MPU_RASR_A2_XN_Pos (28UL)
3452 #define PPB_MPU_RASR_A2_XN_Msk (0x10000000UL)
3454 /* ------------------------------- PPB_MPU_RBAR_A3 ------------------------------ */
3455 #define PPB_MPU_RBAR_A3_REGION_Pos (0UL)
3456 #define PPB_MPU_RBAR_A3_REGION_Msk (0xfUL)
3457 #define PPB_MPU_RBAR_A3_VALID_Pos (4UL)
3458 #define PPB_MPU_RBAR_A3_VALID_Msk (0x10UL)
3459 #define PPB_MPU_RBAR_A3_ADDR_Pos (9UL)
3460 #define PPB_MPU_RBAR_A3_ADDR_Msk (0xfffffe00UL)
3462 /* ------------------------------- PPB_MPU_RASR_A3 ------------------------------ */
3463 #define PPB_MPU_RASR_A3_ENABLE_Pos (0UL)
3464 #define PPB_MPU_RASR_A3_ENABLE_Msk (0x1UL)
3465 #define PPB_MPU_RASR_A3_SIZE_Pos (1UL)
3466 #define PPB_MPU_RASR_A3_SIZE_Msk (0x3eUL)
3467 #define PPB_MPU_RASR_A3_SRD_Pos (8UL)
3468 #define PPB_MPU_RASR_A3_SRD_Msk (0xff00UL)
3469 #define PPB_MPU_RASR_A3_B_Pos (16UL)
3470 #define PPB_MPU_RASR_A3_B_Msk (0x10000UL)
3471 #define PPB_MPU_RASR_A3_C_Pos (17UL)
3472 #define PPB_MPU_RASR_A3_C_Msk (0x20000UL)
3473 #define PPB_MPU_RASR_A3_S_Pos (18UL)
3474 #define PPB_MPU_RASR_A3_S_Msk (0x40000UL)
3475 #define PPB_MPU_RASR_A3_TEX_Pos (19UL)
3476 #define PPB_MPU_RASR_A3_TEX_Msk (0x380000UL)
3477 #define PPB_MPU_RASR_A3_AP_Pos (24UL)
3478 #define PPB_MPU_RASR_A3_AP_Msk (0x7000000UL)
3479 #define PPB_MPU_RASR_A3_XN_Pos (28UL)
3480 #define PPB_MPU_RASR_A3_XN_Msk (0x10000000UL)
3482 /* ---------------------------------- PPB_STIR ---------------------------------- */
3483 #define PPB_STIR_INTID_Pos (0UL)
3484 #define PPB_STIR_INTID_Msk (0x1ffUL)
3486 /* ---------------------------------- PPB_FPCCR --------------------------------- */
3487 #define PPB_FPCCR_LSPACT_Pos (0UL)
3488 #define PPB_FPCCR_LSPACT_Msk (0x1UL)
3489 #define PPB_FPCCR_USER_Pos (1UL)
3490 #define PPB_FPCCR_USER_Msk (0x2UL)
3491 #define PPB_FPCCR_THREAD_Pos (3UL)
3492 #define PPB_FPCCR_THREAD_Msk (0x8UL)
3493 #define PPB_FPCCR_HFRDY_Pos (4UL)
3494 #define PPB_FPCCR_HFRDY_Msk (0x10UL)
3495 #define PPB_FPCCR_MMRDY_Pos (5UL)
3496 #define PPB_FPCCR_MMRDY_Msk (0x20UL)
3497 #define PPB_FPCCR_BFRDY_Pos (6UL)
3498 #define PPB_FPCCR_BFRDY_Msk (0x40UL)
3499 #define PPB_FPCCR_MONRDY_Pos (8UL)
3500 #define PPB_FPCCR_MONRDY_Msk (0x100UL)
3501 #define PPB_FPCCR_LSPEN_Pos (30UL)
3502 #define PPB_FPCCR_LSPEN_Msk (0x40000000UL)
3503 #define PPB_FPCCR_ASPEN_Pos (31UL)
3504 #define PPB_FPCCR_ASPEN_Msk (0x80000000UL)
3506 /* ---------------------------------- PPB_FPCAR --------------------------------- */
3507 #define PPB_FPCAR_ADDRESS_Pos (3UL)
3508 #define PPB_FPCAR_ADDRESS_Msk (0xfffffff8UL)
3510 /* --------------------------------- PPB_FPDSCR --------------------------------- */
3511 #define PPB_FPDSCR_RMode_Pos (22UL)
3512 #define PPB_FPDSCR_RMode_Msk (0xc00000UL)
3513 #define PPB_FPDSCR_FZ_Pos (24UL)
3514 #define PPB_FPDSCR_FZ_Msk (0x1000000UL)
3515 #define PPB_FPDSCR_DN_Pos (25UL)
3516 #define PPB_FPDSCR_DN_Msk (0x2000000UL)
3517 #define PPB_FPDSCR_AHP_Pos (26UL)
3518 #define PPB_FPDSCR_AHP_Msk (0x4000000UL)
3521 /* ================================================================================ */
3522 /* ================ struct 'DLR' Position & Mask ================ */
3523 /* ================================================================================ */
3524 
3525 
3526 /* --------------------------------- DLR_OVRSTAT -------------------------------- */
3527 #define DLR_OVRSTAT_LN0_Pos (0UL)
3528 #define DLR_OVRSTAT_LN0_Msk (0x1UL)
3529 #define DLR_OVRSTAT_LN1_Pos (1UL)
3530 #define DLR_OVRSTAT_LN1_Msk (0x2UL)
3531 #define DLR_OVRSTAT_LN2_Pos (2UL)
3532 #define DLR_OVRSTAT_LN2_Msk (0x4UL)
3533 #define DLR_OVRSTAT_LN3_Pos (3UL)
3534 #define DLR_OVRSTAT_LN3_Msk (0x8UL)
3535 #define DLR_OVRSTAT_LN4_Pos (4UL)
3536 #define DLR_OVRSTAT_LN4_Msk (0x10UL)
3537 #define DLR_OVRSTAT_LN5_Pos (5UL)
3538 #define DLR_OVRSTAT_LN5_Msk (0x20UL)
3539 #define DLR_OVRSTAT_LN6_Pos (6UL)
3540 #define DLR_OVRSTAT_LN6_Msk (0x40UL)
3541 #define DLR_OVRSTAT_LN7_Pos (7UL)
3542 #define DLR_OVRSTAT_LN7_Msk (0x80UL)
3543 #define DLR_OVRSTAT_LN8_Pos (8UL)
3544 #define DLR_OVRSTAT_LN8_Msk (0x100UL)
3545 #define DLR_OVRSTAT_LN9_Pos (9UL)
3546 #define DLR_OVRSTAT_LN9_Msk (0x200UL)
3547 #define DLR_OVRSTAT_LN10_Pos (10UL)
3548 #define DLR_OVRSTAT_LN10_Msk (0x400UL)
3549 #define DLR_OVRSTAT_LN11_Pos (11UL)
3550 #define DLR_OVRSTAT_LN11_Msk (0x800UL)
3552 /* --------------------------------- DLR_OVRCLR --------------------------------- */
3553 #define DLR_OVRCLR_LN0_Pos (0UL)
3554 #define DLR_OVRCLR_LN0_Msk (0x1UL)
3555 #define DLR_OVRCLR_LN1_Pos (1UL)
3556 #define DLR_OVRCLR_LN1_Msk (0x2UL)
3557 #define DLR_OVRCLR_LN2_Pos (2UL)
3558 #define DLR_OVRCLR_LN2_Msk (0x4UL)
3559 #define DLR_OVRCLR_LN3_Pos (3UL)
3560 #define DLR_OVRCLR_LN3_Msk (0x8UL)
3561 #define DLR_OVRCLR_LN4_Pos (4UL)
3562 #define DLR_OVRCLR_LN4_Msk (0x10UL)
3563 #define DLR_OVRCLR_LN5_Pos (5UL)
3564 #define DLR_OVRCLR_LN5_Msk (0x20UL)
3565 #define DLR_OVRCLR_LN6_Pos (6UL)
3566 #define DLR_OVRCLR_LN6_Msk (0x40UL)
3567 #define DLR_OVRCLR_LN7_Pos (7UL)
3568 #define DLR_OVRCLR_LN7_Msk (0x80UL)
3569 #define DLR_OVRCLR_LN8_Pos (8UL)
3570 #define DLR_OVRCLR_LN8_Msk (0x100UL)
3571 #define DLR_OVRCLR_LN9_Pos (9UL)
3572 #define DLR_OVRCLR_LN9_Msk (0x200UL)
3573 #define DLR_OVRCLR_LN10_Pos (10UL)
3574 #define DLR_OVRCLR_LN10_Msk (0x400UL)
3575 #define DLR_OVRCLR_LN11_Pos (11UL)
3576 #define DLR_OVRCLR_LN11_Msk (0x800UL)
3578 /* --------------------------------- DLR_SRSEL0 --------------------------------- */
3579 #define DLR_SRSEL0_RS0_Pos (0UL)
3580 #define DLR_SRSEL0_RS0_Msk (0xfUL)
3581 #define DLR_SRSEL0_RS1_Pos (4UL)
3582 #define DLR_SRSEL0_RS1_Msk (0xf0UL)
3583 #define DLR_SRSEL0_RS2_Pos (8UL)
3584 #define DLR_SRSEL0_RS2_Msk (0xf00UL)
3585 #define DLR_SRSEL0_RS3_Pos (12UL)
3586 #define DLR_SRSEL0_RS3_Msk (0xf000UL)
3587 #define DLR_SRSEL0_RS4_Pos (16UL)
3588 #define DLR_SRSEL0_RS4_Msk (0xf0000UL)
3589 #define DLR_SRSEL0_RS5_Pos (20UL)
3590 #define DLR_SRSEL0_RS5_Msk (0xf00000UL)
3591 #define DLR_SRSEL0_RS6_Pos (24UL)
3592 #define DLR_SRSEL0_RS6_Msk (0xf000000UL)
3593 #define DLR_SRSEL0_RS7_Pos (28UL)
3594 #define DLR_SRSEL0_RS7_Msk (0xf0000000UL)
3596 /* --------------------------------- DLR_SRSEL1 --------------------------------- */
3597 #define DLR_SRSEL1_RS8_Pos (0UL)
3598 #define DLR_SRSEL1_RS8_Msk (0xfUL)
3599 #define DLR_SRSEL1_RS9_Pos (4UL)
3600 #define DLR_SRSEL1_RS9_Msk (0xf0UL)
3601 #define DLR_SRSEL1_RS10_Pos (8UL)
3602 #define DLR_SRSEL1_RS10_Msk (0xf00UL)
3603 #define DLR_SRSEL1_RS11_Pos (12UL)
3604 #define DLR_SRSEL1_RS11_Msk (0xf000UL)
3606 /* ---------------------------------- DLR_LNEN ---------------------------------- */
3607 #define DLR_LNEN_LN0_Pos (0UL)
3608 #define DLR_LNEN_LN0_Msk (0x1UL)
3609 #define DLR_LNEN_LN1_Pos (1UL)
3610 #define DLR_LNEN_LN1_Msk (0x2UL)
3611 #define DLR_LNEN_LN2_Pos (2UL)
3612 #define DLR_LNEN_LN2_Msk (0x4UL)
3613 #define DLR_LNEN_LN3_Pos (3UL)
3614 #define DLR_LNEN_LN3_Msk (0x8UL)
3615 #define DLR_LNEN_LN4_Pos (4UL)
3616 #define DLR_LNEN_LN4_Msk (0x10UL)
3617 #define DLR_LNEN_LN5_Pos (5UL)
3618 #define DLR_LNEN_LN5_Msk (0x20UL)
3619 #define DLR_LNEN_LN6_Pos (6UL)
3620 #define DLR_LNEN_LN6_Msk (0x40UL)
3621 #define DLR_LNEN_LN7_Pos (7UL)
3622 #define DLR_LNEN_LN7_Msk (0x80UL)
3623 #define DLR_LNEN_LN8_Pos (8UL)
3624 #define DLR_LNEN_LN8_Msk (0x100UL)
3625 #define DLR_LNEN_LN9_Pos (9UL)
3626 #define DLR_LNEN_LN9_Msk (0x200UL)
3627 #define DLR_LNEN_LN10_Pos (10UL)
3628 #define DLR_LNEN_LN10_Msk (0x400UL)
3629 #define DLR_LNEN_LN11_Pos (11UL)
3630 #define DLR_LNEN_LN11_Msk (0x800UL)
3633 /* ================================================================================ */
3634 /* ================ Group 'ERU' Position & Mask ================ */
3635 /* ================================================================================ */
3636 
3637 
3638 /* --------------------------------- ERU_EXISEL --------------------------------- */
3639 #define ERU_EXISEL_EXS0A_Pos (0UL)
3640 #define ERU_EXISEL_EXS0A_Msk (0x3UL)
3641 #define ERU_EXISEL_EXS0B_Pos (2UL)
3642 #define ERU_EXISEL_EXS0B_Msk (0xcUL)
3643 #define ERU_EXISEL_EXS1A_Pos (4UL)
3644 #define ERU_EXISEL_EXS1A_Msk (0x30UL)
3645 #define ERU_EXISEL_EXS1B_Pos (6UL)
3646 #define ERU_EXISEL_EXS1B_Msk (0xc0UL)
3647 #define ERU_EXISEL_EXS2A_Pos (8UL)
3648 #define ERU_EXISEL_EXS2A_Msk (0x300UL)
3649 #define ERU_EXISEL_EXS2B_Pos (10UL)
3650 #define ERU_EXISEL_EXS2B_Msk (0xc00UL)
3651 #define ERU_EXISEL_EXS3A_Pos (12UL)
3652 #define ERU_EXISEL_EXS3A_Msk (0x3000UL)
3653 #define ERU_EXISEL_EXS3B_Pos (14UL)
3654 #define ERU_EXISEL_EXS3B_Msk (0xc000UL)
3656 /* --------------------------------- ERU_EXICON --------------------------------- */
3657 #define ERU_EXICON_PE_Pos (0UL)
3658 #define ERU_EXICON_PE_Msk (0x1UL)
3659 #define ERU_EXICON_LD_Pos (1UL)
3660 #define ERU_EXICON_LD_Msk (0x2UL)
3661 #define ERU_EXICON_RE_Pos (2UL)
3662 #define ERU_EXICON_RE_Msk (0x4UL)
3663 #define ERU_EXICON_FE_Pos (3UL)
3664 #define ERU_EXICON_FE_Msk (0x8UL)
3665 #define ERU_EXICON_OCS_Pos (4UL)
3666 #define ERU_EXICON_OCS_Msk (0x70UL)
3667 #define ERU_EXICON_FL_Pos (7UL)
3668 #define ERU_EXICON_FL_Msk (0x80UL)
3669 #define ERU_EXICON_SS_Pos (8UL)
3670 #define ERU_EXICON_SS_Msk (0x300UL)
3671 #define ERU_EXICON_NA_Pos (10UL)
3672 #define ERU_EXICON_NA_Msk (0x400UL)
3673 #define ERU_EXICON_NB_Pos (11UL)
3674 #define ERU_EXICON_NB_Msk (0x800UL)
3676 /* --------------------------------- ERU_EXOCON --------------------------------- */
3677 #define ERU_EXOCON_ISS_Pos (0UL)
3678 #define ERU_EXOCON_ISS_Msk (0x3UL)
3679 #define ERU_EXOCON_GEEN_Pos (2UL)
3680 #define ERU_EXOCON_GEEN_Msk (0x4UL)
3681 #define ERU_EXOCON_PDR_Pos (3UL)
3682 #define ERU_EXOCON_PDR_Msk (0x8UL)
3683 #define ERU_EXOCON_GP_Pos (4UL)
3684 #define ERU_EXOCON_GP_Msk (0x30UL)
3685 #define ERU_EXOCON_IPEN0_Pos (12UL)
3686 #define ERU_EXOCON_IPEN0_Msk (0x1000UL)
3687 #define ERU_EXOCON_IPEN1_Pos (13UL)
3688 #define ERU_EXOCON_IPEN1_Msk (0x2000UL)
3689 #define ERU_EXOCON_IPEN2_Pos (14UL)
3690 #define ERU_EXOCON_IPEN2_Msk (0x4000UL)
3691 #define ERU_EXOCON_IPEN3_Pos (15UL)
3692 #define ERU_EXOCON_IPEN3_Msk (0x8000UL)
3695 /* ================================================================================ */
3696 /* ================ struct 'GPDMA0' Position & Mask ================ */
3697 /* ================================================================================ */
3698 
3699 
3700 /* -------------------------------- GPDMA0_RAWTFR ------------------------------- */
3701 #define GPDMA0_RAWTFR_CH0_Pos (0UL)
3702 #define GPDMA0_RAWTFR_CH0_Msk (0x1UL)
3703 #define GPDMA0_RAWTFR_CH1_Pos (1UL)
3704 #define GPDMA0_RAWTFR_CH1_Msk (0x2UL)
3705 #define GPDMA0_RAWTFR_CH2_Pos (2UL)
3706 #define GPDMA0_RAWTFR_CH2_Msk (0x4UL)
3707 #define GPDMA0_RAWTFR_CH3_Pos (3UL)
3708 #define GPDMA0_RAWTFR_CH3_Msk (0x8UL)
3709 #define GPDMA0_RAWTFR_CH4_Pos (4UL)
3710 #define GPDMA0_RAWTFR_CH4_Msk (0x10UL)
3711 #define GPDMA0_RAWTFR_CH5_Pos (5UL)
3712 #define GPDMA0_RAWTFR_CH5_Msk (0x20UL)
3713 #define GPDMA0_RAWTFR_CH6_Pos (6UL)
3714 #define GPDMA0_RAWTFR_CH6_Msk (0x40UL)
3715 #define GPDMA0_RAWTFR_CH7_Pos (7UL)
3716 #define GPDMA0_RAWTFR_CH7_Msk (0x80UL)
3718 /* ------------------------------- GPDMA0_RAWBLOCK ------------------------------ */
3719 #define GPDMA0_RAWBLOCK_CH0_Pos (0UL)
3720 #define GPDMA0_RAWBLOCK_CH0_Msk (0x1UL)
3721 #define GPDMA0_RAWBLOCK_CH1_Pos (1UL)
3722 #define GPDMA0_RAWBLOCK_CH1_Msk (0x2UL)
3723 #define GPDMA0_RAWBLOCK_CH2_Pos (2UL)
3724 #define GPDMA0_RAWBLOCK_CH2_Msk (0x4UL)
3725 #define GPDMA0_RAWBLOCK_CH3_Pos (3UL)
3726 #define GPDMA0_RAWBLOCK_CH3_Msk (0x8UL)
3727 #define GPDMA0_RAWBLOCK_CH4_Pos (4UL)
3728 #define GPDMA0_RAWBLOCK_CH4_Msk (0x10UL)
3729 #define GPDMA0_RAWBLOCK_CH5_Pos (5UL)
3730 #define GPDMA0_RAWBLOCK_CH5_Msk (0x20UL)
3731 #define GPDMA0_RAWBLOCK_CH6_Pos (6UL)
3732 #define GPDMA0_RAWBLOCK_CH6_Msk (0x40UL)
3733 #define GPDMA0_RAWBLOCK_CH7_Pos (7UL)
3734 #define GPDMA0_RAWBLOCK_CH7_Msk (0x80UL)
3736 /* ------------------------------ GPDMA0_RAWSRCTRAN ----------------------------- */
3737 #define GPDMA0_RAWSRCTRAN_CH0_Pos (0UL)
3738 #define GPDMA0_RAWSRCTRAN_CH0_Msk (0x1UL)
3739 #define GPDMA0_RAWSRCTRAN_CH1_Pos (1UL)
3740 #define GPDMA0_RAWSRCTRAN_CH1_Msk (0x2UL)
3741 #define GPDMA0_RAWSRCTRAN_CH2_Pos (2UL)
3742 #define GPDMA0_RAWSRCTRAN_CH2_Msk (0x4UL)
3743 #define GPDMA0_RAWSRCTRAN_CH3_Pos (3UL)
3744 #define GPDMA0_RAWSRCTRAN_CH3_Msk (0x8UL)
3745 #define GPDMA0_RAWSRCTRAN_CH4_Pos (4UL)
3746 #define GPDMA0_RAWSRCTRAN_CH4_Msk (0x10UL)
3747 #define GPDMA0_RAWSRCTRAN_CH5_Pos (5UL)
3748 #define GPDMA0_RAWSRCTRAN_CH5_Msk (0x20UL)
3749 #define GPDMA0_RAWSRCTRAN_CH6_Pos (6UL)
3750 #define GPDMA0_RAWSRCTRAN_CH6_Msk (0x40UL)
3751 #define GPDMA0_RAWSRCTRAN_CH7_Pos (7UL)
3752 #define GPDMA0_RAWSRCTRAN_CH7_Msk (0x80UL)
3754 /* ------------------------------ GPDMA0_RAWDSTTRAN ----------------------------- */
3755 #define GPDMA0_RAWDSTTRAN_CH0_Pos (0UL)
3756 #define GPDMA0_RAWDSTTRAN_CH0_Msk (0x1UL)
3757 #define GPDMA0_RAWDSTTRAN_CH1_Pos (1UL)
3758 #define GPDMA0_RAWDSTTRAN_CH1_Msk (0x2UL)
3759 #define GPDMA0_RAWDSTTRAN_CH2_Pos (2UL)
3760 #define GPDMA0_RAWDSTTRAN_CH2_Msk (0x4UL)
3761 #define GPDMA0_RAWDSTTRAN_CH3_Pos (3UL)
3762 #define GPDMA0_RAWDSTTRAN_CH3_Msk (0x8UL)
3763 #define GPDMA0_RAWDSTTRAN_CH4_Pos (4UL)
3764 #define GPDMA0_RAWDSTTRAN_CH4_Msk (0x10UL)
3765 #define GPDMA0_RAWDSTTRAN_CH5_Pos (5UL)
3766 #define GPDMA0_RAWDSTTRAN_CH5_Msk (0x20UL)
3767 #define GPDMA0_RAWDSTTRAN_CH6_Pos (6UL)
3768 #define GPDMA0_RAWDSTTRAN_CH6_Msk (0x40UL)
3769 #define GPDMA0_RAWDSTTRAN_CH7_Pos (7UL)
3770 #define GPDMA0_RAWDSTTRAN_CH7_Msk (0x80UL)
3772 /* -------------------------------- GPDMA0_RAWERR ------------------------------- */
3773 #define GPDMA0_RAWERR_CH0_Pos (0UL)
3774 #define GPDMA0_RAWERR_CH0_Msk (0x1UL)
3775 #define GPDMA0_RAWERR_CH1_Pos (1UL)
3776 #define GPDMA0_RAWERR_CH1_Msk (0x2UL)
3777 #define GPDMA0_RAWERR_CH2_Pos (2UL)
3778 #define GPDMA0_RAWERR_CH2_Msk (0x4UL)
3779 #define GPDMA0_RAWERR_CH3_Pos (3UL)
3780 #define GPDMA0_RAWERR_CH3_Msk (0x8UL)
3781 #define GPDMA0_RAWERR_CH4_Pos (4UL)
3782 #define GPDMA0_RAWERR_CH4_Msk (0x10UL)
3783 #define GPDMA0_RAWERR_CH5_Pos (5UL)
3784 #define GPDMA0_RAWERR_CH5_Msk (0x20UL)
3785 #define GPDMA0_RAWERR_CH6_Pos (6UL)
3786 #define GPDMA0_RAWERR_CH6_Msk (0x40UL)
3787 #define GPDMA0_RAWERR_CH7_Pos (7UL)
3788 #define GPDMA0_RAWERR_CH7_Msk (0x80UL)
3790 /* ------------------------------ GPDMA0_STATUSTFR ------------------------------ */
3791 #define GPDMA0_STATUSTFR_CH0_Pos (0UL)
3792 #define GPDMA0_STATUSTFR_CH0_Msk (0x1UL)
3793 #define GPDMA0_STATUSTFR_CH1_Pos (1UL)
3794 #define GPDMA0_STATUSTFR_CH1_Msk (0x2UL)
3795 #define GPDMA0_STATUSTFR_CH2_Pos (2UL)
3796 #define GPDMA0_STATUSTFR_CH2_Msk (0x4UL)
3797 #define GPDMA0_STATUSTFR_CH3_Pos (3UL)
3798 #define GPDMA0_STATUSTFR_CH3_Msk (0x8UL)
3799 #define GPDMA0_STATUSTFR_CH4_Pos (4UL)
3800 #define GPDMA0_STATUSTFR_CH4_Msk (0x10UL)
3801 #define GPDMA0_STATUSTFR_CH5_Pos (5UL)
3802 #define GPDMA0_STATUSTFR_CH5_Msk (0x20UL)
3803 #define GPDMA0_STATUSTFR_CH6_Pos (6UL)
3804 #define GPDMA0_STATUSTFR_CH6_Msk (0x40UL)
3805 #define GPDMA0_STATUSTFR_CH7_Pos (7UL)
3806 #define GPDMA0_STATUSTFR_CH7_Msk (0x80UL)
3808 /* ----------------------------- GPDMA0_STATUSBLOCK ----------------------------- */
3809 #define GPDMA0_STATUSBLOCK_CH0_Pos (0UL)
3810 #define GPDMA0_STATUSBLOCK_CH0_Msk (0x1UL)
3811 #define GPDMA0_STATUSBLOCK_CH1_Pos (1UL)
3812 #define GPDMA0_STATUSBLOCK_CH1_Msk (0x2UL)
3813 #define GPDMA0_STATUSBLOCK_CH2_Pos (2UL)
3814 #define GPDMA0_STATUSBLOCK_CH2_Msk (0x4UL)
3815 #define GPDMA0_STATUSBLOCK_CH3_Pos (3UL)
3816 #define GPDMA0_STATUSBLOCK_CH3_Msk (0x8UL)
3817 #define GPDMA0_STATUSBLOCK_CH4_Pos (4UL)
3818 #define GPDMA0_STATUSBLOCK_CH4_Msk (0x10UL)
3819 #define GPDMA0_STATUSBLOCK_CH5_Pos (5UL)
3820 #define GPDMA0_STATUSBLOCK_CH5_Msk (0x20UL)
3821 #define GPDMA0_STATUSBLOCK_CH6_Pos (6UL)
3822 #define GPDMA0_STATUSBLOCK_CH6_Msk (0x40UL)
3823 #define GPDMA0_STATUSBLOCK_CH7_Pos (7UL)
3824 #define GPDMA0_STATUSBLOCK_CH7_Msk (0x80UL)
3826 /* ---------------------------- GPDMA0_STATUSSRCTRAN ---------------------------- */
3827 #define GPDMA0_STATUSSRCTRAN_CH0_Pos (0UL)
3828 #define GPDMA0_STATUSSRCTRAN_CH0_Msk (0x1UL)
3829 #define GPDMA0_STATUSSRCTRAN_CH1_Pos (1UL)
3830 #define GPDMA0_STATUSSRCTRAN_CH1_Msk (0x2UL)
3831 #define GPDMA0_STATUSSRCTRAN_CH2_Pos (2UL)
3832 #define GPDMA0_STATUSSRCTRAN_CH2_Msk (0x4UL)
3833 #define GPDMA0_STATUSSRCTRAN_CH3_Pos (3UL)
3834 #define GPDMA0_STATUSSRCTRAN_CH3_Msk (0x8UL)
3835 #define GPDMA0_STATUSSRCTRAN_CH4_Pos (4UL)
3836 #define GPDMA0_STATUSSRCTRAN_CH4_Msk (0x10UL)
3837 #define GPDMA0_STATUSSRCTRAN_CH5_Pos (5UL)
3838 #define GPDMA0_STATUSSRCTRAN_CH5_Msk (0x20UL)
3839 #define GPDMA0_STATUSSRCTRAN_CH6_Pos (6UL)
3840 #define GPDMA0_STATUSSRCTRAN_CH6_Msk (0x40UL)
3841 #define GPDMA0_STATUSSRCTRAN_CH7_Pos (7UL)
3842 #define GPDMA0_STATUSSRCTRAN_CH7_Msk (0x80UL)
3844 /* ---------------------------- GPDMA0_STATUSDSTTRAN ---------------------------- */
3845 #define GPDMA0_STATUSDSTTRAN_CH0_Pos (0UL)
3846 #define GPDMA0_STATUSDSTTRAN_CH0_Msk (0x1UL)
3847 #define GPDMA0_STATUSDSTTRAN_CH1_Pos (1UL)
3848 #define GPDMA0_STATUSDSTTRAN_CH1_Msk (0x2UL)
3849 #define GPDMA0_STATUSDSTTRAN_CH2_Pos (2UL)
3850 #define GPDMA0_STATUSDSTTRAN_CH2_Msk (0x4UL)
3851 #define GPDMA0_STATUSDSTTRAN_CH3_Pos (3UL)
3852 #define GPDMA0_STATUSDSTTRAN_CH3_Msk (0x8UL)
3853 #define GPDMA0_STATUSDSTTRAN_CH4_Pos (4UL)
3854 #define GPDMA0_STATUSDSTTRAN_CH4_Msk (0x10UL)
3855 #define GPDMA0_STATUSDSTTRAN_CH5_Pos (5UL)
3856 #define GPDMA0_STATUSDSTTRAN_CH5_Msk (0x20UL)
3857 #define GPDMA0_STATUSDSTTRAN_CH6_Pos (6UL)
3858 #define GPDMA0_STATUSDSTTRAN_CH6_Msk (0x40UL)
3859 #define GPDMA0_STATUSDSTTRAN_CH7_Pos (7UL)
3860 #define GPDMA0_STATUSDSTTRAN_CH7_Msk (0x80UL)
3862 /* ------------------------------ GPDMA0_STATUSERR ------------------------------ */
3863 #define GPDMA0_STATUSERR_CH0_Pos (0UL)
3864 #define GPDMA0_STATUSERR_CH0_Msk (0x1UL)
3865 #define GPDMA0_STATUSERR_CH1_Pos (1UL)
3866 #define GPDMA0_STATUSERR_CH1_Msk (0x2UL)
3867 #define GPDMA0_STATUSERR_CH2_Pos (2UL)
3868 #define GPDMA0_STATUSERR_CH2_Msk (0x4UL)
3869 #define GPDMA0_STATUSERR_CH3_Pos (3UL)
3870 #define GPDMA0_STATUSERR_CH3_Msk (0x8UL)
3871 #define GPDMA0_STATUSERR_CH4_Pos (4UL)
3872 #define GPDMA0_STATUSERR_CH4_Msk (0x10UL)
3873 #define GPDMA0_STATUSERR_CH5_Pos (5UL)
3874 #define GPDMA0_STATUSERR_CH5_Msk (0x20UL)
3875 #define GPDMA0_STATUSERR_CH6_Pos (6UL)
3876 #define GPDMA0_STATUSERR_CH6_Msk (0x40UL)
3877 #define GPDMA0_STATUSERR_CH7_Pos (7UL)
3878 #define GPDMA0_STATUSERR_CH7_Msk (0x80UL)
3880 /* ------------------------------- GPDMA0_MASKTFR ------------------------------- */
3881 #define GPDMA0_MASKTFR_CH0_Pos (0UL)
3882 #define GPDMA0_MASKTFR_CH0_Msk (0x1UL)
3883 #define GPDMA0_MASKTFR_CH1_Pos (1UL)
3884 #define GPDMA0_MASKTFR_CH1_Msk (0x2UL)
3885 #define GPDMA0_MASKTFR_CH2_Pos (2UL)
3886 #define GPDMA0_MASKTFR_CH2_Msk (0x4UL)
3887 #define GPDMA0_MASKTFR_CH3_Pos (3UL)
3888 #define GPDMA0_MASKTFR_CH3_Msk (0x8UL)
3889 #define GPDMA0_MASKTFR_CH4_Pos (4UL)
3890 #define GPDMA0_MASKTFR_CH4_Msk (0x10UL)
3891 #define GPDMA0_MASKTFR_CH5_Pos (5UL)
3892 #define GPDMA0_MASKTFR_CH5_Msk (0x20UL)
3893 #define GPDMA0_MASKTFR_CH6_Pos (6UL)
3894 #define GPDMA0_MASKTFR_CH6_Msk (0x40UL)
3895 #define GPDMA0_MASKTFR_CH7_Pos (7UL)
3896 #define GPDMA0_MASKTFR_CH7_Msk (0x80UL)
3897 #define GPDMA0_MASKTFR_WE_CH0_Pos (8UL)
3898 #define GPDMA0_MASKTFR_WE_CH0_Msk (0x100UL)
3899 #define GPDMA0_MASKTFR_WE_CH1_Pos (9UL)
3900 #define GPDMA0_MASKTFR_WE_CH1_Msk (0x200UL)
3901 #define GPDMA0_MASKTFR_WE_CH2_Pos (10UL)
3902 #define GPDMA0_MASKTFR_WE_CH2_Msk (0x400UL)
3903 #define GPDMA0_MASKTFR_WE_CH3_Pos (11UL)
3904 #define GPDMA0_MASKTFR_WE_CH3_Msk (0x800UL)
3905 #define GPDMA0_MASKTFR_WE_CH4_Pos (12UL)
3906 #define GPDMA0_MASKTFR_WE_CH4_Msk (0x1000UL)
3907 #define GPDMA0_MASKTFR_WE_CH5_Pos (13UL)
3908 #define GPDMA0_MASKTFR_WE_CH5_Msk (0x2000UL)
3909 #define GPDMA0_MASKTFR_WE_CH6_Pos (14UL)
3910 #define GPDMA0_MASKTFR_WE_CH6_Msk (0x4000UL)
3911 #define GPDMA0_MASKTFR_WE_CH7_Pos (15UL)
3912 #define GPDMA0_MASKTFR_WE_CH7_Msk (0x8000UL)
3914 /* ------------------------------ GPDMA0_MASKBLOCK ------------------------------ */
3915 #define GPDMA0_MASKBLOCK_CH0_Pos (0UL)
3916 #define GPDMA0_MASKBLOCK_CH0_Msk (0x1UL)
3917 #define GPDMA0_MASKBLOCK_CH1_Pos (1UL)
3918 #define GPDMA0_MASKBLOCK_CH1_Msk (0x2UL)
3919 #define GPDMA0_MASKBLOCK_CH2_Pos (2UL)
3920 #define GPDMA0_MASKBLOCK_CH2_Msk (0x4UL)
3921 #define GPDMA0_MASKBLOCK_CH3_Pos (3UL)
3922 #define GPDMA0_MASKBLOCK_CH3_Msk (0x8UL)
3923 #define GPDMA0_MASKBLOCK_CH4_Pos (4UL)
3924 #define GPDMA0_MASKBLOCK_CH4_Msk (0x10UL)
3925 #define GPDMA0_MASKBLOCK_CH5_Pos (5UL)
3926 #define GPDMA0_MASKBLOCK_CH5_Msk (0x20UL)
3927 #define GPDMA0_MASKBLOCK_CH6_Pos (6UL)
3928 #define GPDMA0_MASKBLOCK_CH6_Msk (0x40UL)
3929 #define GPDMA0_MASKBLOCK_CH7_Pos (7UL)
3930 #define GPDMA0_MASKBLOCK_CH7_Msk (0x80UL)
3931 #define GPDMA0_MASKBLOCK_WE_CH0_Pos (8UL)
3932 #define GPDMA0_MASKBLOCK_WE_CH0_Msk (0x100UL)
3933 #define GPDMA0_MASKBLOCK_WE_CH1_Pos (9UL)
3934 #define GPDMA0_MASKBLOCK_WE_CH1_Msk (0x200UL)
3935 #define GPDMA0_MASKBLOCK_WE_CH2_Pos (10UL)
3936 #define GPDMA0_MASKBLOCK_WE_CH2_Msk (0x400UL)
3937 #define GPDMA0_MASKBLOCK_WE_CH3_Pos (11UL)
3938 #define GPDMA0_MASKBLOCK_WE_CH3_Msk (0x800UL)
3939 #define GPDMA0_MASKBLOCK_WE_CH4_Pos (12UL)
3940 #define GPDMA0_MASKBLOCK_WE_CH4_Msk (0x1000UL)
3941 #define GPDMA0_MASKBLOCK_WE_CH5_Pos (13UL)
3942 #define GPDMA0_MASKBLOCK_WE_CH5_Msk (0x2000UL)
3943 #define GPDMA0_MASKBLOCK_WE_CH6_Pos (14UL)
3944 #define GPDMA0_MASKBLOCK_WE_CH6_Msk (0x4000UL)
3945 #define GPDMA0_MASKBLOCK_WE_CH7_Pos (15UL)
3946 #define GPDMA0_MASKBLOCK_WE_CH7_Msk (0x8000UL)
3948 /* ----------------------------- GPDMA0_MASKSRCTRAN ----------------------------- */
3949 #define GPDMA0_MASKSRCTRAN_CH0_Pos (0UL)
3950 #define GPDMA0_MASKSRCTRAN_CH0_Msk (0x1UL)
3951 #define GPDMA0_MASKSRCTRAN_CH1_Pos (1UL)
3952 #define GPDMA0_MASKSRCTRAN_CH1_Msk (0x2UL)
3953 #define GPDMA0_MASKSRCTRAN_CH2_Pos (2UL)
3954 #define GPDMA0_MASKSRCTRAN_CH2_Msk (0x4UL)
3955 #define GPDMA0_MASKSRCTRAN_CH3_Pos (3UL)
3956 #define GPDMA0_MASKSRCTRAN_CH3_Msk (0x8UL)
3957 #define GPDMA0_MASKSRCTRAN_CH4_Pos (4UL)
3958 #define GPDMA0_MASKSRCTRAN_CH4_Msk (0x10UL)
3959 #define GPDMA0_MASKSRCTRAN_CH5_Pos (5UL)
3960 #define GPDMA0_MASKSRCTRAN_CH5_Msk (0x20UL)
3961 #define GPDMA0_MASKSRCTRAN_CH6_Pos (6UL)
3962 #define GPDMA0_MASKSRCTRAN_CH6_Msk (0x40UL)
3963 #define GPDMA0_MASKSRCTRAN_CH7_Pos (7UL)
3964 #define GPDMA0_MASKSRCTRAN_CH7_Msk (0x80UL)
3965 #define GPDMA0_MASKSRCTRAN_WE_CH0_Pos (8UL)
3966 #define GPDMA0_MASKSRCTRAN_WE_CH0_Msk (0x100UL)
3967 #define GPDMA0_MASKSRCTRAN_WE_CH1_Pos (9UL)
3968 #define GPDMA0_MASKSRCTRAN_WE_CH1_Msk (0x200UL)
3969 #define GPDMA0_MASKSRCTRAN_WE_CH2_Pos (10UL)
3970 #define GPDMA0_MASKSRCTRAN_WE_CH2_Msk (0x400UL)
3971 #define GPDMA0_MASKSRCTRAN_WE_CH3_Pos (11UL)
3972 #define GPDMA0_MASKSRCTRAN_WE_CH3_Msk (0x800UL)
3973 #define GPDMA0_MASKSRCTRAN_WE_CH4_Pos (12UL)
3974 #define GPDMA0_MASKSRCTRAN_WE_CH4_Msk (0x1000UL)
3975 #define GPDMA0_MASKSRCTRAN_WE_CH5_Pos (13UL)
3976 #define GPDMA0_MASKSRCTRAN_WE_CH5_Msk (0x2000UL)
3977 #define GPDMA0_MASKSRCTRAN_WE_CH6_Pos (14UL)
3978 #define GPDMA0_MASKSRCTRAN_WE_CH6_Msk (0x4000UL)
3979 #define GPDMA0_MASKSRCTRAN_WE_CH7_Pos (15UL)
3980 #define GPDMA0_MASKSRCTRAN_WE_CH7_Msk (0x8000UL)
3982 /* ----------------------------- GPDMA0_MASKDSTTRAN ----------------------------- */
3983 #define GPDMA0_MASKDSTTRAN_CH0_Pos (0UL)
3984 #define GPDMA0_MASKDSTTRAN_CH0_Msk (0x1UL)
3985 #define GPDMA0_MASKDSTTRAN_CH1_Pos (1UL)
3986 #define GPDMA0_MASKDSTTRAN_CH1_Msk (0x2UL)
3987 #define GPDMA0_MASKDSTTRAN_CH2_Pos (2UL)
3988 #define GPDMA0_MASKDSTTRAN_CH2_Msk (0x4UL)
3989 #define GPDMA0_MASKDSTTRAN_CH3_Pos (3UL)
3990 #define GPDMA0_MASKDSTTRAN_CH3_Msk (0x8UL)
3991 #define GPDMA0_MASKDSTTRAN_CH4_Pos (4UL)
3992 #define GPDMA0_MASKDSTTRAN_CH4_Msk (0x10UL)
3993 #define GPDMA0_MASKDSTTRAN_CH5_Pos (5UL)
3994 #define GPDMA0_MASKDSTTRAN_CH5_Msk (0x20UL)
3995 #define GPDMA0_MASKDSTTRAN_CH6_Pos (6UL)
3996 #define GPDMA0_MASKDSTTRAN_CH6_Msk (0x40UL)
3997 #define GPDMA0_MASKDSTTRAN_CH7_Pos (7UL)
3998 #define GPDMA0_MASKDSTTRAN_CH7_Msk (0x80UL)
3999 #define GPDMA0_MASKDSTTRAN_WE_CH0_Pos (8UL)
4000 #define GPDMA0_MASKDSTTRAN_WE_CH0_Msk (0x100UL)
4001 #define GPDMA0_MASKDSTTRAN_WE_CH1_Pos (9UL)
4002 #define GPDMA0_MASKDSTTRAN_WE_CH1_Msk (0x200UL)
4003 #define GPDMA0_MASKDSTTRAN_WE_CH2_Pos (10UL)
4004 #define GPDMA0_MASKDSTTRAN_WE_CH2_Msk (0x400UL)
4005 #define GPDMA0_MASKDSTTRAN_WE_CH3_Pos (11UL)
4006 #define GPDMA0_MASKDSTTRAN_WE_CH3_Msk (0x800UL)
4007 #define GPDMA0_MASKDSTTRAN_WE_CH4_Pos (12UL)
4008 #define GPDMA0_MASKDSTTRAN_WE_CH4_Msk (0x1000UL)
4009 #define GPDMA0_MASKDSTTRAN_WE_CH5_Pos (13UL)
4010 #define GPDMA0_MASKDSTTRAN_WE_CH5_Msk (0x2000UL)
4011 #define GPDMA0_MASKDSTTRAN_WE_CH6_Pos (14UL)
4012 #define GPDMA0_MASKDSTTRAN_WE_CH6_Msk (0x4000UL)
4013 #define GPDMA0_MASKDSTTRAN_WE_CH7_Pos (15UL)
4014 #define GPDMA0_MASKDSTTRAN_WE_CH7_Msk (0x8000UL)
4016 /* ------------------------------- GPDMA0_MASKERR ------------------------------- */
4017 #define GPDMA0_MASKERR_CH0_Pos (0UL)
4018 #define GPDMA0_MASKERR_CH0_Msk (0x1UL)
4019 #define GPDMA0_MASKERR_CH1_Pos (1UL)
4020 #define GPDMA0_MASKERR_CH1_Msk (0x2UL)
4021 #define GPDMA0_MASKERR_CH2_Pos (2UL)
4022 #define GPDMA0_MASKERR_CH2_Msk (0x4UL)
4023 #define GPDMA0_MASKERR_CH3_Pos (3UL)
4024 #define GPDMA0_MASKERR_CH3_Msk (0x8UL)
4025 #define GPDMA0_MASKERR_CH4_Pos (4UL)
4026 #define GPDMA0_MASKERR_CH4_Msk (0x10UL)
4027 #define GPDMA0_MASKERR_CH5_Pos (5UL)
4028 #define GPDMA0_MASKERR_CH5_Msk (0x20UL)
4029 #define GPDMA0_MASKERR_CH6_Pos (6UL)
4030 #define GPDMA0_MASKERR_CH6_Msk (0x40UL)
4031 #define GPDMA0_MASKERR_CH7_Pos (7UL)
4032 #define GPDMA0_MASKERR_CH7_Msk (0x80UL)
4033 #define GPDMA0_MASKERR_WE_CH0_Pos (8UL)
4034 #define GPDMA0_MASKERR_WE_CH0_Msk (0x100UL)
4035 #define GPDMA0_MASKERR_WE_CH1_Pos (9UL)
4036 #define GPDMA0_MASKERR_WE_CH1_Msk (0x200UL)
4037 #define GPDMA0_MASKERR_WE_CH2_Pos (10UL)
4038 #define GPDMA0_MASKERR_WE_CH2_Msk (0x400UL)
4039 #define GPDMA0_MASKERR_WE_CH3_Pos (11UL)
4040 #define GPDMA0_MASKERR_WE_CH3_Msk (0x800UL)
4041 #define GPDMA0_MASKERR_WE_CH4_Pos (12UL)
4042 #define GPDMA0_MASKERR_WE_CH4_Msk (0x1000UL)
4043 #define GPDMA0_MASKERR_WE_CH5_Pos (13UL)
4044 #define GPDMA0_MASKERR_WE_CH5_Msk (0x2000UL)
4045 #define GPDMA0_MASKERR_WE_CH6_Pos (14UL)
4046 #define GPDMA0_MASKERR_WE_CH6_Msk (0x4000UL)
4047 #define GPDMA0_MASKERR_WE_CH7_Pos (15UL)
4048 #define GPDMA0_MASKERR_WE_CH7_Msk (0x8000UL)
4050 /* ------------------------------- GPDMA0_CLEARTFR ------------------------------ */
4051 #define GPDMA0_CLEARTFR_CH0_Pos (0UL)
4052 #define GPDMA0_CLEARTFR_CH0_Msk (0x1UL)
4053 #define GPDMA0_CLEARTFR_CH1_Pos (1UL)
4054 #define GPDMA0_CLEARTFR_CH1_Msk (0x2UL)
4055 #define GPDMA0_CLEARTFR_CH2_Pos (2UL)
4056 #define GPDMA0_CLEARTFR_CH2_Msk (0x4UL)
4057 #define GPDMA0_CLEARTFR_CH3_Pos (3UL)
4058 #define GPDMA0_CLEARTFR_CH3_Msk (0x8UL)
4059 #define GPDMA0_CLEARTFR_CH4_Pos (4UL)
4060 #define GPDMA0_CLEARTFR_CH4_Msk (0x10UL)
4061 #define GPDMA0_CLEARTFR_CH5_Pos (5UL)
4062 #define GPDMA0_CLEARTFR_CH5_Msk (0x20UL)
4063 #define GPDMA0_CLEARTFR_CH6_Pos (6UL)
4064 #define GPDMA0_CLEARTFR_CH6_Msk (0x40UL)
4065 #define GPDMA0_CLEARTFR_CH7_Pos (7UL)
4066 #define GPDMA0_CLEARTFR_CH7_Msk (0x80UL)
4068 /* ------------------------------ GPDMA0_CLEARBLOCK ----------------------------- */
4069 #define GPDMA0_CLEARBLOCK_CH0_Pos (0UL)
4070 #define GPDMA0_CLEARBLOCK_CH0_Msk (0x1UL)
4071 #define GPDMA0_CLEARBLOCK_CH1_Pos (1UL)
4072 #define GPDMA0_CLEARBLOCK_CH1_Msk (0x2UL)
4073 #define GPDMA0_CLEARBLOCK_CH2_Pos (2UL)
4074 #define GPDMA0_CLEARBLOCK_CH2_Msk (0x4UL)
4075 #define GPDMA0_CLEARBLOCK_CH3_Pos (3UL)
4076 #define GPDMA0_CLEARBLOCK_CH3_Msk (0x8UL)
4077 #define GPDMA0_CLEARBLOCK_CH4_Pos (4UL)
4078 #define GPDMA0_CLEARBLOCK_CH4_Msk (0x10UL)
4079 #define GPDMA0_CLEARBLOCK_CH5_Pos (5UL)
4080 #define GPDMA0_CLEARBLOCK_CH5_Msk (0x20UL)
4081 #define GPDMA0_CLEARBLOCK_CH6_Pos (6UL)
4082 #define GPDMA0_CLEARBLOCK_CH6_Msk (0x40UL)
4083 #define GPDMA0_CLEARBLOCK_CH7_Pos (7UL)
4084 #define GPDMA0_CLEARBLOCK_CH7_Msk (0x80UL)
4086 /* ----------------------------- GPDMA0_CLEARSRCTRAN ---------------------------- */
4087 #define GPDMA0_CLEARSRCTRAN_CH0_Pos (0UL)
4088 #define GPDMA0_CLEARSRCTRAN_CH0_Msk (0x1UL)
4089 #define GPDMA0_CLEARSRCTRAN_CH1_Pos (1UL)
4090 #define GPDMA0_CLEARSRCTRAN_CH1_Msk (0x2UL)
4091 #define GPDMA0_CLEARSRCTRAN_CH2_Pos (2UL)
4092 #define GPDMA0_CLEARSRCTRAN_CH2_Msk (0x4UL)
4093 #define GPDMA0_CLEARSRCTRAN_CH3_Pos (3UL)
4094 #define GPDMA0_CLEARSRCTRAN_CH3_Msk (0x8UL)
4095 #define GPDMA0_CLEARSRCTRAN_CH4_Pos (4UL)
4096 #define GPDMA0_CLEARSRCTRAN_CH4_Msk (0x10UL)
4097 #define GPDMA0_CLEARSRCTRAN_CH5_Pos (5UL)
4098 #define GPDMA0_CLEARSRCTRAN_CH5_Msk (0x20UL)
4099 #define GPDMA0_CLEARSRCTRAN_CH6_Pos (6UL)
4100 #define GPDMA0_CLEARSRCTRAN_CH6_Msk (0x40UL)
4101 #define GPDMA0_CLEARSRCTRAN_CH7_Pos (7UL)
4102 #define GPDMA0_CLEARSRCTRAN_CH7_Msk (0x80UL)
4104 /* ----------------------------- GPDMA0_CLEARDSTTRAN ---------------------------- */
4105 #define GPDMA0_CLEARDSTTRAN_CH0_Pos (0UL)
4106 #define GPDMA0_CLEARDSTTRAN_CH0_Msk (0x1UL)
4107 #define GPDMA0_CLEARDSTTRAN_CH1_Pos (1UL)
4108 #define GPDMA0_CLEARDSTTRAN_CH1_Msk (0x2UL)
4109 #define GPDMA0_CLEARDSTTRAN_CH2_Pos (2UL)
4110 #define GPDMA0_CLEARDSTTRAN_CH2_Msk (0x4UL)
4111 #define GPDMA0_CLEARDSTTRAN_CH3_Pos (3UL)
4112 #define GPDMA0_CLEARDSTTRAN_CH3_Msk (0x8UL)
4113 #define GPDMA0_CLEARDSTTRAN_CH4_Pos (4UL)
4114 #define GPDMA0_CLEARDSTTRAN_CH4_Msk (0x10UL)
4115 #define GPDMA0_CLEARDSTTRAN_CH5_Pos (5UL)
4116 #define GPDMA0_CLEARDSTTRAN_CH5_Msk (0x20UL)
4117 #define GPDMA0_CLEARDSTTRAN_CH6_Pos (6UL)
4118 #define GPDMA0_CLEARDSTTRAN_CH6_Msk (0x40UL)
4119 #define GPDMA0_CLEARDSTTRAN_CH7_Pos (7UL)
4120 #define GPDMA0_CLEARDSTTRAN_CH7_Msk (0x80UL)
4122 /* ------------------------------- GPDMA0_CLEARERR ------------------------------ */
4123 #define GPDMA0_CLEARERR_CH0_Pos (0UL)
4124 #define GPDMA0_CLEARERR_CH0_Msk (0x1UL)
4125 #define GPDMA0_CLEARERR_CH1_Pos (1UL)
4126 #define GPDMA0_CLEARERR_CH1_Msk (0x2UL)
4127 #define GPDMA0_CLEARERR_CH2_Pos (2UL)
4128 #define GPDMA0_CLEARERR_CH2_Msk (0x4UL)
4129 #define GPDMA0_CLEARERR_CH3_Pos (3UL)
4130 #define GPDMA0_CLEARERR_CH3_Msk (0x8UL)
4131 #define GPDMA0_CLEARERR_CH4_Pos (4UL)
4132 #define GPDMA0_CLEARERR_CH4_Msk (0x10UL)
4133 #define GPDMA0_CLEARERR_CH5_Pos (5UL)
4134 #define GPDMA0_CLEARERR_CH5_Msk (0x20UL)
4135 #define GPDMA0_CLEARERR_CH6_Pos (6UL)
4136 #define GPDMA0_CLEARERR_CH6_Msk (0x40UL)
4137 #define GPDMA0_CLEARERR_CH7_Pos (7UL)
4138 #define GPDMA0_CLEARERR_CH7_Msk (0x80UL)
4140 /* ------------------------------ GPDMA0_STATUSINT ------------------------------ */
4141 #define GPDMA0_STATUSINT_TFR_Pos (0UL)
4142 #define GPDMA0_STATUSINT_TFR_Msk (0x1UL)
4143 #define GPDMA0_STATUSINT_BLOCK_Pos (1UL)
4144 #define GPDMA0_STATUSINT_BLOCK_Msk (0x2UL)
4145 #define GPDMA0_STATUSINT_SRCT_Pos (2UL)
4146 #define GPDMA0_STATUSINT_SRCT_Msk (0x4UL)
4147 #define GPDMA0_STATUSINT_DSTT_Pos (3UL)
4148 #define GPDMA0_STATUSINT_DSTT_Msk (0x8UL)
4149 #define GPDMA0_STATUSINT_ERR_Pos (4UL)
4150 #define GPDMA0_STATUSINT_ERR_Msk (0x10UL)
4152 /* ------------------------------ GPDMA0_REQSRCREG ------------------------------ */
4153 #define GPDMA0_REQSRCREG_CH0_Pos (0UL)
4154 #define GPDMA0_REQSRCREG_CH0_Msk (0x1UL)
4155 #define GPDMA0_REQSRCREG_CH1_Pos (1UL)
4156 #define GPDMA0_REQSRCREG_CH1_Msk (0x2UL)
4157 #define GPDMA0_REQSRCREG_CH2_Pos (2UL)
4158 #define GPDMA0_REQSRCREG_CH2_Msk (0x4UL)
4159 #define GPDMA0_REQSRCREG_CH3_Pos (3UL)
4160 #define GPDMA0_REQSRCREG_CH3_Msk (0x8UL)
4161 #define GPDMA0_REQSRCREG_CH4_Pos (4UL)
4162 #define GPDMA0_REQSRCREG_CH4_Msk (0x10UL)
4163 #define GPDMA0_REQSRCREG_CH5_Pos (5UL)
4164 #define GPDMA0_REQSRCREG_CH5_Msk (0x20UL)
4165 #define GPDMA0_REQSRCREG_CH6_Pos (6UL)
4166 #define GPDMA0_REQSRCREG_CH6_Msk (0x40UL)
4167 #define GPDMA0_REQSRCREG_CH7_Pos (7UL)
4168 #define GPDMA0_REQSRCREG_CH7_Msk (0x80UL)
4169 #define GPDMA0_REQSRCREG_WE_CH0_Pos (8UL)
4170 #define GPDMA0_REQSRCREG_WE_CH0_Msk (0x100UL)
4171 #define GPDMA0_REQSRCREG_WE_CH1_Pos (9UL)
4172 #define GPDMA0_REQSRCREG_WE_CH1_Msk (0x200UL)
4173 #define GPDMA0_REQSRCREG_WE_CH2_Pos (10UL)
4174 #define GPDMA0_REQSRCREG_WE_CH2_Msk (0x400UL)
4175 #define GPDMA0_REQSRCREG_WE_CH3_Pos (11UL)
4176 #define GPDMA0_REQSRCREG_WE_CH3_Msk (0x800UL)
4177 #define GPDMA0_REQSRCREG_WE_CH4_Pos (12UL)
4178 #define GPDMA0_REQSRCREG_WE_CH4_Msk (0x1000UL)
4179 #define GPDMA0_REQSRCREG_WE_CH5_Pos (13UL)
4180 #define GPDMA0_REQSRCREG_WE_CH5_Msk (0x2000UL)
4181 #define GPDMA0_REQSRCREG_WE_CH6_Pos (14UL)
4182 #define GPDMA0_REQSRCREG_WE_CH6_Msk (0x4000UL)
4183 #define GPDMA0_REQSRCREG_WE_CH7_Pos (15UL)
4184 #define GPDMA0_REQSRCREG_WE_CH7_Msk (0x8000UL)
4186 /* ------------------------------ GPDMA0_REQDSTREG ------------------------------ */
4187 #define GPDMA0_REQDSTREG_CH0_Pos (0UL)
4188 #define GPDMA0_REQDSTREG_CH0_Msk (0x1UL)
4189 #define GPDMA0_REQDSTREG_CH1_Pos (1UL)
4190 #define GPDMA0_REQDSTREG_CH1_Msk (0x2UL)
4191 #define GPDMA0_REQDSTREG_CH2_Pos (2UL)
4192 #define GPDMA0_REQDSTREG_CH2_Msk (0x4UL)
4193 #define GPDMA0_REQDSTREG_CH3_Pos (3UL)
4194 #define GPDMA0_REQDSTREG_CH3_Msk (0x8UL)
4195 #define GPDMA0_REQDSTREG_CH4_Pos (4UL)
4196 #define GPDMA0_REQDSTREG_CH4_Msk (0x10UL)
4197 #define GPDMA0_REQDSTREG_CH5_Pos (5UL)
4198 #define GPDMA0_REQDSTREG_CH5_Msk (0x20UL)
4199 #define GPDMA0_REQDSTREG_CH6_Pos (6UL)
4200 #define GPDMA0_REQDSTREG_CH6_Msk (0x40UL)
4201 #define GPDMA0_REQDSTREG_CH7_Pos (7UL)
4202 #define GPDMA0_REQDSTREG_CH7_Msk (0x80UL)
4203 #define GPDMA0_REQDSTREG_WE_CH0_Pos (8UL)
4204 #define GPDMA0_REQDSTREG_WE_CH0_Msk (0x100UL)
4205 #define GPDMA0_REQDSTREG_WE_CH1_Pos (9UL)
4206 #define GPDMA0_REQDSTREG_WE_CH1_Msk (0x200UL)
4207 #define GPDMA0_REQDSTREG_WE_CH2_Pos (10UL)
4208 #define GPDMA0_REQDSTREG_WE_CH2_Msk (0x400UL)
4209 #define GPDMA0_REQDSTREG_WE_CH3_Pos (11UL)
4210 #define GPDMA0_REQDSTREG_WE_CH3_Msk (0x800UL)
4211 #define GPDMA0_REQDSTREG_WE_CH4_Pos (12UL)
4212 #define GPDMA0_REQDSTREG_WE_CH4_Msk (0x1000UL)
4213 #define GPDMA0_REQDSTREG_WE_CH5_Pos (13UL)
4214 #define GPDMA0_REQDSTREG_WE_CH5_Msk (0x2000UL)
4215 #define GPDMA0_REQDSTREG_WE_CH6_Pos (14UL)
4216 #define GPDMA0_REQDSTREG_WE_CH6_Msk (0x4000UL)
4217 #define GPDMA0_REQDSTREG_WE_CH7_Pos (15UL)
4218 #define GPDMA0_REQDSTREG_WE_CH7_Msk (0x8000UL)
4220 /* ----------------------------- GPDMA0_SGLREQSRCREG ---------------------------- */
4221 #define GPDMA0_SGLREQSRCREG_CH0_Pos (0UL)
4222 #define GPDMA0_SGLREQSRCREG_CH0_Msk (0x1UL)
4223 #define GPDMA0_SGLREQSRCREG_CH1_Pos (1UL)
4224 #define GPDMA0_SGLREQSRCREG_CH1_Msk (0x2UL)
4225 #define GPDMA0_SGLREQSRCREG_CH2_Pos (2UL)
4226 #define GPDMA0_SGLREQSRCREG_CH2_Msk (0x4UL)
4227 #define GPDMA0_SGLREQSRCREG_CH3_Pos (3UL)
4228 #define GPDMA0_SGLREQSRCREG_CH3_Msk (0x8UL)
4229 #define GPDMA0_SGLREQSRCREG_CH4_Pos (4UL)
4230 #define GPDMA0_SGLREQSRCREG_CH4_Msk (0x10UL)
4231 #define GPDMA0_SGLREQSRCREG_CH5_Pos (5UL)
4232 #define GPDMA0_SGLREQSRCREG_CH5_Msk (0x20UL)
4233 #define GPDMA0_SGLREQSRCREG_CH6_Pos (6UL)
4234 #define GPDMA0_SGLREQSRCREG_CH6_Msk (0x40UL)
4235 #define GPDMA0_SGLREQSRCREG_CH7_Pos (7UL)
4236 #define GPDMA0_SGLREQSRCREG_CH7_Msk (0x80UL)
4237 #define GPDMA0_SGLREQSRCREG_WE_CH0_Pos (8UL)
4238 #define GPDMA0_SGLREQSRCREG_WE_CH0_Msk (0x100UL)
4239 #define GPDMA0_SGLREQSRCREG_WE_CH1_Pos (9UL)
4240 #define GPDMA0_SGLREQSRCREG_WE_CH1_Msk (0x200UL)
4241 #define GPDMA0_SGLREQSRCREG_WE_CH2_Pos (10UL)
4242 #define GPDMA0_SGLREQSRCREG_WE_CH2_Msk (0x400UL)
4243 #define GPDMA0_SGLREQSRCREG_WE_CH3_Pos (11UL)
4244 #define GPDMA0_SGLREQSRCREG_WE_CH3_Msk (0x800UL)
4245 #define GPDMA0_SGLREQSRCREG_WE_CH4_Pos (12UL)
4246 #define GPDMA0_SGLREQSRCREG_WE_CH4_Msk (0x1000UL)
4247 #define GPDMA0_SGLREQSRCREG_WE_CH5_Pos (13UL)
4248 #define GPDMA0_SGLREQSRCREG_WE_CH5_Msk (0x2000UL)
4249 #define GPDMA0_SGLREQSRCREG_WE_CH6_Pos (14UL)
4250 #define GPDMA0_SGLREQSRCREG_WE_CH6_Msk (0x4000UL)
4251 #define GPDMA0_SGLREQSRCREG_WE_CH7_Pos (15UL)
4252 #define GPDMA0_SGLREQSRCREG_WE_CH7_Msk (0x8000UL)
4254 /* ----------------------------- GPDMA0_SGLREQDSTREG ---------------------------- */
4255 #define GPDMA0_SGLREQDSTREG_CH0_Pos (0UL)
4256 #define GPDMA0_SGLREQDSTREG_CH0_Msk (0x1UL)
4257 #define GPDMA0_SGLREQDSTREG_CH1_Pos (1UL)
4258 #define GPDMA0_SGLREQDSTREG_CH1_Msk (0x2UL)
4259 #define GPDMA0_SGLREQDSTREG_CH2_Pos (2UL)
4260 #define GPDMA0_SGLREQDSTREG_CH2_Msk (0x4UL)
4261 #define GPDMA0_SGLREQDSTREG_CH3_Pos (3UL)
4262 #define GPDMA0_SGLREQDSTREG_CH3_Msk (0x8UL)
4263 #define GPDMA0_SGLREQDSTREG_CH4_Pos (4UL)
4264 #define GPDMA0_SGLREQDSTREG_CH4_Msk (0x10UL)
4265 #define GPDMA0_SGLREQDSTREG_CH5_Pos (5UL)
4266 #define GPDMA0_SGLREQDSTREG_CH5_Msk (0x20UL)
4267 #define GPDMA0_SGLREQDSTREG_CH6_Pos (6UL)
4268 #define GPDMA0_SGLREQDSTREG_CH6_Msk (0x40UL)
4269 #define GPDMA0_SGLREQDSTREG_CH7_Pos (7UL)
4270 #define GPDMA0_SGLREQDSTREG_CH7_Msk (0x80UL)
4271 #define GPDMA0_SGLREQDSTREG_WE_CH0_Pos (8UL)
4272 #define GPDMA0_SGLREQDSTREG_WE_CH0_Msk (0x100UL)
4273 #define GPDMA0_SGLREQDSTREG_WE_CH1_Pos (9UL)
4274 #define GPDMA0_SGLREQDSTREG_WE_CH1_Msk (0x200UL)
4275 #define GPDMA0_SGLREQDSTREG_WE_CH2_Pos (10UL)
4276 #define GPDMA0_SGLREQDSTREG_WE_CH2_Msk (0x400UL)
4277 #define GPDMA0_SGLREQDSTREG_WE_CH3_Pos (11UL)
4278 #define GPDMA0_SGLREQDSTREG_WE_CH3_Msk (0x800UL)
4279 #define GPDMA0_SGLREQDSTREG_WE_CH4_Pos (12UL)
4280 #define GPDMA0_SGLREQDSTREG_WE_CH4_Msk (0x1000UL)
4281 #define GPDMA0_SGLREQDSTREG_WE_CH5_Pos (13UL)
4282 #define GPDMA0_SGLREQDSTREG_WE_CH5_Msk (0x2000UL)
4283 #define GPDMA0_SGLREQDSTREG_WE_CH6_Pos (14UL)
4284 #define GPDMA0_SGLREQDSTREG_WE_CH6_Msk (0x4000UL)
4285 #define GPDMA0_SGLREQDSTREG_WE_CH7_Pos (15UL)
4286 #define GPDMA0_SGLREQDSTREG_WE_CH7_Msk (0x8000UL)
4288 /* ------------------------------ GPDMA0_LSTSRCREG ------------------------------ */
4289 #define GPDMA0_LSTSRCREG_CH0_Pos (0UL)
4290 #define GPDMA0_LSTSRCREG_CH0_Msk (0x1UL)
4291 #define GPDMA0_LSTSRCREG_CH1_Pos (1UL)
4292 #define GPDMA0_LSTSRCREG_CH1_Msk (0x2UL)
4293 #define GPDMA0_LSTSRCREG_CH2_Pos (2UL)
4294 #define GPDMA0_LSTSRCREG_CH2_Msk (0x4UL)
4295 #define GPDMA0_LSTSRCREG_CH3_Pos (3UL)
4296 #define GPDMA0_LSTSRCREG_CH3_Msk (0x8UL)
4297 #define GPDMA0_LSTSRCREG_CH4_Pos (4UL)
4298 #define GPDMA0_LSTSRCREG_CH4_Msk (0x10UL)
4299 #define GPDMA0_LSTSRCREG_CH5_Pos (5UL)
4300 #define GPDMA0_LSTSRCREG_CH5_Msk (0x20UL)
4301 #define GPDMA0_LSTSRCREG_CH6_Pos (6UL)
4302 #define GPDMA0_LSTSRCREG_CH6_Msk (0x40UL)
4303 #define GPDMA0_LSTSRCREG_CH7_Pos (7UL)
4304 #define GPDMA0_LSTSRCREG_CH7_Msk (0x80UL)
4305 #define GPDMA0_LSTSRCREG_WE_CH0_Pos (8UL)
4306 #define GPDMA0_LSTSRCREG_WE_CH0_Msk (0x100UL)
4307 #define GPDMA0_LSTSRCREG_WE_CH1_Pos (9UL)
4308 #define GPDMA0_LSTSRCREG_WE_CH1_Msk (0x200UL)
4309 #define GPDMA0_LSTSRCREG_WE_CH2_Pos (10UL)
4310 #define GPDMA0_LSTSRCREG_WE_CH2_Msk (0x400UL)
4311 #define GPDMA0_LSTSRCREG_WE_CH3_Pos (11UL)
4312 #define GPDMA0_LSTSRCREG_WE_CH3_Msk (0x800UL)
4313 #define GPDMA0_LSTSRCREG_WE_CH4_Pos (12UL)
4314 #define GPDMA0_LSTSRCREG_WE_CH4_Msk (0x1000UL)
4315 #define GPDMA0_LSTSRCREG_WE_CH5_Pos (13UL)
4316 #define GPDMA0_LSTSRCREG_WE_CH5_Msk (0x2000UL)
4317 #define GPDMA0_LSTSRCREG_WE_CH6_Pos (14UL)
4318 #define GPDMA0_LSTSRCREG_WE_CH6_Msk (0x4000UL)
4319 #define GPDMA0_LSTSRCREG_WE_CH7_Pos (15UL)
4320 #define GPDMA0_LSTSRCREG_WE_CH7_Msk (0x8000UL)
4322 /* ------------------------------ GPDMA0_LSTDSTREG ------------------------------ */
4323 #define GPDMA0_LSTDSTREG_CH0_Pos (0UL)
4324 #define GPDMA0_LSTDSTREG_CH0_Msk (0x1UL)
4325 #define GPDMA0_LSTDSTREG_CH1_Pos (1UL)
4326 #define GPDMA0_LSTDSTREG_CH1_Msk (0x2UL)
4327 #define GPDMA0_LSTDSTREG_CH2_Pos (2UL)
4328 #define GPDMA0_LSTDSTREG_CH2_Msk (0x4UL)
4329 #define GPDMA0_LSTDSTREG_CH3_Pos (3UL)
4330 #define GPDMA0_LSTDSTREG_CH3_Msk (0x8UL)
4331 #define GPDMA0_LSTDSTREG_CH4_Pos (4UL)
4332 #define GPDMA0_LSTDSTREG_CH4_Msk (0x10UL)
4333 #define GPDMA0_LSTDSTREG_CH5_Pos (5UL)
4334 #define GPDMA0_LSTDSTREG_CH5_Msk (0x20UL)
4335 #define GPDMA0_LSTDSTREG_CH6_Pos (6UL)
4336 #define GPDMA0_LSTDSTREG_CH6_Msk (0x40UL)
4337 #define GPDMA0_LSTDSTREG_CH7_Pos (7UL)
4338 #define GPDMA0_LSTDSTREG_CH7_Msk (0x80UL)
4339 #define GPDMA0_LSTDSTREG_WE_CH0_Pos (8UL)
4340 #define GPDMA0_LSTDSTREG_WE_CH0_Msk (0x100UL)
4341 #define GPDMA0_LSTDSTREG_WE_CH1_Pos (9UL)
4342 #define GPDMA0_LSTDSTREG_WE_CH1_Msk (0x200UL)
4343 #define GPDMA0_LSTDSTREG_WE_CH2_Pos (10UL)
4344 #define GPDMA0_LSTDSTREG_WE_CH2_Msk (0x400UL)
4345 #define GPDMA0_LSTDSTREG_WE_CH3_Pos (11UL)
4346 #define GPDMA0_LSTDSTREG_WE_CH3_Msk (0x800UL)
4347 #define GPDMA0_LSTDSTREG_WE_CH4_Pos (12UL)
4348 #define GPDMA0_LSTDSTREG_WE_CH4_Msk (0x1000UL)
4349 #define GPDMA0_LSTDSTREG_WE_CH5_Pos (13UL)
4350 #define GPDMA0_LSTDSTREG_WE_CH5_Msk (0x2000UL)
4351 #define GPDMA0_LSTDSTREG_WE_CH6_Pos (14UL)
4352 #define GPDMA0_LSTDSTREG_WE_CH6_Msk (0x4000UL)
4353 #define GPDMA0_LSTDSTREG_WE_CH7_Pos (15UL)
4354 #define GPDMA0_LSTDSTREG_WE_CH7_Msk (0x8000UL)
4356 /* ------------------------------ GPDMA0_DMACFGREG ------------------------------ */
4357 #define GPDMA0_DMACFGREG_DMA_EN_Pos (0UL)
4358 #define GPDMA0_DMACFGREG_DMA_EN_Msk (0x1UL)
4360 /* ------------------------------- GPDMA0_CHENREG ------------------------------- */
4361 #define GPDMA0_CHENREG_CH_Pos (0UL)
4362 #define GPDMA0_CHENREG_CH_Msk (0xffUL)
4363 #define GPDMA0_CHENREG_WE_CH_Pos (8UL)
4364 #define GPDMA0_CHENREG_WE_CH_Msk (0xff00UL)
4366 /* ---------------------------------- GPDMA0_ID --------------------------------- */
4367 #define GPDMA0_ID_VALUE_Pos (0UL)
4368 #define GPDMA0_ID_VALUE_Msk (0xffffffffUL)
4370 /* --------------------------------- GPDMA0_TYPE -------------------------------- */
4371 #define GPDMA0_TYPE_VALUE_Pos (0UL)
4372 #define GPDMA0_TYPE_VALUE_Msk (0xffffffffUL)
4374 /* ------------------------------- GPDMA0_VERSION ------------------------------- */
4375 #define GPDMA0_VERSION_VALUE_Pos (0UL)
4376 #define GPDMA0_VERSION_VALUE_Msk (0xffffffffUL)
4379 /* ================================================================================ */
4380 /* ================ Group 'GPDMA0_CH0_1' Position & Mask ================ */
4381 /* ================================================================================ */
4382 
4383 
4384 /* ------------------------------ GPDMA0_CH_SAR ------------------------------ */
4385 #define GPDMA0_CH_SAR_SAR_Pos (0UL)
4386 #define GPDMA0_CH_SAR_SAR_Msk (0xffffffffUL)
4388 /* ------------------------------ GPDMA0_CH_DAR ------------------------------ */
4389 #define GPDMA0_CH_DAR_DAR_Pos (0UL)
4390 #define GPDMA0_CH_DAR_DAR_Msk (0xffffffffUL)
4392 /* ------------------------------ GPDMA0_CH_LLP ------------------------------ */
4393 #define GPDMA0_CH_LLP_LOC_Pos (2UL)
4394 #define GPDMA0_CH_LLP_LOC_Msk (0xfffffffcUL)
4396 /* ------------------------------ GPDMA0_CH_CTLL ----------------------------- */
4397 #define GPDMA0_CH_CTLL_INT_EN_Pos (0UL)
4398 #define GPDMA0_CH_CTLL_INT_EN_Msk (0x1UL)
4399 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos (1UL)
4400 #define GPDMA0_CH_CTLL_DST_TR_WIDTH_Msk (0xeUL)
4401 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos (4UL)
4402 #define GPDMA0_CH_CTLL_SRC_TR_WIDTH_Msk (0x70UL)
4403 #define GPDMA0_CH_CTLL_DINC_Pos (7UL)
4404 #define GPDMA0_CH_CTLL_DINC_Msk (0x180UL)
4405 #define GPDMA0_CH_CTLL_SINC_Pos (9UL)
4406 #define GPDMA0_CH_CTLL_SINC_Msk (0x600UL)
4407 #define GPDMA0_CH_CTLL_DEST_MSIZE_Pos (11UL)
4408 #define GPDMA0_CH_CTLL_DEST_MSIZE_Msk (0x3800UL)
4409 #define GPDMA0_CH_CTLL_SRC_MSIZE_Pos (14UL)
4410 #define GPDMA0_CH_CTLL_SRC_MSIZE_Msk (0x1c000UL)
4411 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos (17UL)
4412 #define GPDMA0_CH_CTLL_SRC_GATHER_EN_Msk (0x20000UL)
4413 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos (18UL)
4414 #define GPDMA0_CH_CTLL_DST_SCATTER_EN_Msk (0x40000UL)
4415 #define GPDMA0_CH_CTLL_TT_FC_Pos (20UL)
4416 #define GPDMA0_CH_CTLL_TT_FC_Msk (0x700000UL)
4417 #define GPDMA0_CH_CTLL_LLP_DST_EN_Pos (27UL)
4418 #define GPDMA0_CH_CTLL_LLP_DST_EN_Msk (0x8000000UL)
4419 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Pos (28UL)
4420 #define GPDMA0_CH_CTLL_LLP_SRC_EN_Msk (0x10000000UL)
4422 /* ------------------------------ GPDMA0_CH_CTLH ----------------------------- */
4423 #define GPDMA0_CH_CTLH_BLOCK_TS_Pos (0UL)
4424 #define GPDMA0_CH_CTLH_BLOCK_TS_Msk (0xfffUL)
4425 #define GPDMA0_CH_CTLH_DONE_Pos (12UL)
4426 #define GPDMA0_CH_CTLH_DONE_Msk (0x1000UL)
4428 /* ----------------------------- GPDMA0_CH_SSTAT ----------------------------- */
4429 #define GPDMA0_CH_SSTAT_SSTAT_Pos (0UL)
4430 #define GPDMA0_CH_SSTAT_SSTAT_Msk (0xffffffffUL)
4432 /* ----------------------------- GPDMA0_CH_DSTAT ----------------------------- */
4433 #define GPDMA0_CH_DSTAT_DSTAT_Pos (0UL)
4434 #define GPDMA0_CH_DSTAT_DSTAT_Msk (0xffffffffUL)
4436 /* ---------------------------- GPDMA0_CH_SSTATAR ---------------------------- */
4437 #define GPDMA0_CH_SSTATAR_SSTATAR_Pos (0UL)
4438 #define GPDMA0_CH_SSTATAR_SSTATAR_Msk (0xffffffffUL)
4440 /* ---------------------------- GPDMA0_CH_DSTATAR ---------------------------- */
4441 #define GPDMA0_CH_DSTATAR_DSTATAR_Pos (0UL)
4442 #define GPDMA0_CH_DSTATAR_DSTATAR_Msk (0xffffffffUL)
4444 /* ------------------------------ GPDMA0_CH_CFGL ----------------------------- */
4445 #define GPDMA0_CH_CFGL_CH_PRIOR_Pos (5UL)
4446 #define GPDMA0_CH_CFGL_CH_PRIOR_Msk (0xe0UL)
4447 #define GPDMA0_CH_CFGL_CH_SUSP_Pos (8UL)
4448 #define GPDMA0_CH_CFGL_CH_SUSP_Msk (0x100UL)
4449 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Pos (9UL)
4450 #define GPDMA0_CH_CFGL_FIFO_EMPTY_Msk (0x200UL)
4451 #define GPDMA0_CH_CFGL_HS_SEL_DST_Pos (10UL)
4452 #define GPDMA0_CH_CFGL_HS_SEL_DST_Msk (0x400UL)
4453 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Pos (11UL)
4454 #define GPDMA0_CH_CFGL_HS_SEL_SRC_Msk (0x800UL)
4455 #define GPDMA0_CH_CFGL_LOCK_CH_L_Pos (12UL)
4456 #define GPDMA0_CH_CFGL_LOCK_CH_L_Msk (0x3000UL)
4457 #define GPDMA0_CH_CFGL_LOCK_B_L_Pos (14UL)
4458 #define GPDMA0_CH_CFGL_LOCK_B_L_Msk (0xc000UL)
4459 #define GPDMA0_CH_CFGL_LOCK_CH_Pos (16UL)
4460 #define GPDMA0_CH_CFGL_LOCK_CH_Msk (0x10000UL)
4461 #define GPDMA0_CH_CFGL_LOCK_B_Pos (17UL)
4462 #define GPDMA0_CH_CFGL_LOCK_B_Msk (0x20000UL)
4463 #define GPDMA0_CH_CFGL_DST_HS_POL_Pos (18UL)
4464 #define GPDMA0_CH_CFGL_DST_HS_POL_Msk (0x40000UL)
4465 #define GPDMA0_CH_CFGL_SRC_HS_POL_Pos (19UL)
4466 #define GPDMA0_CH_CFGL_SRC_HS_POL_Msk (0x80000UL)
4467 #define GPDMA0_CH_CFGL_MAX_ABRST_Pos (20UL)
4468 #define GPDMA0_CH_CFGL_MAX_ABRST_Msk (0x3ff00000UL)
4469 #define GPDMA0_CH_CFGL_RELOAD_SRC_Pos (30UL)
4470 #define GPDMA0_CH_CFGL_RELOAD_SRC_Msk (0x40000000UL)
4471 #define GPDMA0_CH_CFGL_RELOAD_DST_Pos (31UL)
4472 #define GPDMA0_CH_CFGL_RELOAD_DST_Msk (0x80000000UL)
4474 /* ------------------------------ GPDMA0_CH_CFGH ----------------------------- */
4475 #define GPDMA0_CH_CFGH_FCMODE_Pos (0UL)
4476 #define GPDMA0_CH_CFGH_FCMODE_Msk (0x1UL)
4477 #define GPDMA0_CH_CFGH_FIFO_MODE_Pos (1UL)
4478 #define GPDMA0_CH_CFGH_FIFO_MODE_Msk (0x2UL)
4479 #define GPDMA0_CH_CFGH_PROTCTL_Pos (2UL)
4480 #define GPDMA0_CH_CFGH_PROTCTL_Msk (0x1cUL)
4481 #define GPDMA0_CH_CFGH_DS_UPD_EN_Pos (5UL)
4482 #define GPDMA0_CH_CFGH_DS_UPD_EN_Msk (0x20UL)
4483 #define GPDMA0_CH_CFGH_SS_UPD_EN_Pos (6UL)
4484 #define GPDMA0_CH_CFGH_SS_UPD_EN_Msk (0x40UL)
4485 #define GPDMA0_CH_CFGH_SRC_PER_Pos (7UL)
4486 #define GPDMA0_CH_CFGH_SRC_PER_Msk (0x780UL)
4487 #define GPDMA0_CH_CFGH_DEST_PER_Pos (11UL)
4488 #define GPDMA0_CH_CFGH_DEST_PER_Msk (0x7800UL)
4490 /* ------------------------------ GPDMA0_CH_SGR ------------------------------ */
4491 #define GPDMA0_CH_SGR_SGI_Pos (0UL)
4492 #define GPDMA0_CH_SGR_SGI_Msk (0xfffffUL)
4493 #define GPDMA0_CH_SGR_SGC_Pos (20UL)
4494 #define GPDMA0_CH_SGR_SGC_Msk (0xfff00000UL)
4496 /* ------------------------------ GPDMA0_CH_DSR ------------------------------ */
4497 #define GPDMA0_CH_DSR_DSI_Pos (0UL)
4498 #define GPDMA0_CH_DSR_DSI_Msk (0xfffffUL)
4499 #define GPDMA0_CH_DSR_DSC_Pos (20UL)
4500 #define GPDMA0_CH_DSR_DSC_Msk (0xfff00000UL)
4503 /* ================================================================================ */
4504 /* ================ struct 'GPDMA1' Position & Mask ================ */
4505 /* ================================================================================ */
4506 
4507 
4508 /* -------------------------------- GPDMA1_RAWTFR ------------------------------- */
4509 #define GPDMA1_RAWTFR_CH0_Pos (0UL)
4510 #define GPDMA1_RAWTFR_CH0_Msk (0x1UL)
4511 #define GPDMA1_RAWTFR_CH1_Pos (1UL)
4512 #define GPDMA1_RAWTFR_CH1_Msk (0x2UL)
4513 #define GPDMA1_RAWTFR_CH2_Pos (2UL)
4514 #define GPDMA1_RAWTFR_CH2_Msk (0x4UL)
4515 #define GPDMA1_RAWTFR_CH3_Pos (3UL)
4516 #define GPDMA1_RAWTFR_CH3_Msk (0x8UL)
4518 /* ------------------------------- GPDMA1_RAWBLOCK ------------------------------ */
4519 #define GPDMA1_RAWBLOCK_CH0_Pos (0UL)
4520 #define GPDMA1_RAWBLOCK_CH0_Msk (0x1UL)
4521 #define GPDMA1_RAWBLOCK_CH1_Pos (1UL)
4522 #define GPDMA1_RAWBLOCK_CH1_Msk (0x2UL)
4523 #define GPDMA1_RAWBLOCK_CH2_Pos (2UL)
4524 #define GPDMA1_RAWBLOCK_CH2_Msk (0x4UL)
4525 #define GPDMA1_RAWBLOCK_CH3_Pos (3UL)
4526 #define GPDMA1_RAWBLOCK_CH3_Msk (0x8UL)
4528 /* ------------------------------ GPDMA1_RAWSRCTRAN ----------------------------- */
4529 #define GPDMA1_RAWSRCTRAN_CH0_Pos (0UL)
4530 #define GPDMA1_RAWSRCTRAN_CH0_Msk (0x1UL)
4531 #define GPDMA1_RAWSRCTRAN_CH1_Pos (1UL)
4532 #define GPDMA1_RAWSRCTRAN_CH1_Msk (0x2UL)
4533 #define GPDMA1_RAWSRCTRAN_CH2_Pos (2UL)
4534 #define GPDMA1_RAWSRCTRAN_CH2_Msk (0x4UL)
4535 #define GPDMA1_RAWSRCTRAN_CH3_Pos (3UL)
4536 #define GPDMA1_RAWSRCTRAN_CH3_Msk (0x8UL)
4538 /* ------------------------------ GPDMA1_RAWDSTTRAN ----------------------------- */
4539 #define GPDMA1_RAWDSTTRAN_CH0_Pos (0UL)
4540 #define GPDMA1_RAWDSTTRAN_CH0_Msk (0x1UL)
4541 #define GPDMA1_RAWDSTTRAN_CH1_Pos (1UL)
4542 #define GPDMA1_RAWDSTTRAN_CH1_Msk (0x2UL)
4543 #define GPDMA1_RAWDSTTRAN_CH2_Pos (2UL)
4544 #define GPDMA1_RAWDSTTRAN_CH2_Msk (0x4UL)
4545 #define GPDMA1_RAWDSTTRAN_CH3_Pos (3UL)
4546 #define GPDMA1_RAWDSTTRAN_CH3_Msk (0x8UL)
4548 /* -------------------------------- GPDMA1_RAWERR ------------------------------- */
4549 #define GPDMA1_RAWERR_CH0_Pos (0UL)
4550 #define GPDMA1_RAWERR_CH0_Msk (0x1UL)
4551 #define GPDMA1_RAWERR_CH1_Pos (1UL)
4552 #define GPDMA1_RAWERR_CH1_Msk (0x2UL)
4553 #define GPDMA1_RAWERR_CH2_Pos (2UL)
4554 #define GPDMA1_RAWERR_CH2_Msk (0x4UL)
4555 #define GPDMA1_RAWERR_CH3_Pos (3UL)
4556 #define GPDMA1_RAWERR_CH3_Msk (0x8UL)
4558 /* ------------------------------ GPDMA1_STATUSTFR ------------------------------ */
4559 #define GPDMA1_STATUSTFR_CH0_Pos (0UL)
4560 #define GPDMA1_STATUSTFR_CH0_Msk (0x1UL)
4561 #define GPDMA1_STATUSTFR_CH1_Pos (1UL)
4562 #define GPDMA1_STATUSTFR_CH1_Msk (0x2UL)
4563 #define GPDMA1_STATUSTFR_CH2_Pos (2UL)
4564 #define GPDMA1_STATUSTFR_CH2_Msk (0x4UL)
4565 #define GPDMA1_STATUSTFR_CH3_Pos (3UL)
4566 #define GPDMA1_STATUSTFR_CH3_Msk (0x8UL)
4568 /* ----------------------------- GPDMA1_STATUSBLOCK ----------------------------- */
4569 #define GPDMA1_STATUSBLOCK_CH0_Pos (0UL)
4570 #define GPDMA1_STATUSBLOCK_CH0_Msk (0x1UL)
4571 #define GPDMA1_STATUSBLOCK_CH1_Pos (1UL)
4572 #define GPDMA1_STATUSBLOCK_CH1_Msk (0x2UL)
4573 #define GPDMA1_STATUSBLOCK_CH2_Pos (2UL)
4574 #define GPDMA1_STATUSBLOCK_CH2_Msk (0x4UL)
4575 #define GPDMA1_STATUSBLOCK_CH3_Pos (3UL)
4576 #define GPDMA1_STATUSBLOCK_CH3_Msk (0x8UL)
4578 /* ---------------------------- GPDMA1_STATUSSRCTRAN ---------------------------- */
4579 #define GPDMA1_STATUSSRCTRAN_CH0_Pos (0UL)
4580 #define GPDMA1_STATUSSRCTRAN_CH0_Msk (0x1UL)
4581 #define GPDMA1_STATUSSRCTRAN_CH1_Pos (1UL)
4582 #define GPDMA1_STATUSSRCTRAN_CH1_Msk (0x2UL)
4583 #define GPDMA1_STATUSSRCTRAN_CH2_Pos (2UL)
4584 #define GPDMA1_STATUSSRCTRAN_CH2_Msk (0x4UL)
4585 #define GPDMA1_STATUSSRCTRAN_CH3_Pos (3UL)
4586 #define GPDMA1_STATUSSRCTRAN_CH3_Msk (0x8UL)
4588 /* ---------------------------- GPDMA1_STATUSDSTTRAN ---------------------------- */
4589 #define GPDMA1_STATUSDSTTRAN_CH0_Pos (0UL)
4590 #define GPDMA1_STATUSDSTTRAN_CH0_Msk (0x1UL)
4591 #define GPDMA1_STATUSDSTTRAN_CH1_Pos (1UL)
4592 #define GPDMA1_STATUSDSTTRAN_CH1_Msk (0x2UL)
4593 #define GPDMA1_STATUSDSTTRAN_CH2_Pos (2UL)
4594 #define GPDMA1_STATUSDSTTRAN_CH2_Msk (0x4UL)
4595 #define GPDMA1_STATUSDSTTRAN_CH3_Pos (3UL)
4596 #define GPDMA1_STATUSDSTTRAN_CH3_Msk (0x8UL)
4598 /* ------------------------------ GPDMA1_STATUSERR ------------------------------ */
4599 #define GPDMA1_STATUSERR_CH0_Pos (0UL)
4600 #define GPDMA1_STATUSERR_CH0_Msk (0x1UL)
4601 #define GPDMA1_STATUSERR_CH1_Pos (1UL)
4602 #define GPDMA1_STATUSERR_CH1_Msk (0x2UL)
4603 #define GPDMA1_STATUSERR_CH2_Pos (2UL)
4604 #define GPDMA1_STATUSERR_CH2_Msk (0x4UL)
4605 #define GPDMA1_STATUSERR_CH3_Pos (3UL)
4606 #define GPDMA1_STATUSERR_CH3_Msk (0x8UL)
4608 /* ------------------------------- GPDMA1_MASKTFR ------------------------------- */
4609 #define GPDMA1_MASKTFR_CH0_Pos (0UL)
4610 #define GPDMA1_MASKTFR_CH0_Msk (0x1UL)
4611 #define GPDMA1_MASKTFR_CH1_Pos (1UL)
4612 #define GPDMA1_MASKTFR_CH1_Msk (0x2UL)
4613 #define GPDMA1_MASKTFR_CH2_Pos (2UL)
4614 #define GPDMA1_MASKTFR_CH2_Msk (0x4UL)
4615 #define GPDMA1_MASKTFR_CH3_Pos (3UL)
4616 #define GPDMA1_MASKTFR_CH3_Msk (0x8UL)
4617 #define GPDMA1_MASKTFR_WE_CH0_Pos (8UL)
4618 #define GPDMA1_MASKTFR_WE_CH0_Msk (0x100UL)
4619 #define GPDMA1_MASKTFR_WE_CH1_Pos (9UL)
4620 #define GPDMA1_MASKTFR_WE_CH1_Msk (0x200UL)
4621 #define GPDMA1_MASKTFR_WE_CH2_Pos (10UL)
4622 #define GPDMA1_MASKTFR_WE_CH2_Msk (0x400UL)
4623 #define GPDMA1_MASKTFR_WE_CH3_Pos (11UL)
4624 #define GPDMA1_MASKTFR_WE_CH3_Msk (0x800UL)
4626 /* ------------------------------ GPDMA1_MASKBLOCK ------------------------------ */
4627 #define GPDMA1_MASKBLOCK_CH0_Pos (0UL)
4628 #define GPDMA1_MASKBLOCK_CH0_Msk (0x1UL)
4629 #define GPDMA1_MASKBLOCK_CH1_Pos (1UL)
4630 #define GPDMA1_MASKBLOCK_CH1_Msk (0x2UL)
4631 #define GPDMA1_MASKBLOCK_CH2_Pos (2UL)
4632 #define GPDMA1_MASKBLOCK_CH2_Msk (0x4UL)
4633 #define GPDMA1_MASKBLOCK_CH3_Pos (3UL)
4634 #define GPDMA1_MASKBLOCK_CH3_Msk (0x8UL)
4635 #define GPDMA1_MASKBLOCK_WE_CH0_Pos (8UL)
4636 #define GPDMA1_MASKBLOCK_WE_CH0_Msk (0x100UL)
4637 #define GPDMA1_MASKBLOCK_WE_CH1_Pos (9UL)
4638 #define GPDMA1_MASKBLOCK_WE_CH1_Msk (0x200UL)
4639 #define GPDMA1_MASKBLOCK_WE_CH2_Pos (10UL)
4640 #define GPDMA1_MASKBLOCK_WE_CH2_Msk (0x400UL)
4641 #define GPDMA1_MASKBLOCK_WE_CH3_Pos (11UL)
4642 #define GPDMA1_MASKBLOCK_WE_CH3_Msk (0x800UL)
4644 /* ----------------------------- GPDMA1_MASKSRCTRAN ----------------------------- */
4645 #define GPDMA1_MASKSRCTRAN_CH0_Pos (0UL)
4646 #define GPDMA1_MASKSRCTRAN_CH0_Msk (0x1UL)
4647 #define GPDMA1_MASKSRCTRAN_CH1_Pos (1UL)
4648 #define GPDMA1_MASKSRCTRAN_CH1_Msk (0x2UL)
4649 #define GPDMA1_MASKSRCTRAN_CH2_Pos (2UL)
4650 #define GPDMA1_MASKSRCTRAN_CH2_Msk (0x4UL)
4651 #define GPDMA1_MASKSRCTRAN_CH3_Pos (3UL)
4652 #define GPDMA1_MASKSRCTRAN_CH3_Msk (0x8UL)
4653 #define GPDMA1_MASKSRCTRAN_WE_CH0_Pos (8UL)
4654 #define GPDMA1_MASKSRCTRAN_WE_CH0_Msk (0x100UL)
4655 #define GPDMA1_MASKSRCTRAN_WE_CH1_Pos (9UL)
4656 #define GPDMA1_MASKSRCTRAN_WE_CH1_Msk (0x200UL)
4657 #define GPDMA1_MASKSRCTRAN_WE_CH2_Pos (10UL)
4658 #define GPDMA1_MASKSRCTRAN_WE_CH2_Msk (0x400UL)
4659 #define GPDMA1_MASKSRCTRAN_WE_CH3_Pos (11UL)
4660 #define GPDMA1_MASKSRCTRAN_WE_CH3_Msk (0x800UL)
4662 /* ----------------------------- GPDMA1_MASKDSTTRAN ----------------------------- */
4663 #define GPDMA1_MASKDSTTRAN_CH0_Pos (0UL)
4664 #define GPDMA1_MASKDSTTRAN_CH0_Msk (0x1UL)
4665 #define GPDMA1_MASKDSTTRAN_CH1_Pos (1UL)
4666 #define GPDMA1_MASKDSTTRAN_CH1_Msk (0x2UL)
4667 #define GPDMA1_MASKDSTTRAN_CH2_Pos (2UL)
4668 #define GPDMA1_MASKDSTTRAN_CH2_Msk (0x4UL)
4669 #define GPDMA1_MASKDSTTRAN_CH3_Pos (3UL)
4670 #define GPDMA1_MASKDSTTRAN_CH3_Msk (0x8UL)
4671 #define GPDMA1_MASKDSTTRAN_WE_CH0_Pos (8UL)
4672 #define GPDMA1_MASKDSTTRAN_WE_CH0_Msk (0x100UL)
4673 #define GPDMA1_MASKDSTTRAN_WE_CH1_Pos (9UL)
4674 #define GPDMA1_MASKDSTTRAN_WE_CH1_Msk (0x200UL)
4675 #define GPDMA1_MASKDSTTRAN_WE_CH2_Pos (10UL)
4676 #define GPDMA1_MASKDSTTRAN_WE_CH2_Msk (0x400UL)
4677 #define GPDMA1_MASKDSTTRAN_WE_CH3_Pos (11UL)
4678 #define GPDMA1_MASKDSTTRAN_WE_CH3_Msk (0x800UL)
4680 /* ------------------------------- GPDMA1_MASKERR ------------------------------- */
4681 #define GPDMA1_MASKERR_CH0_Pos (0UL)
4682 #define GPDMA1_MASKERR_CH0_Msk (0x1UL)
4683 #define GPDMA1_MASKERR_CH1_Pos (1UL)
4684 #define GPDMA1_MASKERR_CH1_Msk (0x2UL)
4685 #define GPDMA1_MASKERR_CH2_Pos (2UL)
4686 #define GPDMA1_MASKERR_CH2_Msk (0x4UL)
4687 #define GPDMA1_MASKERR_CH3_Pos (3UL)
4688 #define GPDMA1_MASKERR_CH3_Msk (0x8UL)
4689 #define GPDMA1_MASKERR_WE_CH0_Pos (8UL)
4690 #define GPDMA1_MASKERR_WE_CH0_Msk (0x100UL)
4691 #define GPDMA1_MASKERR_WE_CH1_Pos (9UL)
4692 #define GPDMA1_MASKERR_WE_CH1_Msk (0x200UL)
4693 #define GPDMA1_MASKERR_WE_CH2_Pos (10UL)
4694 #define GPDMA1_MASKERR_WE_CH2_Msk (0x400UL)
4695 #define GPDMA1_MASKERR_WE_CH3_Pos (11UL)
4696 #define GPDMA1_MASKERR_WE_CH3_Msk (0x800UL)
4698 /* ------------------------------- GPDMA1_CLEARTFR ------------------------------ */
4699 #define GPDMA1_CLEARTFR_CH0_Pos (0UL)
4700 #define GPDMA1_CLEARTFR_CH0_Msk (0x1UL)
4701 #define GPDMA1_CLEARTFR_CH1_Pos (1UL)
4702 #define GPDMA1_CLEARTFR_CH1_Msk (0x2UL)
4703 #define GPDMA1_CLEARTFR_CH2_Pos (2UL)
4704 #define GPDMA1_CLEARTFR_CH2_Msk (0x4UL)
4705 #define GPDMA1_CLEARTFR_CH3_Pos (3UL)
4706 #define GPDMA1_CLEARTFR_CH3_Msk (0x8UL)
4708 /* ------------------------------ GPDMA1_CLEARBLOCK ----------------------------- */
4709 #define GPDMA1_CLEARBLOCK_CH0_Pos (0UL)
4710 #define GPDMA1_CLEARBLOCK_CH0_Msk (0x1UL)
4711 #define GPDMA1_CLEARBLOCK_CH1_Pos (1UL)
4712 #define GPDMA1_CLEARBLOCK_CH1_Msk (0x2UL)
4713 #define GPDMA1_CLEARBLOCK_CH2_Pos (2UL)
4714 #define GPDMA1_CLEARBLOCK_CH2_Msk (0x4UL)
4715 #define GPDMA1_CLEARBLOCK_CH3_Pos (3UL)
4716 #define GPDMA1_CLEARBLOCK_CH3_Msk (0x8UL)
4718 /* ----------------------------- GPDMA1_CLEARSRCTRAN ---------------------------- */
4719 #define GPDMA1_CLEARSRCTRAN_CH0_Pos (0UL)
4720 #define GPDMA1_CLEARSRCTRAN_CH0_Msk (0x1UL)
4721 #define GPDMA1_CLEARSRCTRAN_CH1_Pos (1UL)
4722 #define GPDMA1_CLEARSRCTRAN_CH1_Msk (0x2UL)
4723 #define GPDMA1_CLEARSRCTRAN_CH2_Pos (2UL)
4724 #define GPDMA1_CLEARSRCTRAN_CH2_Msk (0x4UL)
4725 #define GPDMA1_CLEARSRCTRAN_CH3_Pos (3UL)
4726 #define GPDMA1_CLEARSRCTRAN_CH3_Msk (0x8UL)
4728 /* ----------------------------- GPDMA1_CLEARDSTTRAN ---------------------------- */
4729 #define GPDMA1_CLEARDSTTRAN_CH0_Pos (0UL)
4730 #define GPDMA1_CLEARDSTTRAN_CH0_Msk (0x1UL)
4731 #define GPDMA1_CLEARDSTTRAN_CH1_Pos (1UL)
4732 #define GPDMA1_CLEARDSTTRAN_CH1_Msk (0x2UL)
4733 #define GPDMA1_CLEARDSTTRAN_CH2_Pos (2UL)
4734 #define GPDMA1_CLEARDSTTRAN_CH2_Msk (0x4UL)
4735 #define GPDMA1_CLEARDSTTRAN_CH3_Pos (3UL)
4736 #define GPDMA1_CLEARDSTTRAN_CH3_Msk (0x8UL)
4738 /* ------------------------------- GPDMA1_CLEARERR ------------------------------ */
4739 #define GPDMA1_CLEARERR_CH0_Pos (0UL)
4740 #define GPDMA1_CLEARERR_CH0_Msk (0x1UL)
4741 #define GPDMA1_CLEARERR_CH1_Pos (1UL)
4742 #define GPDMA1_CLEARERR_CH1_Msk (0x2UL)
4743 #define GPDMA1_CLEARERR_CH2_Pos (2UL)
4744 #define GPDMA1_CLEARERR_CH2_Msk (0x4UL)
4745 #define GPDMA1_CLEARERR_CH3_Pos (3UL)
4746 #define GPDMA1_CLEARERR_CH3_Msk (0x8UL)
4748 /* ------------------------------ GPDMA1_STATUSINT ------------------------------ */
4749 #define GPDMA1_STATUSINT_TFR_Pos (0UL)
4750 #define GPDMA1_STATUSINT_TFR_Msk (0x1UL)
4751 #define GPDMA1_STATUSINT_BLOCK_Pos (1UL)
4752 #define GPDMA1_STATUSINT_BLOCK_Msk (0x2UL)
4753 #define GPDMA1_STATUSINT_SRCT_Pos (2UL)
4754 #define GPDMA1_STATUSINT_SRCT_Msk (0x4UL)
4755 #define GPDMA1_STATUSINT_DSTT_Pos (3UL)
4756 #define GPDMA1_STATUSINT_DSTT_Msk (0x8UL)
4757 #define GPDMA1_STATUSINT_ERR_Pos (4UL)
4758 #define GPDMA1_STATUSINT_ERR_Msk (0x10UL)
4760 /* ------------------------------ GPDMA1_REQSRCREG ------------------------------ */
4761 #define GPDMA1_REQSRCREG_CH0_Pos (0UL)
4762 #define GPDMA1_REQSRCREG_CH0_Msk (0x1UL)
4763 #define GPDMA1_REQSRCREG_CH1_Pos (1UL)
4764 #define GPDMA1_REQSRCREG_CH1_Msk (0x2UL)
4765 #define GPDMA1_REQSRCREG_CH2_Pos (2UL)
4766 #define GPDMA1_REQSRCREG_CH2_Msk (0x4UL)
4767 #define GPDMA1_REQSRCREG_CH3_Pos (3UL)
4768 #define GPDMA1_REQSRCREG_CH3_Msk (0x8UL)
4769 #define GPDMA1_REQSRCREG_WE_CH0_Pos (8UL)
4770 #define GPDMA1_REQSRCREG_WE_CH0_Msk (0x100UL)
4771 #define GPDMA1_REQSRCREG_WE_CH1_Pos (9UL)
4772 #define GPDMA1_REQSRCREG_WE_CH1_Msk (0x200UL)
4773 #define GPDMA1_REQSRCREG_WE_CH2_Pos (10UL)
4774 #define GPDMA1_REQSRCREG_WE_CH2_Msk (0x400UL)
4775 #define GPDMA1_REQSRCREG_WE_CH3_Pos (11UL)
4776 #define GPDMA1_REQSRCREG_WE_CH3_Msk (0x800UL)
4778 /* ------------------------------ GPDMA1_REQDSTREG ------------------------------ */
4779 #define GPDMA1_REQDSTREG_CH0_Pos (0UL)
4780 #define GPDMA1_REQDSTREG_CH0_Msk (0x1UL)
4781 #define GPDMA1_REQDSTREG_CH1_Pos (1UL)
4782 #define GPDMA1_REQDSTREG_CH1_Msk (0x2UL)
4783 #define GPDMA1_REQDSTREG_CH2_Pos (2UL)
4784 #define GPDMA1_REQDSTREG_CH2_Msk (0x4UL)
4785 #define GPDMA1_REQDSTREG_CH3_Pos (3UL)
4786 #define GPDMA1_REQDSTREG_CH3_Msk (0x8UL)
4787 #define GPDMA1_REQDSTREG_WE_CH0_Pos (8UL)
4788 #define GPDMA1_REQDSTREG_WE_CH0_Msk (0x100UL)
4789 #define GPDMA1_REQDSTREG_WE_CH1_Pos (9UL)
4790 #define GPDMA1_REQDSTREG_WE_CH1_Msk (0x200UL)
4791 #define GPDMA1_REQDSTREG_WE_CH2_Pos (10UL)
4792 #define GPDMA1_REQDSTREG_WE_CH2_Msk (0x400UL)
4793 #define GPDMA1_REQDSTREG_WE_CH3_Pos (11UL)
4794 #define GPDMA1_REQDSTREG_WE_CH3_Msk (0x800UL)
4796 /* ----------------------------- GPDMA1_SGLREQSRCREG ---------------------------- */
4797 #define GPDMA1_SGLREQSRCREG_CH0_Pos (0UL)
4798 #define GPDMA1_SGLREQSRCREG_CH0_Msk (0x1UL)
4799 #define GPDMA1_SGLREQSRCREG_CH1_Pos (1UL)
4800 #define GPDMA1_SGLREQSRCREG_CH1_Msk (0x2UL)
4801 #define GPDMA1_SGLREQSRCREG_CH2_Pos (2UL)
4802 #define GPDMA1_SGLREQSRCREG_CH2_Msk (0x4UL)
4803 #define GPDMA1_SGLREQSRCREG_CH3_Pos (3UL)
4804 #define GPDMA1_SGLREQSRCREG_CH3_Msk (0x8UL)
4805 #define GPDMA1_SGLREQSRCREG_WE_CH0_Pos (8UL)
4806 #define GPDMA1_SGLREQSRCREG_WE_CH0_Msk (0x100UL)
4807 #define GPDMA1_SGLREQSRCREG_WE_CH1_Pos (9UL)
4808 #define GPDMA1_SGLREQSRCREG_WE_CH1_Msk (0x200UL)
4809 #define GPDMA1_SGLREQSRCREG_WE_CH2_Pos (10UL)
4810 #define GPDMA1_SGLREQSRCREG_WE_CH2_Msk (0x400UL)
4811 #define GPDMA1_SGLREQSRCREG_WE_CH3_Pos (11UL)
4812 #define GPDMA1_SGLREQSRCREG_WE_CH3_Msk (0x800UL)
4814 /* ----------------------------- GPDMA1_SGLREQDSTREG ---------------------------- */
4815 #define GPDMA1_SGLREQDSTREG_CH0_Pos (0UL)
4816 #define GPDMA1_SGLREQDSTREG_CH0_Msk (0x1UL)
4817 #define GPDMA1_SGLREQDSTREG_CH1_Pos (1UL)
4818 #define GPDMA1_SGLREQDSTREG_CH1_Msk (0x2UL)
4819 #define GPDMA1_SGLREQDSTREG_CH2_Pos (2UL)
4820 #define GPDMA1_SGLREQDSTREG_CH2_Msk (0x4UL)
4821 #define GPDMA1_SGLREQDSTREG_CH3_Pos (3UL)
4822 #define GPDMA1_SGLREQDSTREG_CH3_Msk (0x8UL)
4823 #define GPDMA1_SGLREQDSTREG_WE_CH0_Pos (8UL)
4824 #define GPDMA1_SGLREQDSTREG_WE_CH0_Msk (0x100UL)
4825 #define GPDMA1_SGLREQDSTREG_WE_CH1_Pos (9UL)
4826 #define GPDMA1_SGLREQDSTREG_WE_CH1_Msk (0x200UL)
4827 #define GPDMA1_SGLREQDSTREG_WE_CH2_Pos (10UL)
4828 #define GPDMA1_SGLREQDSTREG_WE_CH2_Msk (0x400UL)
4829 #define GPDMA1_SGLREQDSTREG_WE_CH3_Pos (11UL)
4830 #define GPDMA1_SGLREQDSTREG_WE_CH3_Msk (0x800UL)
4832 /* ------------------------------ GPDMA1_LSTSRCREG ------------------------------ */
4833 #define GPDMA1_LSTSRCREG_CH0_Pos (0UL)
4834 #define GPDMA1_LSTSRCREG_CH0_Msk (0x1UL)
4835 #define GPDMA1_LSTSRCREG_CH1_Pos (1UL)
4836 #define GPDMA1_LSTSRCREG_CH1_Msk (0x2UL)
4837 #define GPDMA1_LSTSRCREG_CH2_Pos (2UL)
4838 #define GPDMA1_LSTSRCREG_CH2_Msk (0x4UL)
4839 #define GPDMA1_LSTSRCREG_CH3_Pos (3UL)
4840 #define GPDMA1_LSTSRCREG_CH3_Msk (0x8UL)
4841 #define GPDMA1_LSTSRCREG_WE_CH0_Pos (8UL)
4842 #define GPDMA1_LSTSRCREG_WE_CH0_Msk (0x100UL)
4843 #define GPDMA1_LSTSRCREG_WE_CH1_Pos (9UL)
4844 #define GPDMA1_LSTSRCREG_WE_CH1_Msk (0x200UL)
4845 #define GPDMA1_LSTSRCREG_WE_CH2_Pos (10UL)
4846 #define GPDMA1_LSTSRCREG_WE_CH2_Msk (0x400UL)
4847 #define GPDMA1_LSTSRCREG_WE_CH3_Pos (11UL)
4848 #define GPDMA1_LSTSRCREG_WE_CH3_Msk (0x800UL)
4850 /* ------------------------------ GPDMA1_LSTDSTREG ------------------------------ */
4851 #define GPDMA1_LSTDSTREG_CH0_Pos (0UL)
4852 #define GPDMA1_LSTDSTREG_CH0_Msk (0x1UL)
4853 #define GPDMA1_LSTDSTREG_CH1_Pos (1UL)
4854 #define GPDMA1_LSTDSTREG_CH1_Msk (0x2UL)
4855 #define GPDMA1_LSTDSTREG_CH2_Pos (2UL)
4856 #define GPDMA1_LSTDSTREG_CH2_Msk (0x4UL)
4857 #define GPDMA1_LSTDSTREG_CH3_Pos (3UL)
4858 #define GPDMA1_LSTDSTREG_CH3_Msk (0x8UL)
4859 #define GPDMA1_LSTDSTREG_WE_CH0_Pos (8UL)
4860 #define GPDMA1_LSTDSTREG_WE_CH0_Msk (0x100UL)
4861 #define GPDMA1_LSTDSTREG_WE_CH1_Pos (9UL)
4862 #define GPDMA1_LSTDSTREG_WE_CH1_Msk (0x200UL)
4863 #define GPDMA1_LSTDSTREG_WE_CH2_Pos (10UL)
4864 #define GPDMA1_LSTDSTREG_WE_CH2_Msk (0x400UL)
4865 #define GPDMA1_LSTDSTREG_WE_CH3_Pos (11UL)
4866 #define GPDMA1_LSTDSTREG_WE_CH3_Msk (0x800UL)
4868 /* ------------------------------ GPDMA1_DMACFGREG ------------------------------ */
4869 #define GPDMA1_DMACFGREG_DMA_EN_Pos (0UL)
4870 #define GPDMA1_DMACFGREG_DMA_EN_Msk (0x1UL)
4872 /* ------------------------------- GPDMA1_CHENREG ------------------------------- */
4873 #define GPDMA1_CHENREG_CH_Pos (0UL)
4874 #define GPDMA1_CHENREG_CH_Msk (0xfUL)
4875 #define GPDMA1_CHENREG_WE_CH_Pos (8UL)
4876 #define GPDMA1_CHENREG_WE_CH_Msk (0xf00UL)
4878 /* ---------------------------------- GPDMA1_ID --------------------------------- */
4879 #define GPDMA1_ID_VALUE_Pos (0UL)
4880 #define GPDMA1_ID_VALUE_Msk (0xffffffffUL)
4882 /* --------------------------------- GPDMA1_TYPE -------------------------------- */
4883 #define GPDMA1_TYPE_VALUE_Pos (0UL)
4884 #define GPDMA1_TYPE_VALUE_Msk (0xffffffffUL)
4886 /* ------------------------------- GPDMA1_VERSION ------------------------------- */
4887 #define GPDMA1_VERSION_VALUE_Pos (0UL)
4888 #define GPDMA1_VERSION_VALUE_Msk (0xffffffffUL)
4891 /* ================================================================================ */
4892 /* ================ Group 'GPDMA1_CH' Position & Mask ================ */
4893 /* ================================================================================ */
4894 
4895 
4896 /* -------------------------------- GPDMA1_CH_SAR ------------------------------- */
4897 #define GPDMA1_CH_SAR_SAR_Pos (0UL)
4898 #define GPDMA1_CH_SAR_SAR_Msk (0xffffffffUL)
4900 /* -------------------------------- GPDMA1_CH_DAR ------------------------------- */
4901 #define GPDMA1_CH_DAR_DAR_Pos (0UL)
4902 #define GPDMA1_CH_DAR_DAR_Msk (0xffffffffUL)
4904 /* ------------------------------- GPDMA1_CH_CTLL ------------------------------- */
4905 #define GPDMA1_CH_CTLL_INT_EN_Pos (0UL)
4906 #define GPDMA1_CH_CTLL_INT_EN_Msk (0x1UL)
4907 #define GPDMA1_CH_CTLL_DST_TR_WIDTH_Pos (1UL)
4908 #define GPDMA1_CH_CTLL_DST_TR_WIDTH_Msk (0xeUL)
4909 #define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Pos (4UL)
4910 #define GPDMA1_CH_CTLL_SRC_TR_WIDTH_Msk (0x70UL)
4911 #define GPDMA1_CH_CTLL_DINC_Pos (7UL)
4912 #define GPDMA1_CH_CTLL_DINC_Msk (0x180UL)
4913 #define GPDMA1_CH_CTLL_SINC_Pos (9UL)
4914 #define GPDMA1_CH_CTLL_SINC_Msk (0x600UL)
4915 #define GPDMA1_CH_CTLL_DEST_MSIZE_Pos (11UL)
4916 #define GPDMA1_CH_CTLL_DEST_MSIZE_Msk (0x3800UL)
4917 #define GPDMA1_CH_CTLL_SRC_MSIZE_Pos (14UL)
4918 #define GPDMA1_CH_CTLL_SRC_MSIZE_Msk (0x1c000UL)
4919 #define GPDMA1_CH_CTLL_TT_FC_Pos (20UL)
4920 #define GPDMA1_CH_CTLL_TT_FC_Msk (0x700000UL)
4922 /* ------------------------------- GPDMA1_CH_CTLH ------------------------------- */
4923 #define GPDMA1_CH_CTLH_BLOCK_TS_Pos (0UL)
4924 #define GPDMA1_CH_CTLH_BLOCK_TS_Msk (0xfffUL)
4925 #define GPDMA1_CH_CTLH_DONE_Pos (12UL)
4926 #define GPDMA1_CH_CTLH_DONE_Msk (0x1000UL)
4928 /* ------------------------------- GPDMA1_CH_CFGL ------------------------------- */
4929 #define GPDMA1_CH_CFGL_CH_PRIOR_Pos (5UL)
4930 #define GPDMA1_CH_CFGL_CH_PRIOR_Msk (0xe0UL)
4931 #define GPDMA1_CH_CFGL_CH_SUSP_Pos (8UL)
4932 #define GPDMA1_CH_CFGL_CH_SUSP_Msk (0x100UL)
4933 #define GPDMA1_CH_CFGL_FIFO_EMPTY_Pos (9UL)
4934 #define GPDMA1_CH_CFGL_FIFO_EMPTY_Msk (0x200UL)
4935 #define GPDMA1_CH_CFGL_HS_SEL_DST_Pos (10UL)
4936 #define GPDMA1_CH_CFGL_HS_SEL_DST_Msk (0x400UL)
4937 #define GPDMA1_CH_CFGL_HS_SEL_SRC_Pos (11UL)
4938 #define GPDMA1_CH_CFGL_HS_SEL_SRC_Msk (0x800UL)
4939 #define GPDMA1_CH_CFGL_LOCK_CH_L_Pos (12UL)
4940 #define GPDMA1_CH_CFGL_LOCK_CH_L_Msk (0x3000UL)
4941 #define GPDMA1_CH_CFGL_LOCK_B_L_Pos (14UL)
4942 #define GPDMA1_CH_CFGL_LOCK_B_L_Msk (0xc000UL)
4943 #define GPDMA1_CH_CFGL_LOCK_CH_Pos (16UL)
4944 #define GPDMA1_CH_CFGL_LOCK_CH_Msk (0x10000UL)
4945 #define GPDMA1_CH_CFGL_LOCK_B_Pos (17UL)
4946 #define GPDMA1_CH_CFGL_LOCK_B_Msk (0x20000UL)
4947 #define GPDMA1_CH_CFGL_DST_HS_POL_Pos (18UL)
4948 #define GPDMA1_CH_CFGL_DST_HS_POL_Msk (0x40000UL)
4949 #define GPDMA1_CH_CFGL_SRC_HS_POL_Pos (19UL)
4950 #define GPDMA1_CH_CFGL_SRC_HS_POL_Msk (0x80000UL)
4951 #define GPDMA1_CH_CFGL_MAX_ABRST_Pos (20UL)
4952 #define GPDMA1_CH_CFGL_MAX_ABRST_Msk (0x3ff00000UL)
4954 /* ------------------------------- GPDMA1_CH_CFGH ------------------------------- */
4955 #define GPDMA1_CH_CFGH_FCMODE_Pos (0UL)
4956 #define GPDMA1_CH_CFGH_FCMODE_Msk (0x1UL)
4957 #define GPDMA1_CH_CFGH_FIFO_MODE_Pos (1UL)
4958 #define GPDMA1_CH_CFGH_FIFO_MODE_Msk (0x2UL)
4959 #define GPDMA1_CH_CFGH_PROTCTL_Pos (2UL)
4960 #define GPDMA1_CH_CFGH_PROTCTL_Msk (0x1cUL)
4961 #define GPDMA1_CH_CFGH_SRC_PER_Pos (7UL)
4962 #define GPDMA1_CH_CFGH_SRC_PER_Msk (0x780UL)
4963 #define GPDMA1_CH_CFGH_DEST_PER_Pos (11UL)
4964 #define GPDMA1_CH_CFGH_DEST_PER_Msk (0x7800UL)
4967 /* ================================================================================ */
4968 /* ================ struct 'FCE' Position & Mask ================ */
4969 /* ================================================================================ */
4970 
4971 
4972 /* ----------------------------------- FCE_CLC ---------------------------------- */
4973 #define FCE_CLC_DISR_Pos (0UL)
4974 #define FCE_CLC_DISR_Msk (0x1UL)
4975 #define FCE_CLC_DISS_Pos (1UL)
4976 #define FCE_CLC_DISS_Msk (0x2UL)
4978 /* ----------------------------------- FCE_ID ----------------------------------- */
4979 #define FCE_ID_MOD_REV_Pos (0UL)
4980 #define FCE_ID_MOD_REV_Msk (0xffUL)
4981 #define FCE_ID_MOD_TYPE_Pos (8UL)
4982 #define FCE_ID_MOD_TYPE_Msk (0xff00UL)
4983 #define FCE_ID_MOD_NUMBER_Pos (16UL)
4984 #define FCE_ID_MOD_NUMBER_Msk (0xffff0000UL)
4987 /* ================================================================================ */
4988 /* ================ Group 'FCE_KE' Position & Mask ================ */
4989 /* ================================================================================ */
4990 
4991 
4992 /* ---------------------------------- FCE_KE_IR --------------------------------- */
4993 #define FCE_KE_IR_IR_Pos (0UL)
4994 #define FCE_KE_IR_IR_Msk (0xffffffffUL)
4996 /* --------------------------------- FCE_KE_RES --------------------------------- */
4997 #define FCE_KE_RES_RES_Pos (0UL)
4998 #define FCE_KE_RES_RES_Msk (0xffffffffUL)
5000 /* --------------------------------- FCE_KE_CFG --------------------------------- */
5001 #define FCE_KE_CFG_CMI_Pos (0UL)
5002 #define FCE_KE_CFG_CMI_Msk (0x1UL)
5003 #define FCE_KE_CFG_CEI_Pos (1UL)
5004 #define FCE_KE_CFG_CEI_Msk (0x2UL)
5005 #define FCE_KE_CFG_LEI_Pos (2UL)
5006 #define FCE_KE_CFG_LEI_Msk (0x4UL)
5007 #define FCE_KE_CFG_BEI_Pos (3UL)
5008 #define FCE_KE_CFG_BEI_Msk (0x8UL)
5009 #define FCE_KE_CFG_CCE_Pos (4UL)
5010 #define FCE_KE_CFG_CCE_Msk (0x10UL)
5011 #define FCE_KE_CFG_ALR_Pos (5UL)
5012 #define FCE_KE_CFG_ALR_Msk (0x20UL)
5013 #define FCE_KE_CFG_REFIN_Pos (8UL)
5014 #define FCE_KE_CFG_REFIN_Msk (0x100UL)
5015 #define FCE_KE_CFG_REFOUT_Pos (9UL)
5016 #define FCE_KE_CFG_REFOUT_Msk (0x200UL)
5017 #define FCE_KE_CFG_XSEL_Pos (10UL)
5018 #define FCE_KE_CFG_XSEL_Msk (0x400UL)
5020 /* --------------------------------- FCE_KE_STS --------------------------------- */
5021 #define FCE_KE_STS_CMF_Pos (0UL)
5022 #define FCE_KE_STS_CMF_Msk (0x1UL)
5023 #define FCE_KE_STS_CEF_Pos (1UL)
5024 #define FCE_KE_STS_CEF_Msk (0x2UL)
5025 #define FCE_KE_STS_LEF_Pos (2UL)
5026 #define FCE_KE_STS_LEF_Msk (0x4UL)
5027 #define FCE_KE_STS_BEF_Pos (3UL)
5028 #define FCE_KE_STS_BEF_Msk (0x8UL)
5030 /* -------------------------------- FCE_KE_LENGTH ------------------------------- */
5031 #define FCE_KE_LENGTH_LENGTH_Pos (0UL)
5032 #define FCE_KE_LENGTH_LENGTH_Msk (0xffffUL)
5034 /* -------------------------------- FCE_KE_CHECK -------------------------------- */
5035 #define FCE_KE_CHECK_CHECK_Pos (0UL)
5036 #define FCE_KE_CHECK_CHECK_Msk (0xffffffffUL)
5038 /* --------------------------------- FCE_KE_CRC --------------------------------- */
5039 #define FCE_KE_CRC_CRC_Pos (0UL)
5040 #define FCE_KE_CRC_CRC_Msk (0xffffffffUL)
5042 /* --------------------------------- FCE_KE_CTR --------------------------------- */
5043 #define FCE_KE_CTR_FCM_Pos (0UL)
5044 #define FCE_KE_CTR_FCM_Msk (0x1UL)
5045 #define FCE_KE_CTR_FRM_CFG_Pos (1UL)
5046 #define FCE_KE_CTR_FRM_CFG_Msk (0x2UL)
5047 #define FCE_KE_CTR_FRM_CHECK_Pos (2UL)
5048 #define FCE_KE_CTR_FRM_CHECK_Msk (0x4UL)
5051 /* ================================================================================ */
5052 /* ================ Group 'PBA' Position & Mask ================ */
5053 /* ================================================================================ */
5054 
5055 
5056 /* ----------------------------------- PBA_STS ---------------------------------- */
5057 #define PBA_STS_WERR_Pos (0UL)
5058 #define PBA_STS_WERR_Msk (0x1UL)
5060 /* ---------------------------------- PBA_WADDR --------------------------------- */
5061 #define PBA_WADDR_WADDR_Pos (0UL)
5062 #define PBA_WADDR_WADDR_Msk (0xffffffffUL)
5065 /* ================================================================================ */
5066 /* ================ Group 'FLASH' Position & Mask ================ */
5067 /* ================================================================================ */
5068 
5069 
5070 /* ---------------------------------- FLASH_ID ---------------------------------- */
5071 #define FLASH_ID_MOD_REV_Pos (0UL)
5072 #define FLASH_ID_MOD_REV_Msk (0xffUL)
5073 #define FLASH_ID_MOD_TYPE_Pos (8UL)
5074 #define FLASH_ID_MOD_TYPE_Msk (0xff00UL)
5075 #define FLASH_ID_MOD_NUMBER_Pos (16UL)
5076 #define FLASH_ID_MOD_NUMBER_Msk (0xffff0000UL)
5078 /* ---------------------------------- FLASH_FSR --------------------------------- */
5079 #define FLASH_FSR_PBUSY_Pos (0UL)
5080 #define FLASH_FSR_PBUSY_Msk (0x1UL)
5081 #define FLASH_FSR_FABUSY_Pos (1UL)
5082 #define FLASH_FSR_FABUSY_Msk (0x2UL)
5083 #define FLASH_FSR_PROG_Pos (4UL)
5084 #define FLASH_FSR_PROG_Msk (0x10UL)
5085 #define FLASH_FSR_ERASE_Pos (5UL)
5086 #define FLASH_FSR_ERASE_Msk (0x20UL)
5087 #define FLASH_FSR_PFPAGE_Pos (6UL)
5088 #define FLASH_FSR_PFPAGE_Msk (0x40UL)
5089 #define FLASH_FSR_PFOPER_Pos (8UL)
5090 #define FLASH_FSR_PFOPER_Msk (0x100UL)
5091 #define FLASH_FSR_SQER_Pos (10UL)
5092 #define FLASH_FSR_SQER_Msk (0x400UL)
5093 #define FLASH_FSR_PROER_Pos (11UL)
5094 #define FLASH_FSR_PROER_Msk (0x800UL)
5095 #define FLASH_FSR_PFSBER_Pos (12UL)
5096 #define FLASH_FSR_PFSBER_Msk (0x1000UL)
5097 #define FLASH_FSR_PFDBER_Pos (14UL)
5098 #define FLASH_FSR_PFDBER_Msk (0x4000UL)
5099 #define FLASH_FSR_PROIN_Pos (16UL)
5100 #define FLASH_FSR_PROIN_Msk (0x10000UL)
5101 #define FLASH_FSR_RPROIN_Pos (18UL)
5102 #define FLASH_FSR_RPROIN_Msk (0x40000UL)
5103 #define FLASH_FSR_RPRODIS_Pos (19UL)
5104 #define FLASH_FSR_RPRODIS_Msk (0x80000UL)
5105 #define FLASH_FSR_WPROIN0_Pos (21UL)
5106 #define FLASH_FSR_WPROIN0_Msk (0x200000UL)
5107 #define FLASH_FSR_WPROIN1_Pos (22UL)
5108 #define FLASH_FSR_WPROIN1_Msk (0x400000UL)
5109 #define FLASH_FSR_WPROIN2_Pos (23UL)
5110 #define FLASH_FSR_WPROIN2_Msk (0x800000UL)
5111 #define FLASH_FSR_WPRODIS0_Pos (25UL)
5112 #define FLASH_FSR_WPRODIS0_Msk (0x2000000UL)
5113 #define FLASH_FSR_WPRODIS1_Pos (26UL)
5114 #define FLASH_FSR_WPRODIS1_Msk (0x4000000UL)
5115 #define FLASH_FSR_SLM_Pos (28UL)
5116 #define FLASH_FSR_SLM_Msk (0x10000000UL)
5117 #define FLASH_FSR_VER_Pos (31UL)
5118 #define FLASH_FSR_VER_Msk (0x80000000UL)
5120 /* --------------------------------- FLASH_FCON --------------------------------- */
5121 #define FLASH_FCON_WSPFLASH_Pos (0UL)
5122 #define FLASH_FCON_WSPFLASH_Msk (0xfUL)
5123 #define FLASH_FCON_WSECPF_Pos (4UL)
5124 #define FLASH_FCON_WSECPF_Msk (0x10UL)
5125 #define FLASH_FCON_IDLE_Pos (13UL)
5126 #define FLASH_FCON_IDLE_Msk (0x2000UL)
5127 #define FLASH_FCON_ESLDIS_Pos (14UL)
5128 #define FLASH_FCON_ESLDIS_Msk (0x4000UL)
5129 #define FLASH_FCON_SLEEP_Pos (15UL)
5130 #define FLASH_FCON_SLEEP_Msk (0x8000UL)
5131 #define FLASH_FCON_RPA_Pos (16UL)
5132 #define FLASH_FCON_RPA_Msk (0x10000UL)
5133 #define FLASH_FCON_DCF_Pos (17UL)
5134 #define FLASH_FCON_DCF_Msk (0x20000UL)
5135 #define FLASH_FCON_DDF_Pos (18UL)
5136 #define FLASH_FCON_DDF_Msk (0x40000UL)
5137 #define FLASH_FCON_VOPERM_Pos (24UL)
5138 #define FLASH_FCON_VOPERM_Msk (0x1000000UL)
5139 #define FLASH_FCON_SQERM_Pos (25UL)
5140 #define FLASH_FCON_SQERM_Msk (0x2000000UL)
5141 #define FLASH_FCON_PROERM_Pos (26UL)
5142 #define FLASH_FCON_PROERM_Msk (0x4000000UL)
5143 #define FLASH_FCON_PFSBERM_Pos (27UL)
5144 #define FLASH_FCON_PFSBERM_Msk (0x8000000UL)
5145 #define FLASH_FCON_PFDBERM_Pos (29UL)
5146 #define FLASH_FCON_PFDBERM_Msk (0x20000000UL)
5147 #define FLASH_FCON_EOBM_Pos (31UL)
5148 #define FLASH_FCON_EOBM_Msk (0x80000000UL)
5150 /* --------------------------------- FLASH_MARP --------------------------------- */
5151 #define FLASH_MARP_MARGIN_Pos (0UL)
5152 #define FLASH_MARP_MARGIN_Msk (0xfUL)
5153 #define FLASH_MARP_TRAPDIS_Pos (15UL)
5154 #define FLASH_MARP_TRAPDIS_Msk (0x8000UL)
5156 /* -------------------------------- FLASH_PROCON0 ------------------------------- */
5157 #define FLASH_PROCON0_S0L_Pos (0UL)
5158 #define FLASH_PROCON0_S0L_Msk (0x1UL)
5159 #define FLASH_PROCON0_S1L_Pos (1UL)
5160 #define FLASH_PROCON0_S1L_Msk (0x2UL)
5161 #define FLASH_PROCON0_S2L_Pos (2UL)
5162 #define FLASH_PROCON0_S2L_Msk (0x4UL)
5163 #define FLASH_PROCON0_S3L_Pos (3UL)
5164 #define FLASH_PROCON0_S3L_Msk (0x8UL)
5165 #define FLASH_PROCON0_S4L_Pos (4UL)
5166 #define FLASH_PROCON0_S4L_Msk (0x10UL)
5167 #define FLASH_PROCON0_S5L_Pos (5UL)
5168 #define FLASH_PROCON0_S5L_Msk (0x20UL)
5169 #define FLASH_PROCON0_S6L_Pos (6UL)
5170 #define FLASH_PROCON0_S6L_Msk (0x40UL)
5171 #define FLASH_PROCON0_S7L_Pos (7UL)
5172 #define FLASH_PROCON0_S7L_Msk (0x80UL)
5173 #define FLASH_PROCON0_S8L_Pos (8UL)
5174 #define FLASH_PROCON0_S8L_Msk (0x100UL)
5175 #define FLASH_PROCON0_S9L_Pos (9UL)
5176 #define FLASH_PROCON0_S9L_Msk (0x200UL)
5177 #define FLASH_PROCON0_S10_S11L_Pos (10UL)
5178 #define FLASH_PROCON0_S10_S11L_Msk (0x400UL)
5179 #define FLASH_PROCON0_S12_S13L_Pos (11UL)
5180 #define FLASH_PROCON0_S12_S13L_Msk (0x800UL)
5181 #define FLASH_PROCON0_S14_S15L_Pos (12UL)
5182 #define FLASH_PROCON0_S14_S15L_Msk (0x1000UL)
5183 #define FLASH_PROCON0_RPRO_Pos (15UL)
5184 #define FLASH_PROCON0_RPRO_Msk (0x8000UL)
5186 /* -------------------------------- FLASH_PROCON1 ------------------------------- */
5187 #define FLASH_PROCON1_S0L_Pos (0UL)
5188 #define FLASH_PROCON1_S0L_Msk (0x1UL)
5189 #define FLASH_PROCON1_S1L_Pos (1UL)
5190 #define FLASH_PROCON1_S1L_Msk (0x2UL)
5191 #define FLASH_PROCON1_S2L_Pos (2UL)
5192 #define FLASH_PROCON1_S2L_Msk (0x4UL)
5193 #define FLASH_PROCON1_S3L_Pos (3UL)
5194 #define FLASH_PROCON1_S3L_Msk (0x8UL)
5195 #define FLASH_PROCON1_S4L_Pos (4UL)
5196 #define FLASH_PROCON1_S4L_Msk (0x10UL)
5197 #define FLASH_PROCON1_S5L_Pos (5UL)
5198 #define FLASH_PROCON1_S5L_Msk (0x20UL)
5199 #define FLASH_PROCON1_S6L_Pos (6UL)
5200 #define FLASH_PROCON1_S6L_Msk (0x40UL)
5201 #define FLASH_PROCON1_S7L_Pos (7UL)
5202 #define FLASH_PROCON1_S7L_Msk (0x80UL)
5203 #define FLASH_PROCON1_S8L_Pos (8UL)
5204 #define FLASH_PROCON1_S8L_Msk (0x100UL)
5205 #define FLASH_PROCON1_S9L_Pos (9UL)
5206 #define FLASH_PROCON1_S9L_Msk (0x200UL)
5207 #define FLASH_PROCON1_S10_S11L_Pos (10UL)
5208 #define FLASH_PROCON1_S10_S11L_Msk (0x400UL)
5209 #define FLASH_PROCON1_S12_S13L_Pos (11UL)
5210 #define FLASH_PROCON1_S12_S13L_Msk (0x800UL)
5211 #define FLASH_PROCON1_S14_S15L_Pos (12UL)
5212 #define FLASH_PROCON1_S14_S15L_Msk (0x1000UL)
5213 #define FLASH_PROCON1_PSR_Pos (16UL)
5214 #define FLASH_PROCON1_PSR_Msk (0x10000UL)
5216 /* -------------------------------- FLASH_PROCON2 ------------------------------- */
5217 #define FLASH_PROCON2_S0ROM_Pos (0UL)
5218 #define FLASH_PROCON2_S0ROM_Msk (0x1UL)
5219 #define FLASH_PROCON2_S1ROM_Pos (1UL)
5220 #define FLASH_PROCON2_S1ROM_Msk (0x2UL)
5221 #define FLASH_PROCON2_S2ROM_Pos (2UL)
5222 #define FLASH_PROCON2_S2ROM_Msk (0x4UL)
5223 #define FLASH_PROCON2_S3ROM_Pos (3UL)
5224 #define FLASH_PROCON2_S3ROM_Msk (0x8UL)
5225 #define FLASH_PROCON2_S4ROM_Pos (4UL)
5226 #define FLASH_PROCON2_S4ROM_Msk (0x10UL)
5227 #define FLASH_PROCON2_S5ROM_Pos (5UL)
5228 #define FLASH_PROCON2_S5ROM_Msk (0x20UL)
5229 #define FLASH_PROCON2_S6ROM_Pos (6UL)
5230 #define FLASH_PROCON2_S6ROM_Msk (0x40UL)
5231 #define FLASH_PROCON2_S7ROM_Pos (7UL)
5232 #define FLASH_PROCON2_S7ROM_Msk (0x80UL)
5233 #define FLASH_PROCON2_S8ROM_Pos (8UL)
5234 #define FLASH_PROCON2_S8ROM_Msk (0x100UL)
5235 #define FLASH_PROCON2_S9ROM_Pos (9UL)
5236 #define FLASH_PROCON2_S9ROM_Msk (0x200UL)
5237 #define FLASH_PROCON2_S10_S11ROM_Pos (10UL)
5238 #define FLASH_PROCON2_S10_S11ROM_Msk (0x400UL)
5239 #define FLASH_PROCON2_S12_S13ROM_Pos (11UL)
5240 #define FLASH_PROCON2_S12_S13ROM_Msk (0x800UL)
5241 #define FLASH_PROCON2_S14_S15ROM_Pos (12UL)
5242 #define FLASH_PROCON2_S14_S15ROM_Msk (0x1000UL)
5245 /* ================================================================================ */
5246 /* ================ struct 'PREF' Position & Mask ================ */
5247 /* ================================================================================ */
5248 
5249 
5250 /* ---------------------------------- PREF_PCON --------------------------------- */
5251 #define PREF_PCON_IBYP_Pos (0UL)
5252 #define PREF_PCON_IBYP_Msk (0x1UL)
5253 #define PREF_PCON_IINV_Pos (1UL)
5254 #define PREF_PCON_IINV_Msk (0x2UL)
5255 #define PREF_PCON_DBYP_Pos (4UL)
5256 #define PREF_PCON_DBYP_Msk (0x10UL)
5259 /* ================================================================================ */
5260 /* ================ Group 'PMU' Position & Mask ================ */
5261 /* ================================================================================ */
5262 
5263 
5264 /* ----------------------------------- PMU_ID ----------------------------------- */
5265 #define PMU_ID_MOD_REV_Pos (0UL)
5266 #define PMU_ID_MOD_REV_Msk (0xffUL)
5267 #define PMU_ID_MOD_TYPE_Pos (8UL)
5268 #define PMU_ID_MOD_TYPE_Msk (0xff00UL)
5269 #define PMU_ID_MOD_NUMBER_Pos (16UL)
5270 #define PMU_ID_MOD_NUMBER_Msk (0xffff0000UL)
5273 /* ================================================================================ */
5274 /* ================ struct 'WDT' Position & Mask ================ */
5275 /* ================================================================================ */
5276 
5277 
5278 /* ----------------------------------- WDT_ID ----------------------------------- */
5279 #define WDT_ID_MOD_REV_Pos (0UL)
5280 #define WDT_ID_MOD_REV_Msk (0xffUL)
5281 #define WDT_ID_MOD_TYPE_Pos (8UL)
5282 #define WDT_ID_MOD_TYPE_Msk (0xff00UL)
5283 #define WDT_ID_MOD_NUMBER_Pos (16UL)
5284 #define WDT_ID_MOD_NUMBER_Msk (0xffff0000UL)
5286 /* ----------------------------------- WDT_CTR ---------------------------------- */
5287 #define WDT_CTR_ENB_Pos (0UL)
5288 #define WDT_CTR_ENB_Msk (0x1UL)
5289 #define WDT_CTR_PRE_Pos (1UL)
5290 #define WDT_CTR_PRE_Msk (0x2UL)
5291 #define WDT_CTR_DSP_Pos (4UL)
5292 #define WDT_CTR_DSP_Msk (0x10UL)
5293 #define WDT_CTR_SPW_Pos (8UL)
5294 #define WDT_CTR_SPW_Msk (0xff00UL)
5296 /* ----------------------------------- WDT_SRV ---------------------------------- */
5297 #define WDT_SRV_SRV_Pos (0UL)
5298 #define WDT_SRV_SRV_Msk (0xffffffffUL)
5300 /* ----------------------------------- WDT_TIM ---------------------------------- */
5301 #define WDT_TIM_TIM_Pos (0UL)
5302 #define WDT_TIM_TIM_Msk (0xffffffffUL)
5304 /* ----------------------------------- WDT_WLB ---------------------------------- */
5305 #define WDT_WLB_WLB_Pos (0UL)
5306 #define WDT_WLB_WLB_Msk (0xffffffffUL)
5308 /* ----------------------------------- WDT_WUB ---------------------------------- */
5309 #define WDT_WUB_WUB_Pos (0UL)
5310 #define WDT_WUB_WUB_Msk (0xffffffffUL)
5312 /* --------------------------------- WDT_WDTSTS --------------------------------- */
5313 #define WDT_WDTSTS_ALMS_Pos (0UL)
5314 #define WDT_WDTSTS_ALMS_Msk (0x1UL)
5316 /* --------------------------------- WDT_WDTCLR --------------------------------- */
5317 #define WDT_WDTCLR_ALMC_Pos (0UL)
5318 #define WDT_WDTCLR_ALMC_Msk (0x1UL)
5321 /* ================================================================================ */
5322 /* ================ struct 'RTC' Position & Mask ================ */
5323 /* ================================================================================ */
5324 
5325 
5326 /* ----------------------------------- RTC_ID ----------------------------------- */
5327 #define RTC_ID_MOD_REV_Pos (0UL)
5328 #define RTC_ID_MOD_REV_Msk (0xffUL)
5329 #define RTC_ID_MOD_TYPE_Pos (8UL)
5330 #define RTC_ID_MOD_TYPE_Msk (0xff00UL)
5331 #define RTC_ID_MOD_NUMBER_Pos (16UL)
5332 #define RTC_ID_MOD_NUMBER_Msk (0xffff0000UL)
5334 /* ----------------------------------- RTC_CTR ---------------------------------- */
5335 #define RTC_CTR_ENB_Pos (0UL)
5336 #define RTC_CTR_ENB_Msk (0x1UL)
5337 #define RTC_CTR_TAE_Pos (2UL)
5338 #define RTC_CTR_TAE_Msk (0x4UL)
5339 #define RTC_CTR_ESEC_Pos (8UL)
5340 #define RTC_CTR_ESEC_Msk (0x100UL)
5341 #define RTC_CTR_EMIC_Pos (9UL)
5342 #define RTC_CTR_EMIC_Msk (0x200UL)
5343 #define RTC_CTR_EHOC_Pos (10UL)
5344 #define RTC_CTR_EHOC_Msk (0x400UL)
5345 #define RTC_CTR_EDAC_Pos (11UL)
5346 #define RTC_CTR_EDAC_Msk (0x800UL)
5347 #define RTC_CTR_EMOC_Pos (13UL)
5348 #define RTC_CTR_EMOC_Msk (0x2000UL)
5349 #define RTC_CTR_EYEC_Pos (14UL)
5350 #define RTC_CTR_EYEC_Msk (0x4000UL)
5351 #define RTC_CTR_DIV_Pos (16UL)
5352 #define RTC_CTR_DIV_Msk (0xffff0000UL)
5354 /* --------------------------------- RTC_RAWSTAT -------------------------------- */
5355 #define RTC_RAWSTAT_RPSE_Pos (0UL)
5356 #define RTC_RAWSTAT_RPSE_Msk (0x1UL)
5357 #define RTC_RAWSTAT_RPMI_Pos (1UL)
5358 #define RTC_RAWSTAT_RPMI_Msk (0x2UL)
5359 #define RTC_RAWSTAT_RPHO_Pos (2UL)
5360 #define RTC_RAWSTAT_RPHO_Msk (0x4UL)
5361 #define RTC_RAWSTAT_RPDA_Pos (3UL)
5362 #define RTC_RAWSTAT_RPDA_Msk (0x8UL)
5363 #define RTC_RAWSTAT_RPMO_Pos (5UL)
5364 #define RTC_RAWSTAT_RPMO_Msk (0x20UL)
5365 #define RTC_RAWSTAT_RPYE_Pos (6UL)
5366 #define RTC_RAWSTAT_RPYE_Msk (0x40UL)
5367 #define RTC_RAWSTAT_RAI_Pos (8UL)
5368 #define RTC_RAWSTAT_RAI_Msk (0x100UL)
5370 /* ---------------------------------- RTC_STSSR --------------------------------- */
5371 #define RTC_STSSR_SPSE_Pos (0UL)
5372 #define RTC_STSSR_SPSE_Msk (0x1UL)
5373 #define RTC_STSSR_SPMI_Pos (1UL)
5374 #define RTC_STSSR_SPMI_Msk (0x2UL)
5375 #define RTC_STSSR_SPHO_Pos (2UL)
5376 #define RTC_STSSR_SPHO_Msk (0x4UL)
5377 #define RTC_STSSR_SPDA_Pos (3UL)
5378 #define RTC_STSSR_SPDA_Msk (0x8UL)
5379 #define RTC_STSSR_SPMO_Pos (5UL)
5380 #define RTC_STSSR_SPMO_Msk (0x20UL)
5381 #define RTC_STSSR_SPYE_Pos (6UL)
5382 #define RTC_STSSR_SPYE_Msk (0x40UL)
5383 #define RTC_STSSR_SAI_Pos (8UL)
5384 #define RTC_STSSR_SAI_Msk (0x100UL)
5386 /* ---------------------------------- RTC_MSKSR --------------------------------- */
5387 #define RTC_MSKSR_MPSE_Pos (0UL)
5388 #define RTC_MSKSR_MPSE_Msk (0x1UL)
5389 #define RTC_MSKSR_MPMI_Pos (1UL)
5390 #define RTC_MSKSR_MPMI_Msk (0x2UL)
5391 #define RTC_MSKSR_MPHO_Pos (2UL)
5392 #define RTC_MSKSR_MPHO_Msk (0x4UL)
5393 #define RTC_MSKSR_MPDA_Pos (3UL)
5394 #define RTC_MSKSR_MPDA_Msk (0x8UL)
5395 #define RTC_MSKSR_MPMO_Pos (5UL)
5396 #define RTC_MSKSR_MPMO_Msk (0x20UL)
5397 #define RTC_MSKSR_MPYE_Pos (6UL)
5398 #define RTC_MSKSR_MPYE_Msk (0x40UL)
5399 #define RTC_MSKSR_MAI_Pos (8UL)
5400 #define RTC_MSKSR_MAI_Msk (0x100UL)
5402 /* ---------------------------------- RTC_CLRSR --------------------------------- */
5403 #define RTC_CLRSR_RPSE_Pos (0UL)
5404 #define RTC_CLRSR_RPSE_Msk (0x1UL)
5405 #define RTC_CLRSR_RPMI_Pos (1UL)
5406 #define RTC_CLRSR_RPMI_Msk (0x2UL)
5407 #define RTC_CLRSR_RPHO_Pos (2UL)
5408 #define RTC_CLRSR_RPHO_Msk (0x4UL)
5409 #define RTC_CLRSR_RPDA_Pos (3UL)
5410 #define RTC_CLRSR_RPDA_Msk (0x8UL)
5411 #define RTC_CLRSR_RPMO_Pos (5UL)
5412 #define RTC_CLRSR_RPMO_Msk (0x20UL)
5413 #define RTC_CLRSR_RPYE_Pos (6UL)
5414 #define RTC_CLRSR_RPYE_Msk (0x40UL)
5415 #define RTC_CLRSR_RAI_Pos (8UL)
5416 #define RTC_CLRSR_RAI_Msk (0x100UL)
5418 /* ---------------------------------- RTC_ATIM0 --------------------------------- */
5419 #define RTC_ATIM0_ASE_Pos (0UL)
5420 #define RTC_ATIM0_ASE_Msk (0x3fUL)
5421 #define RTC_ATIM0_AMI_Pos (8UL)
5422 #define RTC_ATIM0_AMI_Msk (0x3f00UL)
5423 #define RTC_ATIM0_AHO_Pos (16UL)
5424 #define RTC_ATIM0_AHO_Msk (0x1f0000UL)
5425 #define RTC_ATIM0_ADA_Pos (24UL)
5426 #define RTC_ATIM0_ADA_Msk (0x1f000000UL)
5428 /* ---------------------------------- RTC_ATIM1 --------------------------------- */
5429 #define RTC_ATIM1_AMO_Pos (8UL)
5430 #define RTC_ATIM1_AMO_Msk (0xf00UL)
5431 #define RTC_ATIM1_AYE_Pos (16UL)
5432 #define RTC_ATIM1_AYE_Msk (0xffff0000UL)
5434 /* ---------------------------------- RTC_TIM0 ---------------------------------- */
5435 #define RTC_TIM0_SE_Pos (0UL)
5436 #define RTC_TIM0_SE_Msk (0x3fUL)
5437 #define RTC_TIM0_MI_Pos (8UL)
5438 #define RTC_TIM0_MI_Msk (0x3f00UL)
5439 #define RTC_TIM0_HO_Pos (16UL)
5440 #define RTC_TIM0_HO_Msk (0x1f0000UL)
5441 #define RTC_TIM0_DA_Pos (24UL)
5442 #define RTC_TIM0_DA_Msk (0x1f000000UL)
5444 /* ---------------------------------- RTC_TIM1 ---------------------------------- */
5445 #define RTC_TIM1_DAWE_Pos (0UL)
5446 #define RTC_TIM1_DAWE_Msk (0x7UL)
5447 #define RTC_TIM1_MO_Pos (8UL)
5448 #define RTC_TIM1_MO_Msk (0xf00UL)
5449 #define RTC_TIM1_YE_Pos (16UL)
5450 #define RTC_TIM1_YE_Msk (0xffff0000UL)
5453 /* ================================================================================ */
5454 /* ================ struct 'SCU_CLK' Position & Mask ================ */
5455 /* ================================================================================ */
5456 
5457 
5458 /* ------------------------------- SCU_CLK_CLKSTAT ------------------------------ */
5459 #define SCU_CLK_CLKSTAT_USBCST_Pos (0UL)
5460 #define SCU_CLK_CLKSTAT_USBCST_Msk (0x1UL)
5461 #define SCU_CLK_CLKSTAT_MMCCST_Pos (1UL)
5462 #define SCU_CLK_CLKSTAT_MMCCST_Msk (0x2UL)
5463 #define SCU_CLK_CLKSTAT_ETH0CST_Pos (2UL)
5464 #define SCU_CLK_CLKSTAT_ETH0CST_Msk (0x4UL)
5465 #define SCU_CLK_CLKSTAT_EBUCST_Pos (3UL)
5466 #define SCU_CLK_CLKSTAT_EBUCST_Msk (0x8UL)
5467 #define SCU_CLK_CLKSTAT_CCUCST_Pos (4UL)
5468 #define SCU_CLK_CLKSTAT_CCUCST_Msk (0x10UL)
5469 #define SCU_CLK_CLKSTAT_WDTCST_Pos (5UL)
5470 #define SCU_CLK_CLKSTAT_WDTCST_Msk (0x20UL)
5472 /* ------------------------------- SCU_CLK_CLKSET ------------------------------- */
5473 #define SCU_CLK_CLKSET_USBCEN_Pos (0UL)
5474 #define SCU_CLK_CLKSET_USBCEN_Msk (0x1UL)
5475 #define SCU_CLK_CLKSET_MMCCEN_Pos (1UL)
5476 #define SCU_CLK_CLKSET_MMCCEN_Msk (0x2UL)
5477 #define SCU_CLK_CLKSET_ETH0CEN_Pos (2UL)
5478 #define SCU_CLK_CLKSET_ETH0CEN_Msk (0x4UL)
5479 #define SCU_CLK_CLKSET_EBUCEN_Pos (3UL)
5480 #define SCU_CLK_CLKSET_EBUCEN_Msk (0x8UL)
5481 #define SCU_CLK_CLKSET_CCUCEN_Pos (4UL)
5482 #define SCU_CLK_CLKSET_CCUCEN_Msk (0x10UL)
5483 #define SCU_CLK_CLKSET_WDTCEN_Pos (5UL)
5484 #define SCU_CLK_CLKSET_WDTCEN_Msk (0x20UL)
5486 /* ------------------------------- SCU_CLK_CLKCLR ------------------------------- */
5487 #define SCU_CLK_CLKCLR_USBCDI_Pos (0UL)
5488 #define SCU_CLK_CLKCLR_USBCDI_Msk (0x1UL)
5489 #define SCU_CLK_CLKCLR_MMCCDI_Pos (1UL)
5490 #define SCU_CLK_CLKCLR_MMCCDI_Msk (0x2UL)
5491 #define SCU_CLK_CLKCLR_ETH0CDI_Pos (2UL)
5492 #define SCU_CLK_CLKCLR_ETH0CDI_Msk (0x4UL)
5493 #define SCU_CLK_CLKCLR_EBUCDI_Pos (3UL)
5494 #define SCU_CLK_CLKCLR_EBUCDI_Msk (0x8UL)
5495 #define SCU_CLK_CLKCLR_CCUCDI_Pos (4UL)
5496 #define SCU_CLK_CLKCLR_CCUCDI_Msk (0x10UL)
5497 #define SCU_CLK_CLKCLR_WDTCDI_Pos (5UL)
5498 #define SCU_CLK_CLKCLR_WDTCDI_Msk (0x20UL)
5500 /* ------------------------------ SCU_CLK_SYSCLKCR ------------------------------ */
5501 #define SCU_CLK_SYSCLKCR_SYSDIV_Pos (0UL)
5502 #define SCU_CLK_SYSCLKCR_SYSDIV_Msk (0xffUL)
5503 #define SCU_CLK_SYSCLKCR_SYSSEL_Pos (16UL)
5504 #define SCU_CLK_SYSCLKCR_SYSSEL_Msk (0x10000UL)
5506 /* ------------------------------ SCU_CLK_CPUCLKCR ------------------------------ */
5507 #define SCU_CLK_CPUCLKCR_CPUDIV_Pos (0UL)
5508 #define SCU_CLK_CPUCLKCR_CPUDIV_Msk (0x1UL)
5510 /* ------------------------------- SCU_CLK_PBCLKCR ------------------------------ */
5511 #define SCU_CLK_PBCLKCR_PBDIV_Pos (0UL)
5512 #define SCU_CLK_PBCLKCR_PBDIV_Msk (0x1UL)
5514 /* ------------------------------ SCU_CLK_USBCLKCR ------------------------------ */
5515 #define SCU_CLK_USBCLKCR_USBDIV_Pos (0UL)
5516 #define SCU_CLK_USBCLKCR_USBDIV_Msk (0x7UL)
5517 #define SCU_CLK_USBCLKCR_USBSEL_Pos (16UL)
5518 #define SCU_CLK_USBCLKCR_USBSEL_Msk (0x10000UL)
5520 /* ------------------------------ SCU_CLK_EBUCLKCR ------------------------------ */
5521 #define SCU_CLK_EBUCLKCR_EBUDIV_Pos (0UL)
5522 #define SCU_CLK_EBUCLKCR_EBUDIV_Msk (0x3fUL)
5524 /* ------------------------------ SCU_CLK_CCUCLKCR ------------------------------ */
5525 #define SCU_CLK_CCUCLKCR_CCUDIV_Pos (0UL)
5526 #define SCU_CLK_CCUCLKCR_CCUDIV_Msk (0x1UL)
5528 /* ------------------------------ SCU_CLK_WDTCLKCR ------------------------------ */
5529 #define SCU_CLK_WDTCLKCR_WDTDIV_Pos (0UL)
5530 #define SCU_CLK_WDTCLKCR_WDTDIV_Msk (0xffUL)
5531 #define SCU_CLK_WDTCLKCR_WDTSEL_Pos (16UL)
5532 #define SCU_CLK_WDTCLKCR_WDTSEL_Msk (0x30000UL)
5534 /* ------------------------------ SCU_CLK_EXTCLKCR ------------------------------ */
5535 #define SCU_CLK_EXTCLKCR_ECKSEL_Pos (0UL)
5536 #define SCU_CLK_EXTCLKCR_ECKSEL_Msk (0x3UL)
5537 #define SCU_CLK_EXTCLKCR_ECKDIV_Pos (16UL)
5538 #define SCU_CLK_EXTCLKCR_ECKDIV_Msk (0x1ff0000UL)
5540 /* ----------------------------- SCU_CLK_MLINKCLKCR ----------------------------- */
5541 #define SCU_CLK_MLINKCLKCR_SYSDIV_Pos (0UL)
5542 #define SCU_CLK_MLINKCLKCR_SYSDIV_Msk (0xffUL)
5543 #define SCU_CLK_MLINKCLKCR_SYSSEL_Pos (8UL)
5544 #define SCU_CLK_MLINKCLKCR_SYSSEL_Msk (0x100UL)
5545 #define SCU_CLK_MLINKCLKCR_CPUDIV_Pos (10UL)
5546 #define SCU_CLK_MLINKCLKCR_CPUDIV_Msk (0x400UL)
5547 #define SCU_CLK_MLINKCLKCR_PBDIV_Pos (12UL)
5548 #define SCU_CLK_MLINKCLKCR_PBDIV_Msk (0x1000UL)
5549 #define SCU_CLK_MLINKCLKCR_CCUDIV_Pos (14UL)
5550 #define SCU_CLK_MLINKCLKCR_CCUDIV_Msk (0x4000UL)
5551 #define SCU_CLK_MLINKCLKCR_WDTDIV_Pos (16UL)
5552 #define SCU_CLK_MLINKCLKCR_WDTDIV_Msk (0xff0000UL)
5553 #define SCU_CLK_MLINKCLKCR_WDTSEL_Pos (24UL)
5554 #define SCU_CLK_MLINKCLKCR_WDTSEL_Msk (0x3000000UL)
5555 #define SCU_CLK_MLINKCLKCR_EBUDIV_Pos (26UL)
5556 #define SCU_CLK_MLINKCLKCR_EBUDIV_Msk (0xfc000000UL)
5558 /* ------------------------------- SCU_CLK_SLEEPCR ------------------------------ */
5559 #define SCU_CLK_SLEEPCR_SYSSEL_Pos (0UL)
5560 #define SCU_CLK_SLEEPCR_SYSSEL_Msk (0x1UL)
5561 #define SCU_CLK_SLEEPCR_USBCR_Pos (16UL)
5562 #define SCU_CLK_SLEEPCR_USBCR_Msk (0x10000UL)
5563 #define SCU_CLK_SLEEPCR_MMCCR_Pos (17UL)
5564 #define SCU_CLK_SLEEPCR_MMCCR_Msk (0x20000UL)
5565 #define SCU_CLK_SLEEPCR_ETH0CR_Pos (18UL)
5566 #define SCU_CLK_SLEEPCR_ETH0CR_Msk (0x40000UL)
5567 #define SCU_CLK_SLEEPCR_EBUCR_Pos (19UL)
5568 #define SCU_CLK_SLEEPCR_EBUCR_Msk (0x80000UL)
5569 #define SCU_CLK_SLEEPCR_CCUCR_Pos (20UL)
5570 #define SCU_CLK_SLEEPCR_CCUCR_Msk (0x100000UL)
5571 #define SCU_CLK_SLEEPCR_WDTCR_Pos (21UL)
5572 #define SCU_CLK_SLEEPCR_WDTCR_Msk (0x200000UL)
5574 /* ------------------------------ SCU_CLK_DSLEEPCR ------------------------------ */
5575 #define SCU_CLK_DSLEEPCR_SYSSEL_Pos (0UL)
5576 #define SCU_CLK_DSLEEPCR_SYSSEL_Msk (0x3UL)
5577 #define SCU_CLK_DSLEEPCR_FPDN_Pos (11UL)
5578 #define SCU_CLK_DSLEEPCR_FPDN_Msk (0x800UL)
5579 #define SCU_CLK_DSLEEPCR_PLLPDN_Pos (12UL)
5580 #define SCU_CLK_DSLEEPCR_PLLPDN_Msk (0x1000UL)
5581 #define SCU_CLK_DSLEEPCR_VCOPDN_Pos (13UL)
5582 #define SCU_CLK_DSLEEPCR_VCOPDN_Msk (0x2000UL)
5583 #define SCU_CLK_DSLEEPCR_USBCR_Pos (16UL)
5584 #define SCU_CLK_DSLEEPCR_USBCR_Msk (0x10000UL)
5585 #define SCU_CLK_DSLEEPCR_MMCCR_Pos (17UL)
5586 #define SCU_CLK_DSLEEPCR_MMCCR_Msk (0x20000UL)
5587 #define SCU_CLK_DSLEEPCR_ETH0CR_Pos (18UL)
5588 #define SCU_CLK_DSLEEPCR_ETH0CR_Msk (0x40000UL)
5589 #define SCU_CLK_DSLEEPCR_EBUCR_Pos (19UL)
5590 #define SCU_CLK_DSLEEPCR_EBUCR_Msk (0x80000UL)
5591 #define SCU_CLK_DSLEEPCR_CCUCR_Pos (20UL)
5592 #define SCU_CLK_DSLEEPCR_CCUCR_Msk (0x100000UL)
5593 #define SCU_CLK_DSLEEPCR_WDTCR_Pos (21UL)
5594 #define SCU_CLK_DSLEEPCR_WDTCR_Msk (0x200000UL)
5596 /* ------------------------------ SCU_CLK_ECATCLKCR ----------------------------- */
5597 #define SCU_CLK_ECATCLKCR_ECADIV_Pos (0UL)
5598 #define SCU_CLK_ECATCLKCR_ECADIV_Msk (0x3UL)
5599 #define SCU_CLK_ECATCLKCR_ECATSEL_Pos (16UL)
5600 #define SCU_CLK_ECATCLKCR_ECATSEL_Msk (0x10000UL)
5602 /* ------------------------------ SCU_CLK_CGATSTAT0 ----------------------------- */
5603 #define SCU_CLK_CGATSTAT0_VADC_Pos (0UL)
5604 #define SCU_CLK_CGATSTAT0_VADC_Msk (0x1UL)
5605 #define SCU_CLK_CGATSTAT0_DSD_Pos (1UL)
5606 #define SCU_CLK_CGATSTAT0_DSD_Msk (0x2UL)
5607 #define SCU_CLK_CGATSTAT0_CCU40_Pos (2UL)
5608 #define SCU_CLK_CGATSTAT0_CCU40_Msk (0x4UL)
5609 #define SCU_CLK_CGATSTAT0_CCU41_Pos (3UL)
5610 #define SCU_CLK_CGATSTAT0_CCU41_Msk (0x8UL)
5611 #define SCU_CLK_CGATSTAT0_CCU42_Pos (4UL)
5612 #define SCU_CLK_CGATSTAT0_CCU42_Msk (0x10UL)
5613 #define SCU_CLK_CGATSTAT0_CCU80_Pos (7UL)
5614 #define SCU_CLK_CGATSTAT0_CCU80_Msk (0x80UL)
5615 #define SCU_CLK_CGATSTAT0_CCU81_Pos (8UL)
5616 #define SCU_CLK_CGATSTAT0_CCU81_Msk (0x100UL)
5617 #define SCU_CLK_CGATSTAT0_POSIF0_Pos (9UL)
5618 #define SCU_CLK_CGATSTAT0_POSIF0_Msk (0x200UL)
5619 #define SCU_CLK_CGATSTAT0_POSIF1_Pos (10UL)
5620 #define SCU_CLK_CGATSTAT0_POSIF1_Msk (0x400UL)
5621 #define SCU_CLK_CGATSTAT0_USIC0_Pos (11UL)
5622 #define SCU_CLK_CGATSTAT0_USIC0_Msk (0x800UL)
5623 #define SCU_CLK_CGATSTAT0_ERU1_Pos (16UL)
5624 #define SCU_CLK_CGATSTAT0_ERU1_Msk (0x10000UL)
5626 /* ------------------------------ SCU_CLK_CGATSET0 ------------------------------ */
5627 #define SCU_CLK_CGATSET0_VADC_Pos (0UL)
5628 #define SCU_CLK_CGATSET0_VADC_Msk (0x1UL)
5629 #define SCU_CLK_CGATSET0_DSD_Pos (1UL)
5630 #define SCU_CLK_CGATSET0_DSD_Msk (0x2UL)
5631 #define SCU_CLK_CGATSET0_CCU40_Pos (2UL)
5632 #define SCU_CLK_CGATSET0_CCU40_Msk (0x4UL)
5633 #define SCU_CLK_CGATSET0_CCU41_Pos (3UL)
5634 #define SCU_CLK_CGATSET0_CCU41_Msk (0x8UL)
5635 #define SCU_CLK_CGATSET0_CCU42_Pos (4UL)
5636 #define SCU_CLK_CGATSET0_CCU42_Msk (0x10UL)
5637 #define SCU_CLK_CGATSET0_CCU80_Pos (7UL)
5638 #define SCU_CLK_CGATSET0_CCU80_Msk (0x80UL)
5639 #define SCU_CLK_CGATSET0_CCU81_Pos (8UL)
5640 #define SCU_CLK_CGATSET0_CCU81_Msk (0x100UL)
5641 #define SCU_CLK_CGATSET0_POSIF0_Pos (9UL)
5642 #define SCU_CLK_CGATSET0_POSIF0_Msk (0x200UL)
5643 #define SCU_CLK_CGATSET0_POSIF1_Pos (10UL)
5644 #define SCU_CLK_CGATSET0_POSIF1_Msk (0x400UL)
5645 #define SCU_CLK_CGATSET0_USIC0_Pos (11UL)
5646 #define SCU_CLK_CGATSET0_USIC0_Msk (0x800UL)
5647 #define SCU_CLK_CGATSET0_ERU1_Pos (16UL)
5648 #define SCU_CLK_CGATSET0_ERU1_Msk (0x10000UL)
5650 /* ------------------------------ SCU_CLK_CGATCLR0 ------------------------------ */
5651 #define SCU_CLK_CGATCLR0_VADC_Pos (0UL)
5652 #define SCU_CLK_CGATCLR0_VADC_Msk (0x1UL)
5653 #define SCU_CLK_CGATCLR0_DSD_Pos (1UL)
5654 #define SCU_CLK_CGATCLR0_DSD_Msk (0x2UL)
5655 #define SCU_CLK_CGATCLR0_CCU40_Pos (2UL)
5656 #define SCU_CLK_CGATCLR0_CCU40_Msk (0x4UL)
5657 #define SCU_CLK_CGATCLR0_CCU41_Pos (3UL)
5658 #define SCU_CLK_CGATCLR0_CCU41_Msk (0x8UL)
5659 #define SCU_CLK_CGATCLR0_CCU42_Pos (4UL)
5660 #define SCU_CLK_CGATCLR0_CCU42_Msk (0x10UL)
5661 #define SCU_CLK_CGATCLR0_CCU80_Pos (7UL)
5662 #define SCU_CLK_CGATCLR0_CCU80_Msk (0x80UL)
5663 #define SCU_CLK_CGATCLR0_CCU81_Pos (8UL)
5664 #define SCU_CLK_CGATCLR0_CCU81_Msk (0x100UL)
5665 #define SCU_CLK_CGATCLR0_POSIF0_Pos (9UL)
5666 #define SCU_CLK_CGATCLR0_POSIF0_Msk (0x200UL)
5667 #define SCU_CLK_CGATCLR0_POSIF1_Pos (10UL)
5668 #define SCU_CLK_CGATCLR0_POSIF1_Msk (0x400UL)
5669 #define SCU_CLK_CGATCLR0_USIC0_Pos (11UL)
5670 #define SCU_CLK_CGATCLR0_USIC0_Msk (0x800UL)
5671 #define SCU_CLK_CGATCLR0_ERU1_Pos (16UL)
5672 #define SCU_CLK_CGATCLR0_ERU1_Msk (0x10000UL)
5674 /* ------------------------------ SCU_CLK_CGATSTAT1 ----------------------------- */
5675 #define SCU_CLK_CGATSTAT1_CCU43_Pos (0UL)
5676 #define SCU_CLK_CGATSTAT1_CCU43_Msk (0x1UL)
5677 #define SCU_CLK_CGATSTAT1_LEDTSCU0_Pos (3UL)
5678 #define SCU_CLK_CGATSTAT1_LEDTSCU0_Msk (0x8UL)
5679 #define SCU_CLK_CGATSTAT1_MCAN0_Pos (4UL)
5680 #define SCU_CLK_CGATSTAT1_MCAN0_Msk (0x10UL)
5681 #define SCU_CLK_CGATSTAT1_DAC_Pos (5UL)
5682 #define SCU_CLK_CGATSTAT1_DAC_Msk (0x20UL)
5683 #define SCU_CLK_CGATSTAT1_MMCI_Pos (6UL)
5684 #define SCU_CLK_CGATSTAT1_MMCI_Msk (0x40UL)
5685 #define SCU_CLK_CGATSTAT1_USIC1_Pos (7UL)
5686 #define SCU_CLK_CGATSTAT1_USIC1_Msk (0x80UL)
5687 #define SCU_CLK_CGATSTAT1_USIC2_Pos (8UL)
5688 #define SCU_CLK_CGATSTAT1_USIC2_Msk (0x100UL)
5689 #define SCU_CLK_CGATSTAT1_PPORTS_Pos (9UL)
5690 #define SCU_CLK_CGATSTAT1_PPORTS_Msk (0x200UL)
5692 /* ------------------------------ SCU_CLK_CGATSET1 ------------------------------ */
5693 #define SCU_CLK_CGATSET1_CCU43_Pos (0UL)
5694 #define SCU_CLK_CGATSET1_CCU43_Msk (0x1UL)
5695 #define SCU_CLK_CGATSET1_LEDTSCU0_Pos (3UL)
5696 #define SCU_CLK_CGATSET1_LEDTSCU0_Msk (0x8UL)
5697 #define SCU_CLK_CGATSET1_MCAN0_Pos (4UL)
5698 #define SCU_CLK_CGATSET1_MCAN0_Msk (0x10UL)
5699 #define SCU_CLK_CGATSET1_DAC_Pos (5UL)
5700 #define SCU_CLK_CGATSET1_DAC_Msk (0x20UL)
5701 #define SCU_CLK_CGATSET1_MMCI_Pos (6UL)
5702 #define SCU_CLK_CGATSET1_MMCI_Msk (0x40UL)
5703 #define SCU_CLK_CGATSET1_USIC1_Pos (7UL)
5704 #define SCU_CLK_CGATSET1_USIC1_Msk (0x80UL)
5705 #define SCU_CLK_CGATSET1_USIC2_Pos (8UL)
5706 #define SCU_CLK_CGATSET1_USIC2_Msk (0x100UL)
5707 #define SCU_CLK_CGATSET1_PPORTS_Pos (9UL)
5708 #define SCU_CLK_CGATSET1_PPORTS_Msk (0x200UL)
5710 /* ------------------------------ SCU_CLK_CGATCLR1 ------------------------------ */
5711 #define SCU_CLK_CGATCLR1_CCU43_Pos (0UL)
5712 #define SCU_CLK_CGATCLR1_CCU43_Msk (0x1UL)
5713 #define SCU_CLK_CGATCLR1_LEDTSCU0_Pos (3UL)
5714 #define SCU_CLK_CGATCLR1_LEDTSCU0_Msk (0x8UL)
5715 #define SCU_CLK_CGATCLR1_MCAN0_Pos (4UL)
5716 #define SCU_CLK_CGATCLR1_MCAN0_Msk (0x10UL)
5717 #define SCU_CLK_CGATCLR1_DAC_Pos (5UL)
5718 #define SCU_CLK_CGATCLR1_DAC_Msk (0x20UL)
5719 #define SCU_CLK_CGATCLR1_MMCI_Pos (6UL)
5720 #define SCU_CLK_CGATCLR1_MMCI_Msk (0x40UL)
5721 #define SCU_CLK_CGATCLR1_USIC1_Pos (7UL)
5722 #define SCU_CLK_CGATCLR1_USIC1_Msk (0x80UL)
5723 #define SCU_CLK_CGATCLR1_USIC2_Pos (8UL)
5724 #define SCU_CLK_CGATCLR1_USIC2_Msk (0x100UL)
5725 #define SCU_CLK_CGATCLR1_PPORTS_Pos (9UL)
5726 #define SCU_CLK_CGATCLR1_PPORTS_Msk (0x200UL)
5728 /* ------------------------------ SCU_CLK_CGATSTAT2 ----------------------------- */
5729 #define SCU_CLK_CGATSTAT2_WDT_Pos (1UL)
5730 #define SCU_CLK_CGATSTAT2_WDT_Msk (0x2UL)
5731 #define SCU_CLK_CGATSTAT2_ETH0_Pos (2UL)
5732 #define SCU_CLK_CGATSTAT2_ETH0_Msk (0x4UL)
5733 #define SCU_CLK_CGATSTAT2_DMA0_Pos (4UL)
5734 #define SCU_CLK_CGATSTAT2_DMA0_Msk (0x10UL)
5735 #define SCU_CLK_CGATSTAT2_DMA1_Pos (5UL)
5736 #define SCU_CLK_CGATSTAT2_DMA1_Msk (0x20UL)
5737 #define SCU_CLK_CGATSTAT2_FCE_Pos (6UL)
5738 #define SCU_CLK_CGATSTAT2_FCE_Msk (0x40UL)
5739 #define SCU_CLK_CGATSTAT2_USB_Pos (7UL)
5740 #define SCU_CLK_CGATSTAT2_USB_Msk (0x80UL)
5741 #define SCU_CLK_CGATSTAT2_ECAT0_Pos (10UL)
5742 #define SCU_CLK_CGATSTAT2_ECAT0_Msk (0x400UL)
5744 /* ------------------------------ SCU_CLK_CGATSET2 ------------------------------ */
5745 #define SCU_CLK_CGATSET2_WDT_Pos (1UL)
5746 #define SCU_CLK_CGATSET2_WDT_Msk (0x2UL)
5747 #define SCU_CLK_CGATSET2_ETH0_Pos (2UL)
5748 #define SCU_CLK_CGATSET2_ETH0_Msk (0x4UL)
5749 #define SCU_CLK_CGATSET2_DMA0_Pos (4UL)
5750 #define SCU_CLK_CGATSET2_DMA0_Msk (0x10UL)
5751 #define SCU_CLK_CGATSET2_DMA1_Pos (5UL)
5752 #define SCU_CLK_CGATSET2_DMA1_Msk (0x20UL)
5753 #define SCU_CLK_CGATSET2_FCE_Pos (6UL)
5754 #define SCU_CLK_CGATSET2_FCE_Msk (0x40UL)
5755 #define SCU_CLK_CGATSET2_USB_Pos (7UL)
5756 #define SCU_CLK_CGATSET2_USB_Msk (0x80UL)
5757 #define SCU_CLK_CGATSET2_ECAT0_Pos (10UL)
5758 #define SCU_CLK_CGATSET2_ECAT0_Msk (0x400UL)
5760 /* ------------------------------ SCU_CLK_CGATCLR2 ------------------------------ */
5761 #define SCU_CLK_CGATCLR2_WDT_Pos (1UL)
5762 #define SCU_CLK_CGATCLR2_WDT_Msk (0x2UL)
5763 #define SCU_CLK_CGATCLR2_ETH0_Pos (2UL)
5764 #define SCU_CLK_CGATCLR2_ETH0_Msk (0x4UL)
5765 #define SCU_CLK_CGATCLR2_DMA0_Pos (4UL)
5766 #define SCU_CLK_CGATCLR2_DMA0_Msk (0x10UL)
5767 #define SCU_CLK_CGATCLR2_DMA1_Pos (5UL)
5768 #define SCU_CLK_CGATCLR2_DMA1_Msk (0x20UL)
5769 #define SCU_CLK_CGATCLR2_FCE_Pos (6UL)
5770 #define SCU_CLK_CGATCLR2_FCE_Msk (0x40UL)
5771 #define SCU_CLK_CGATCLR2_USB_Pos (7UL)
5772 #define SCU_CLK_CGATCLR2_USB_Msk (0x80UL)
5773 #define SCU_CLK_CGATCLR2_ECAT0_Pos (10UL)
5774 #define SCU_CLK_CGATCLR2_ECAT0_Msk (0x400UL)
5776 /* ------------------------------ SCU_CLK_CGATSTAT3 ----------------------------- */
5777 #define SCU_CLK_CGATSTAT3_EBU_Pos (2UL)
5778 #define SCU_CLK_CGATSTAT3_EBU_Msk (0x4UL)
5780 /* ------------------------------ SCU_CLK_CGATSET3 ------------------------------ */
5781 #define SCU_CLK_CGATSET3_EBU_Pos (2UL)
5782 #define SCU_CLK_CGATSET3_EBU_Msk (0x4UL)
5784 /* ------------------------------ SCU_CLK_CGATCLR3 ------------------------------ */
5785 #define SCU_CLK_CGATCLR3_EBU_Pos (2UL)
5786 #define SCU_CLK_CGATCLR3_EBU_Msk (0x4UL)
5789 /* ================================================================================ */
5790 /* ================ struct 'SCU_OSC' Position & Mask ================ */
5791 /* ================================================================================ */
5792 
5793 
5794 /* ------------------------------ SCU_OSC_OSCHPSTAT ----------------------------- */
5795 #define SCU_OSC_OSCHPSTAT_X1D_Pos (0UL)
5796 #define SCU_OSC_OSCHPSTAT_X1D_Msk (0x1UL)
5798 /* ------------------------------ SCU_OSC_OSCHPCTRL ----------------------------- */
5799 #define SCU_OSC_OSCHPCTRL_X1DEN_Pos (0UL)
5800 #define SCU_OSC_OSCHPCTRL_X1DEN_Msk (0x1UL)
5801 #define SCU_OSC_OSCHPCTRL_SHBY_Pos (1UL)
5802 #define SCU_OSC_OSCHPCTRL_SHBY_Msk (0x2UL)
5803 #define SCU_OSC_OSCHPCTRL_GAINSEL_Pos (2UL)
5804 #define SCU_OSC_OSCHPCTRL_GAINSEL_Msk (0xcUL)
5805 #define SCU_OSC_OSCHPCTRL_MODE_Pos (4UL)
5806 #define SCU_OSC_OSCHPCTRL_MODE_Msk (0x30UL)
5807 #define SCU_OSC_OSCHPCTRL_OSCVAL_Pos (16UL)
5808 #define SCU_OSC_OSCHPCTRL_OSCVAL_Msk (0xf0000UL)
5810 /* ----------------------------- SCU_OSC_CLKCALCONST ---------------------------- */
5811 #define SCU_OSC_CLKCALCONST_CALIBCONST_Pos (0UL)
5812 #define SCU_OSC_CLKCALCONST_CALIBCONST_Msk (0xfUL)
5815 /* ================================================================================ */
5816 /* ================ struct 'SCU_PLL' Position & Mask ================ */
5817 /* ================================================================================ */
5818 
5819 
5820 /* ------------------------------- SCU_PLL_PLLSTAT ------------------------------ */
5821 #define SCU_PLL_PLLSTAT_VCOBYST_Pos (0UL)
5822 #define SCU_PLL_PLLSTAT_VCOBYST_Msk (0x1UL)
5823 #define SCU_PLL_PLLSTAT_PWDSTAT_Pos (1UL)
5824 #define SCU_PLL_PLLSTAT_PWDSTAT_Msk (0x2UL)
5825 #define SCU_PLL_PLLSTAT_VCOLOCK_Pos (2UL)
5826 #define SCU_PLL_PLLSTAT_VCOLOCK_Msk (0x4UL)
5827 #define SCU_PLL_PLLSTAT_K1RDY_Pos (4UL)
5828 #define SCU_PLL_PLLSTAT_K1RDY_Msk (0x10UL)
5829 #define SCU_PLL_PLLSTAT_K2RDY_Pos (5UL)
5830 #define SCU_PLL_PLLSTAT_K2RDY_Msk (0x20UL)
5831 #define SCU_PLL_PLLSTAT_BY_Pos (6UL)
5832 #define SCU_PLL_PLLSTAT_BY_Msk (0x40UL)
5833 #define SCU_PLL_PLLSTAT_PLLLV_Pos (7UL)
5834 #define SCU_PLL_PLLSTAT_PLLLV_Msk (0x80UL)
5835 #define SCU_PLL_PLLSTAT_PLLHV_Pos (8UL)
5836 #define SCU_PLL_PLLSTAT_PLLHV_Msk (0x100UL)
5837 #define SCU_PLL_PLLSTAT_PLLSP_Pos (9UL)
5838 #define SCU_PLL_PLLSTAT_PLLSP_Msk (0x200UL)
5840 /* ------------------------------- SCU_PLL_PLLCON0 ------------------------------ */
5841 #define SCU_PLL_PLLCON0_VCOBYP_Pos (0UL)
5842 #define SCU_PLL_PLLCON0_VCOBYP_Msk (0x1UL)
5843 #define SCU_PLL_PLLCON0_VCOPWD_Pos (1UL)
5844 #define SCU_PLL_PLLCON0_VCOPWD_Msk (0x2UL)
5845 #define SCU_PLL_PLLCON0_VCOTR_Pos (2UL)
5846 #define SCU_PLL_PLLCON0_VCOTR_Msk (0x4UL)
5847 #define SCU_PLL_PLLCON0_FINDIS_Pos (4UL)
5848 #define SCU_PLL_PLLCON0_FINDIS_Msk (0x10UL)
5849 #define SCU_PLL_PLLCON0_OSCDISCDIS_Pos (6UL)
5850 #define SCU_PLL_PLLCON0_OSCDISCDIS_Msk (0x40UL)
5851 #define SCU_PLL_PLLCON0_PLLPWD_Pos (16UL)
5852 #define SCU_PLL_PLLCON0_PLLPWD_Msk (0x10000UL)
5853 #define SCU_PLL_PLLCON0_OSCRES_Pos (17UL)
5854 #define SCU_PLL_PLLCON0_OSCRES_Msk (0x20000UL)
5855 #define SCU_PLL_PLLCON0_RESLD_Pos (18UL)
5856 #define SCU_PLL_PLLCON0_RESLD_Msk (0x40000UL)
5857 #define SCU_PLL_PLLCON0_AOTREN_Pos (19UL)
5858 #define SCU_PLL_PLLCON0_AOTREN_Msk (0x80000UL)
5859 #define SCU_PLL_PLLCON0_FOTR_Pos (20UL)
5860 #define SCU_PLL_PLLCON0_FOTR_Msk (0x100000UL)
5862 /* ------------------------------- SCU_PLL_PLLCON1 ------------------------------ */
5863 #define SCU_PLL_PLLCON1_K1DIV_Pos (0UL)
5864 #define SCU_PLL_PLLCON1_K1DIV_Msk (0x7fUL)
5865 #define SCU_PLL_PLLCON1_NDIV_Pos (8UL)
5866 #define SCU_PLL_PLLCON1_NDIV_Msk (0x7f00UL)
5867 #define SCU_PLL_PLLCON1_K2DIV_Pos (16UL)
5868 #define SCU_PLL_PLLCON1_K2DIV_Msk (0x7f0000UL)
5869 #define SCU_PLL_PLLCON1_PDIV_Pos (24UL)
5870 #define SCU_PLL_PLLCON1_PDIV_Msk (0xf000000UL)
5872 /* ------------------------------- SCU_PLL_PLLCON2 ------------------------------ */
5873 #define SCU_PLL_PLLCON2_PINSEL_Pos (0UL)
5874 #define SCU_PLL_PLLCON2_PINSEL_Msk (0x1UL)
5875 #define SCU_PLL_PLLCON2_K1INSEL_Pos (8UL)
5876 #define SCU_PLL_PLLCON2_K1INSEL_Msk (0x100UL)
5878 /* ----------------------------- SCU_PLL_USBPLLSTAT ----------------------------- */
5879 #define SCU_PLL_USBPLLSTAT_VCOBYST_Pos (0UL)
5880 #define SCU_PLL_USBPLLSTAT_VCOBYST_Msk (0x1UL)
5881 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Pos (1UL)
5882 #define SCU_PLL_USBPLLSTAT_PWDSTAT_Msk (0x2UL)
5883 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Pos (2UL)
5884 #define SCU_PLL_USBPLLSTAT_VCOLOCK_Msk (0x4UL)
5885 #define SCU_PLL_USBPLLSTAT_BY_Pos (6UL)
5886 #define SCU_PLL_USBPLLSTAT_BY_Msk (0x40UL)
5887 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Pos (7UL)
5888 #define SCU_PLL_USBPLLSTAT_VCOLOCKED_Msk (0x80UL)
5890 /* ------------------------------ SCU_PLL_USBPLLCON ----------------------------- */
5891 #define SCU_PLL_USBPLLCON_VCOBYP_Pos (0UL)
5892 #define SCU_PLL_USBPLLCON_VCOBYP_Msk (0x1UL)
5893 #define SCU_PLL_USBPLLCON_VCOPWD_Pos (1UL)
5894 #define SCU_PLL_USBPLLCON_VCOPWD_Msk (0x2UL)
5895 #define SCU_PLL_USBPLLCON_VCOTR_Pos (2UL)
5896 #define SCU_PLL_USBPLLCON_VCOTR_Msk (0x4UL)
5897 #define SCU_PLL_USBPLLCON_FINDIS_Pos (4UL)
5898 #define SCU_PLL_USBPLLCON_FINDIS_Msk (0x10UL)
5899 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Pos (6UL)
5900 #define SCU_PLL_USBPLLCON_OSCDISCDIS_Msk (0x40UL)
5901 #define SCU_PLL_USBPLLCON_NDIV_Pos (8UL)
5902 #define SCU_PLL_USBPLLCON_NDIV_Msk (0x7f00UL)
5903 #define SCU_PLL_USBPLLCON_PLLPWD_Pos (16UL)
5904 #define SCU_PLL_USBPLLCON_PLLPWD_Msk (0x10000UL)
5905 #define SCU_PLL_USBPLLCON_RESLD_Pos (18UL)
5906 #define SCU_PLL_USBPLLCON_RESLD_Msk (0x40000UL)
5907 #define SCU_PLL_USBPLLCON_PDIV_Pos (24UL)
5908 #define SCU_PLL_USBPLLCON_PDIV_Msk (0xf000000UL)
5910 /* ------------------------------ SCU_PLL_CLKMXSTAT ----------------------------- */
5911 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Pos (0UL)
5912 #define SCU_PLL_CLKMXSTAT_SYSCLKMUX_Msk (0x3UL)
5915 /* ================================================================================ */
5916 /* ================ struct 'SCU_GENERAL' Position & Mask ================ */
5917 /* ================================================================================ */
5918 
5919 
5920 /* ------------------------------- SCU_GENERAL_ID ------------------------------- */
5921 #define SCU_GENERAL_ID_MOD_REV_Pos (0UL)
5922 #define SCU_GENERAL_ID_MOD_REV_Msk (0xffUL)
5923 #define SCU_GENERAL_ID_MOD_TYPE_Pos (8UL)
5924 #define SCU_GENERAL_ID_MOD_TYPE_Msk (0xff00UL)
5925 #define SCU_GENERAL_ID_MOD_NUMBER_Pos (16UL)
5926 #define SCU_GENERAL_ID_MOD_NUMBER_Msk (0xffff0000UL)
5928 /* ----------------------------- SCU_GENERAL_IDCHIP ----------------------------- */
5929 #define SCU_GENERAL_IDCHIP_IDCHIP_Pos (0UL)
5930 #define SCU_GENERAL_IDCHIP_IDCHIP_Msk (0xffffffffUL)
5932 /* ----------------------------- SCU_GENERAL_IDMANUF ---------------------------- */
5933 #define SCU_GENERAL_IDMANUF_DEPT_Pos (0UL)
5934 #define SCU_GENERAL_IDMANUF_DEPT_Msk (0x1fUL)
5935 #define SCU_GENERAL_IDMANUF_MANUF_Pos (5UL)
5936 #define SCU_GENERAL_IDMANUF_MANUF_Msk (0xffe0UL)
5938 /* ------------------------------ SCU_GENERAL_STCON ----------------------------- */
5939 #define SCU_GENERAL_STCON_HWCON_Pos (0UL)
5940 #define SCU_GENERAL_STCON_HWCON_Msk (0x3UL)
5941 #define SCU_GENERAL_STCON_SWCON_Pos (8UL)
5942 #define SCU_GENERAL_STCON_SWCON_Msk (0xf00UL)
5944 /* ------------------------------- SCU_GENERAL_GPR ------------------------------ */
5945 #define SCU_GENERAL_GPR_DAT_Pos (0UL)
5946 #define SCU_GENERAL_GPR_DAT_Msk (0xffffffffUL)
5948 /* ----------------------------- SCU_GENERAL_CCUCON ----------------------------- */
5949 #define SCU_GENERAL_CCUCON_GSC40_Pos (0UL)
5950 #define SCU_GENERAL_CCUCON_GSC40_Msk (0x1UL)
5951 #define SCU_GENERAL_CCUCON_GSC41_Pos (1UL)
5952 #define SCU_GENERAL_CCUCON_GSC41_Msk (0x2UL)
5953 #define SCU_GENERAL_CCUCON_GSC42_Pos (2UL)
5954 #define SCU_GENERAL_CCUCON_GSC42_Msk (0x4UL)
5955 #define SCU_GENERAL_CCUCON_GSC43_Pos (3UL)
5956 #define SCU_GENERAL_CCUCON_GSC43_Msk (0x8UL)
5957 #define SCU_GENERAL_CCUCON_GSC80_Pos (8UL)
5958 #define SCU_GENERAL_CCUCON_GSC80_Msk (0x100UL)
5959 #define SCU_GENERAL_CCUCON_GSC81_Pos (9UL)
5960 #define SCU_GENERAL_CCUCON_GSC81_Msk (0x200UL)
5962 /* ----------------------------- SCU_GENERAL_DTSCON ----------------------------- */
5963 #define SCU_GENERAL_DTSCON_PWD_Pos (0UL)
5964 #define SCU_GENERAL_DTSCON_PWD_Msk (0x1UL)
5965 #define SCU_GENERAL_DTSCON_START_Pos (1UL)
5966 #define SCU_GENERAL_DTSCON_START_Msk (0x2UL)
5967 #define SCU_GENERAL_DTSCON_OFFSET_Pos (4UL)
5968 #define SCU_GENERAL_DTSCON_OFFSET_Msk (0x7f0UL)
5969 #define SCU_GENERAL_DTSCON_GAIN_Pos (11UL)
5970 #define SCU_GENERAL_DTSCON_GAIN_Msk (0x1f800UL)
5971 #define SCU_GENERAL_DTSCON_REFTRIM_Pos (17UL)
5972 #define SCU_GENERAL_DTSCON_REFTRIM_Msk (0xe0000UL)
5973 #define SCU_GENERAL_DTSCON_BGTRIM_Pos (20UL)
5974 #define SCU_GENERAL_DTSCON_BGTRIM_Msk (0xf00000UL)
5976 /* ----------------------------- SCU_GENERAL_DTSSTAT ---------------------------- */
5977 #define SCU_GENERAL_DTSSTAT_RESULT_Pos (0UL)
5978 #define SCU_GENERAL_DTSSTAT_RESULT_Msk (0x3ffUL)
5979 #define SCU_GENERAL_DTSSTAT_RDY_Pos (14UL)
5980 #define SCU_GENERAL_DTSSTAT_RDY_Msk (0x4000UL)
5981 #define SCU_GENERAL_DTSSTAT_BUSY_Pos (15UL)
5982 #define SCU_GENERAL_DTSSTAT_BUSY_Msk (0x8000UL)
5984 /* ---------------------------- SCU_GENERAL_SDMMCDEL ---------------------------- */
5985 #define SCU_GENERAL_SDMMCDEL_TAPEN_Pos (0UL)
5986 #define SCU_GENERAL_SDMMCDEL_TAPEN_Msk (0x1UL)
5987 #define SCU_GENERAL_SDMMCDEL_TAPDEL_Pos (4UL)
5988 #define SCU_GENERAL_SDMMCDEL_TAPDEL_Msk (0xf0UL)
5990 /* ----------------------------- SCU_GENERAL_GORCEN ----------------------------- */
5991 #define SCU_GENERAL_GORCEN_ENORC6_Pos (6UL)
5992 #define SCU_GENERAL_GORCEN_ENORC6_Msk (0x40UL)
5993 #define SCU_GENERAL_GORCEN_ENORC7_Pos (7UL)
5994 #define SCU_GENERAL_GORCEN_ENORC7_Msk (0x80UL)
5996 /* ----------------------------- SCU_GENERAL_MIRRSTS ---------------------------- */
5997 #define SCU_GENERAL_MIRRSTS_HDCLR_Pos (1UL)
5998 #define SCU_GENERAL_MIRRSTS_HDCLR_Msk (0x2UL)
5999 #define SCU_GENERAL_MIRRSTS_HDSET_Pos (2UL)
6000 #define SCU_GENERAL_MIRRSTS_HDSET_Msk (0x4UL)
6001 #define SCU_GENERAL_MIRRSTS_HDCR_Pos (3UL)
6002 #define SCU_GENERAL_MIRRSTS_HDCR_Msk (0x8UL)
6003 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Pos (5UL)
6004 #define SCU_GENERAL_MIRRSTS_OSCSICTRL_Msk (0x20UL)
6005 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Pos (7UL)
6006 #define SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk (0x80UL)
6007 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Pos (8UL)
6008 #define SCU_GENERAL_MIRRSTS_RTC_CTR_Msk (0x100UL)
6009 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Pos (9UL)
6010 #define SCU_GENERAL_MIRRSTS_RTC_ATIM0_Msk (0x200UL)
6011 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Pos (10UL)
6012 #define SCU_GENERAL_MIRRSTS_RTC_ATIM1_Msk (0x400UL)
6013 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Pos (11UL)
6014 #define SCU_GENERAL_MIRRSTS_RTC_TIM0_Msk (0x800UL)
6015 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Pos (12UL)
6016 #define SCU_GENERAL_MIRRSTS_RTC_TIM1_Msk (0x1000UL)
6017 #define SCU_GENERAL_MIRRSTS_RMX_Pos (13UL)
6018 #define SCU_GENERAL_MIRRSTS_RMX_Msk (0x2000UL)
6019 #define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Pos (14UL)
6020 #define SCU_GENERAL_MIRRSTS_RTC_MSKSR_Msk (0x4000UL)
6021 #define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Pos (15UL)
6022 #define SCU_GENERAL_MIRRSTS_RTC_CLRSR_Msk (0x8000UL)
6024 /* ------------------------------ SCU_GENERAL_RMACR ----------------------------- */
6025 #define SCU_GENERAL_RMACR_RDWR_Pos (0UL)
6026 #define SCU_GENERAL_RMACR_RDWR_Msk (0x1UL)
6027 #define SCU_GENERAL_RMACR_ADDR_Pos (16UL)
6028 #define SCU_GENERAL_RMACR_ADDR_Msk (0xf0000UL)
6030 /* ----------------------------- SCU_GENERAL_RMDATA ----------------------------- */
6031 #define SCU_GENERAL_RMDATA_DATA_Pos (0UL)
6032 #define SCU_GENERAL_RMDATA_DATA_Msk (0xffffffffUL)
6035 /* ================================================================================ */
6036 /* ================ struct 'SCU_INTERRUPT' Position & Mask ================ */
6037 /* ================================================================================ */
6038 
6039 
6040 /* ---------------------------- SCU_INTERRUPT_SRSTAT ---------------------------- */
6041 #define SCU_INTERRUPT_SRSTAT_PRWARN_Pos (0UL)
6042 #define SCU_INTERRUPT_SRSTAT_PRWARN_Msk (0x1UL)
6043 #define SCU_INTERRUPT_SRSTAT_PI_Pos (1UL)
6044 #define SCU_INTERRUPT_SRSTAT_PI_Msk (0x2UL)
6045 #define SCU_INTERRUPT_SRSTAT_AI_Pos (2UL)
6046 #define SCU_INTERRUPT_SRSTAT_AI_Msk (0x4UL)
6047 #define SCU_INTERRUPT_SRSTAT_DLROVR_Pos (3UL)
6048 #define SCU_INTERRUPT_SRSTAT_DLROVR_Msk (0x8UL)
6049 #define SCU_INTERRUPT_SRSTAT_HDCLR_Pos (17UL)
6050 #define SCU_INTERRUPT_SRSTAT_HDCLR_Msk (0x20000UL)
6051 #define SCU_INTERRUPT_SRSTAT_HDSET_Pos (18UL)
6052 #define SCU_INTERRUPT_SRSTAT_HDSET_Msk (0x40000UL)
6053 #define SCU_INTERRUPT_SRSTAT_HDCR_Pos (19UL)
6054 #define SCU_INTERRUPT_SRSTAT_HDCR_Msk (0x80000UL)
6055 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Pos (21UL)
6056 #define SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk (0x200000UL)
6057 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Pos (23UL)
6058 #define SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk (0x800000UL)
6059 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Pos (24UL)
6060 #define SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk (0x1000000UL)
6061 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Pos (25UL)
6062 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk (0x2000000UL)
6063 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Pos (26UL)
6064 #define SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk (0x4000000UL)
6065 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Pos (27UL)
6066 #define SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk (0x8000000UL)
6067 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Pos (28UL)
6068 #define SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk (0x10000000UL)
6069 #define SCU_INTERRUPT_SRSTAT_RMX_Pos (29UL)
6070 #define SCU_INTERRUPT_SRSTAT_RMX_Msk (0x20000000UL)
6072 /* ----------------------------- SCU_INTERRUPT_SRRAW ---------------------------- */
6073 #define SCU_INTERRUPT_SRRAW_PRWARN_Pos (0UL)
6074 #define SCU_INTERRUPT_SRRAW_PRWARN_Msk (0x1UL)
6075 #define SCU_INTERRUPT_SRRAW_PI_Pos (1UL)
6076 #define SCU_INTERRUPT_SRRAW_PI_Msk (0x2UL)
6077 #define SCU_INTERRUPT_SRRAW_AI_Pos (2UL)
6078 #define SCU_INTERRUPT_SRRAW_AI_Msk (0x4UL)
6079 #define SCU_INTERRUPT_SRRAW_DLROVR_Pos (3UL)
6080 #define SCU_INTERRUPT_SRRAW_DLROVR_Msk (0x8UL)
6081 #define SCU_INTERRUPT_SRRAW_HDCLR_Pos (17UL)
6082 #define SCU_INTERRUPT_SRRAW_HDCLR_Msk (0x20000UL)
6083 #define SCU_INTERRUPT_SRRAW_HDSET_Pos (18UL)
6084 #define SCU_INTERRUPT_SRRAW_HDSET_Msk (0x40000UL)
6085 #define SCU_INTERRUPT_SRRAW_HDCR_Pos (19UL)
6086 #define SCU_INTERRUPT_SRRAW_HDCR_Msk (0x80000UL)
6087 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Pos (21UL)
6088 #define SCU_INTERRUPT_SRRAW_OSCSICTRL_Msk (0x200000UL)
6089 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Pos (23UL)
6090 #define SCU_INTERRUPT_SRRAW_OSCULCTRL_Msk (0x800000UL)
6091 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Pos (24UL)
6092 #define SCU_INTERRUPT_SRRAW_RTC_CTR_Msk (0x1000000UL)
6093 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Pos (25UL)
6094 #define SCU_INTERRUPT_SRRAW_RTC_ATIM0_Msk (0x2000000UL)
6095 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Pos (26UL)
6096 #define SCU_INTERRUPT_SRRAW_RTC_ATIM1_Msk (0x4000000UL)
6097 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Pos (27UL)
6098 #define SCU_INTERRUPT_SRRAW_RTC_TIM0_Msk (0x8000000UL)
6099 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Pos (28UL)
6100 #define SCU_INTERRUPT_SRRAW_RTC_TIM1_Msk (0x10000000UL)
6101 #define SCU_INTERRUPT_SRRAW_RMX_Pos (29UL)
6102 #define SCU_INTERRUPT_SRRAW_RMX_Msk (0x20000000UL)
6104 /* ----------------------------- SCU_INTERRUPT_SRMSK ---------------------------- */
6105 #define SCU_INTERRUPT_SRMSK_PRWARN_Pos (0UL)
6106 #define SCU_INTERRUPT_SRMSK_PRWARN_Msk (0x1UL)
6107 #define SCU_INTERRUPT_SRMSK_PI_Pos (1UL)
6108 #define SCU_INTERRUPT_SRMSK_PI_Msk (0x2UL)
6109 #define SCU_INTERRUPT_SRMSK_AI_Pos (2UL)
6110 #define SCU_INTERRUPT_SRMSK_AI_Msk (0x4UL)
6111 #define SCU_INTERRUPT_SRMSK_DLROVR_Pos (3UL)
6112 #define SCU_INTERRUPT_SRMSK_DLROVR_Msk (0x8UL)
6113 #define SCU_INTERRUPT_SRMSK_HDCLR_Pos (17UL)
6114 #define SCU_INTERRUPT_SRMSK_HDCLR_Msk (0x20000UL)
6115 #define SCU_INTERRUPT_SRMSK_HDSET_Pos (18UL)
6116 #define SCU_INTERRUPT_SRMSK_HDSET_Msk (0x40000UL)
6117 #define SCU_INTERRUPT_SRMSK_HDCR_Pos (19UL)
6118 #define SCU_INTERRUPT_SRMSK_HDCR_Msk (0x80000UL)
6119 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Pos (21UL)
6120 #define SCU_INTERRUPT_SRMSK_OSCSICTRL_Msk (0x200000UL)
6121 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Pos (23UL)
6122 #define SCU_INTERRUPT_SRMSK_OSCULCTRL_Msk (0x800000UL)
6123 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Pos (24UL)
6124 #define SCU_INTERRUPT_SRMSK_RTC_CTR_Msk (0x1000000UL)
6125 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Pos (25UL)
6126 #define SCU_INTERRUPT_SRMSK_RTC_ATIM0_Msk (0x2000000UL)
6127 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Pos (26UL)
6128 #define SCU_INTERRUPT_SRMSK_RTC_ATIM1_Msk (0x4000000UL)
6129 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Pos (27UL)
6130 #define SCU_INTERRUPT_SRMSK_RTC_TIM0_Msk (0x8000000UL)
6131 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Pos (28UL)
6132 #define SCU_INTERRUPT_SRMSK_RTC_TIM1_Msk (0x10000000UL)
6133 #define SCU_INTERRUPT_SRMSK_RMX_Pos (29UL)
6134 #define SCU_INTERRUPT_SRMSK_RMX_Msk (0x20000000UL)
6136 /* ----------------------------- SCU_INTERRUPT_SRCLR ---------------------------- */
6137 #define SCU_INTERRUPT_SRCLR_PRWARN_Pos (0UL)
6138 #define SCU_INTERRUPT_SRCLR_PRWARN_Msk (0x1UL)
6139 #define SCU_INTERRUPT_SRCLR_PI_Pos (1UL)
6140 #define SCU_INTERRUPT_SRCLR_PI_Msk (0x2UL)
6141 #define SCU_INTERRUPT_SRCLR_AI_Pos (2UL)
6142 #define SCU_INTERRUPT_SRCLR_AI_Msk (0x4UL)
6143 #define SCU_INTERRUPT_SRCLR_DLROVR_Pos (3UL)
6144 #define SCU_INTERRUPT_SRCLR_DLROVR_Msk (0x8UL)
6145 #define SCU_INTERRUPT_SRCLR_HDCLR_Pos (17UL)
6146 #define SCU_INTERRUPT_SRCLR_HDCLR_Msk (0x20000UL)
6147 #define SCU_INTERRUPT_SRCLR_HDSET_Pos (18UL)
6148 #define SCU_INTERRUPT_SRCLR_HDSET_Msk (0x40000UL)
6149 #define SCU_INTERRUPT_SRCLR_HDCR_Pos (19UL)
6150 #define SCU_INTERRUPT_SRCLR_HDCR_Msk (0x80000UL)
6151 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Pos (21UL)
6152 #define SCU_INTERRUPT_SRCLR_OSCSICTRL_Msk (0x200000UL)
6153 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Pos (23UL)
6154 #define SCU_INTERRUPT_SRCLR_OSCULCTRL_Msk (0x800000UL)
6155 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Pos (24UL)
6156 #define SCU_INTERRUPT_SRCLR_RTC_CTR_Msk (0x1000000UL)
6157 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Pos (25UL)
6158 #define SCU_INTERRUPT_SRCLR_RTC_ATIM0_Msk (0x2000000UL)
6159 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Pos (26UL)
6160 #define SCU_INTERRUPT_SRCLR_RTC_ATIM1_Msk (0x4000000UL)
6161 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Pos (27UL)
6162 #define SCU_INTERRUPT_SRCLR_RTC_TIM0_Msk (0x8000000UL)
6163 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Pos (28UL)
6164 #define SCU_INTERRUPT_SRCLR_RTC_TIM1_Msk (0x10000000UL)
6165 #define SCU_INTERRUPT_SRCLR_RMX_Pos (29UL)
6166 #define SCU_INTERRUPT_SRCLR_RMX_Msk (0x20000000UL)
6168 /* ----------------------------- SCU_INTERRUPT_SRSET ---------------------------- */
6169 #define SCU_INTERRUPT_SRSET_PRWARN_Pos (0UL)
6170 #define SCU_INTERRUPT_SRSET_PRWARN_Msk (0x1UL)
6171 #define SCU_INTERRUPT_SRSET_PI_Pos (1UL)
6172 #define SCU_INTERRUPT_SRSET_PI_Msk (0x2UL)
6173 #define SCU_INTERRUPT_SRSET_AI_Pos (2UL)
6174 #define SCU_INTERRUPT_SRSET_AI_Msk (0x4UL)
6175 #define SCU_INTERRUPT_SRSET_DLROVR_Pos (3UL)
6176 #define SCU_INTERRUPT_SRSET_DLROVR_Msk (0x8UL)
6177 #define SCU_INTERRUPT_SRSET_HDCRCLR_Pos (17UL)
6178 #define SCU_INTERRUPT_SRSET_HDCRCLR_Msk (0x20000UL)
6179 #define SCU_INTERRUPT_SRSET_HDCRSET_Pos (18UL)
6180 #define SCU_INTERRUPT_SRSET_HDCRSET_Msk (0x40000UL)
6181 #define SCU_INTERRUPT_SRSET_HDCR_Pos (19UL)
6182 #define SCU_INTERRUPT_SRSET_HDCR_Msk (0x80000UL)
6183 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Pos (21UL)
6184 #define SCU_INTERRUPT_SRSET_OSCSICTRL_Msk (0x200000UL)
6185 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Pos (23UL)
6186 #define SCU_INTERRUPT_SRSET_OSCULCTRL_Msk (0x800000UL)
6187 #define SCU_INTERRUPT_SRSET_RTC_CTR_Pos (24UL)
6188 #define SCU_INTERRUPT_SRSET_RTC_CTR_Msk (0x1000000UL)
6189 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Pos (25UL)
6190 #define SCU_INTERRUPT_SRSET_RTC_ATIM0_Msk (0x2000000UL)
6191 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Pos (26UL)
6192 #define SCU_INTERRUPT_SRSET_RTC_ATIM1_Msk (0x4000000UL)
6193 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Pos (27UL)
6194 #define SCU_INTERRUPT_SRSET_RTC_TIM0_Msk (0x8000000UL)
6195 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Pos (28UL)
6196 #define SCU_INTERRUPT_SRSET_RTC_TIM1_Msk (0x10000000UL)
6197 #define SCU_INTERRUPT_SRSET_RMX_Pos (29UL)
6198 #define SCU_INTERRUPT_SRSET_RMX_Msk (0x20000000UL)
6200 /* --------------------------- SCU_INTERRUPT_NMIREQEN --------------------------- */
6201 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Pos (0UL)
6202 #define SCU_INTERRUPT_NMIREQEN_PRWARN_Msk (0x1UL)
6203 #define SCU_INTERRUPT_NMIREQEN_PI_Pos (1UL)
6204 #define SCU_INTERRUPT_NMIREQEN_PI_Msk (0x2UL)
6205 #define SCU_INTERRUPT_NMIREQEN_AI_Pos (2UL)
6206 #define SCU_INTERRUPT_NMIREQEN_AI_Msk (0x4UL)
6207 #define SCU_INTERRUPT_NMIREQEN_ERU00_Pos (16UL)
6208 #define SCU_INTERRUPT_NMIREQEN_ERU00_Msk (0x10000UL)
6209 #define SCU_INTERRUPT_NMIREQEN_ERU01_Pos (17UL)
6210 #define SCU_INTERRUPT_NMIREQEN_ERU01_Msk (0x20000UL)
6211 #define SCU_INTERRUPT_NMIREQEN_ERU02_Pos (18UL)
6212 #define SCU_INTERRUPT_NMIREQEN_ERU02_Msk (0x40000UL)
6213 #define SCU_INTERRUPT_NMIREQEN_ERU03_Pos (19UL)
6214 #define SCU_INTERRUPT_NMIREQEN_ERU03_Msk (0x80000UL)
6217 /* ================================================================================ */
6218 /* ================ struct 'SCU_PARITY' Position & Mask ================ */
6219 /* ================================================================================ */
6220 
6221 
6222 /* ------------------------------- SCU_PARITY_PEEN ------------------------------ */
6223 #define SCU_PARITY_PEEN_PEENPS_Pos (0UL)
6224 #define SCU_PARITY_PEEN_PEENPS_Msk (0x1UL)
6225 #define SCU_PARITY_PEEN_PEENDS1_Pos (1UL)
6226 #define SCU_PARITY_PEEN_PEENDS1_Msk (0x2UL)
6227 #define SCU_PARITY_PEEN_PEENDS2_Pos (2UL)
6228 #define SCU_PARITY_PEEN_PEENDS2_Msk (0x4UL)
6229 #define SCU_PARITY_PEEN_PEENU0_Pos (8UL)
6230 #define SCU_PARITY_PEEN_PEENU0_Msk (0x100UL)
6231 #define SCU_PARITY_PEEN_PEENU1_Pos (9UL)
6232 #define SCU_PARITY_PEEN_PEENU1_Msk (0x200UL)
6233 #define SCU_PARITY_PEEN_PEENU2_Pos (10UL)
6234 #define SCU_PARITY_PEEN_PEENU2_Msk (0x400UL)
6235 #define SCU_PARITY_PEEN_PEENMC_Pos (12UL)
6236 #define SCU_PARITY_PEEN_PEENMC_Msk (0x1000UL)
6237 #define SCU_PARITY_PEEN_PEENPPRF_Pos (13UL)
6238 #define SCU_PARITY_PEEN_PEENPPRF_Msk (0x2000UL)
6239 #define SCU_PARITY_PEEN_PEENUSB_Pos (16UL)
6240 #define SCU_PARITY_PEEN_PEENUSB_Msk (0x10000UL)
6241 #define SCU_PARITY_PEEN_PEENETH0TX_Pos (17UL)
6242 #define SCU_PARITY_PEEN_PEENETH0TX_Msk (0x20000UL)
6243 #define SCU_PARITY_PEEN_PEENETH0RX_Pos (18UL)
6244 #define SCU_PARITY_PEEN_PEENETH0RX_Msk (0x40000UL)
6245 #define SCU_PARITY_PEEN_PEENSD0_Pos (19UL)
6246 #define SCU_PARITY_PEEN_PEENSD0_Msk (0x80000UL)
6247 #define SCU_PARITY_PEEN_PEENSD1_Pos (20UL)
6248 #define SCU_PARITY_PEEN_PEENSD1_Msk (0x100000UL)
6249 #define SCU_PARITY_PEEN_PEENECAT0_Pos (24UL)
6250 #define SCU_PARITY_PEEN_PEENECAT0_Msk (0x1000000UL)
6252 /* ----------------------------- SCU_PARITY_MCHKCON ----------------------------- */
6253 #define SCU_PARITY_MCHKCON_SELPS_Pos (0UL)
6254 #define SCU_PARITY_MCHKCON_SELPS_Msk (0x1UL)
6255 #define SCU_PARITY_MCHKCON_SELDS1_Pos (1UL)
6256 #define SCU_PARITY_MCHKCON_SELDS1_Msk (0x2UL)
6257 #define SCU_PARITY_MCHKCON_SELDS2_Pos (2UL)
6258 #define SCU_PARITY_MCHKCON_SELDS2_Msk (0x4UL)
6259 #define SCU_PARITY_MCHKCON_USIC0DRA_Pos (8UL)
6260 #define SCU_PARITY_MCHKCON_USIC0DRA_Msk (0x100UL)
6261 #define SCU_PARITY_MCHKCON_USIC1DRA_Pos (9UL)
6262 #define SCU_PARITY_MCHKCON_USIC1DRA_Msk (0x200UL)
6263 #define SCU_PARITY_MCHKCON_USIC2DRA_Pos (10UL)
6264 #define SCU_PARITY_MCHKCON_USIC2DRA_Msk (0x400UL)
6265 #define SCU_PARITY_MCHKCON_MCANDRA_Pos (12UL)
6266 #define SCU_PARITY_MCHKCON_MCANDRA_Msk (0x1000UL)
6267 #define SCU_PARITY_MCHKCON_PPRFDRA_Pos (13UL)
6268 #define SCU_PARITY_MCHKCON_PPRFDRA_Msk (0x2000UL)
6269 #define SCU_PARITY_MCHKCON_SELUSB_Pos (16UL)
6270 #define SCU_PARITY_MCHKCON_SELUSB_Msk (0x10000UL)
6271 #define SCU_PARITY_MCHKCON_SELETH0TX_Pos (17UL)
6272 #define SCU_PARITY_MCHKCON_SELETH0TX_Msk (0x20000UL)
6273 #define SCU_PARITY_MCHKCON_SELETH0RX_Pos (18UL)
6274 #define SCU_PARITY_MCHKCON_SELETH0RX_Msk (0x40000UL)
6275 #define SCU_PARITY_MCHKCON_SELSD0_Pos (19UL)
6276 #define SCU_PARITY_MCHKCON_SELSD0_Msk (0x80000UL)
6277 #define SCU_PARITY_MCHKCON_SELSD1_Pos (20UL)
6278 #define SCU_PARITY_MCHKCON_SELSD1_Msk (0x100000UL)
6279 #define SCU_PARITY_MCHKCON_SELECAT0_Pos (24UL)
6280 #define SCU_PARITY_MCHKCON_SELECAT0_Msk (0x1000000UL)
6282 /* ------------------------------- SCU_PARITY_PETE ------------------------------ */
6283 #define SCU_PARITY_PETE_PETEPS_Pos (0UL)
6284 #define SCU_PARITY_PETE_PETEPS_Msk (0x1UL)
6285 #define SCU_PARITY_PETE_PETEDS1_Pos (1UL)
6286 #define SCU_PARITY_PETE_PETEDS1_Msk (0x2UL)
6287 #define SCU_PARITY_PETE_PETEDS2_Pos (2UL)
6288 #define SCU_PARITY_PETE_PETEDS2_Msk (0x4UL)
6289 #define SCU_PARITY_PETE_PETEU0_Pos (8UL)
6290 #define SCU_PARITY_PETE_PETEU0_Msk (0x100UL)
6291 #define SCU_PARITY_PETE_PETEU1_Pos (9UL)
6292 #define SCU_PARITY_PETE_PETEU1_Msk (0x200UL)
6293 #define SCU_PARITY_PETE_PETEU2_Pos (10UL)
6294 #define SCU_PARITY_PETE_PETEU2_Msk (0x400UL)
6295 #define SCU_PARITY_PETE_PETEMC_Pos (12UL)
6296 #define SCU_PARITY_PETE_PETEMC_Msk (0x1000UL)
6297 #define SCU_PARITY_PETE_PETEPPRF_Pos (13UL)
6298 #define SCU_PARITY_PETE_PETEPPRF_Msk (0x2000UL)
6299 #define SCU_PARITY_PETE_PETEUSB_Pos (16UL)
6300 #define SCU_PARITY_PETE_PETEUSB_Msk (0x10000UL)
6301 #define SCU_PARITY_PETE_PETEETH0TX_Pos (17UL)
6302 #define SCU_PARITY_PETE_PETEETH0TX_Msk (0x20000UL)
6303 #define SCU_PARITY_PETE_PETEETH0RX_Pos (18UL)
6304 #define SCU_PARITY_PETE_PETEETH0RX_Msk (0x40000UL)
6305 #define SCU_PARITY_PETE_PETESD0_Pos (19UL)
6306 #define SCU_PARITY_PETE_PETESD0_Msk (0x80000UL)
6307 #define SCU_PARITY_PETE_PETESD1_Pos (20UL)
6308 #define SCU_PARITY_PETE_PETESD1_Msk (0x100000UL)
6309 #define SCU_PARITY_PETE_PETEECAT0_Pos (24UL)
6310 #define SCU_PARITY_PETE_PETEECAT0_Msk (0x1000000UL)
6312 /* ----------------------------- SCU_PARITY_PERSTEN ----------------------------- */
6313 #define SCU_PARITY_PERSTEN_RSEN_Pos (0UL)
6314 #define SCU_PARITY_PERSTEN_RSEN_Msk (0x1UL)
6316 /* ------------------------------ SCU_PARITY_PEFLAG ----------------------------- */
6317 #define SCU_PARITY_PEFLAG_PEFPS_Pos (0UL)
6318 #define SCU_PARITY_PEFLAG_PEFPS_Msk (0x1UL)
6319 #define SCU_PARITY_PEFLAG_PEFDS1_Pos (1UL)
6320 #define SCU_PARITY_PEFLAG_PEFDS1_Msk (0x2UL)
6321 #define SCU_PARITY_PEFLAG_PEFDS2_Pos (2UL)
6322 #define SCU_PARITY_PEFLAG_PEFDS2_Msk (0x4UL)
6323 #define SCU_PARITY_PEFLAG_PEFU0_Pos (8UL)
6324 #define SCU_PARITY_PEFLAG_PEFU0_Msk (0x100UL)
6325 #define SCU_PARITY_PEFLAG_PEFU1_Pos (9UL)
6326 #define SCU_PARITY_PEFLAG_PEFU1_Msk (0x200UL)
6327 #define SCU_PARITY_PEFLAG_PEFU2_Pos (10UL)
6328 #define SCU_PARITY_PEFLAG_PEFU2_Msk (0x400UL)
6329 #define SCU_PARITY_PEFLAG_PEFMC_Pos (12UL)
6330 #define SCU_PARITY_PEFLAG_PEFMC_Msk (0x1000UL)
6331 #define SCU_PARITY_PEFLAG_PEFPPRF_Pos (13UL)
6332 #define SCU_PARITY_PEFLAG_PEFPPRF_Msk (0x2000UL)
6333 #define SCU_PARITY_PEFLAG_PEUSB_Pos (16UL)
6334 #define SCU_PARITY_PEFLAG_PEUSB_Msk (0x10000UL)
6335 #define SCU_PARITY_PEFLAG_PEETH0TX_Pos (17UL)
6336 #define SCU_PARITY_PEFLAG_PEETH0TX_Msk (0x20000UL)
6337 #define SCU_PARITY_PEFLAG_PEETH0RX_Pos (18UL)
6338 #define SCU_PARITY_PEFLAG_PEETH0RX_Msk (0x40000UL)
6339 #define SCU_PARITY_PEFLAG_PESD0_Pos (19UL)
6340 #define SCU_PARITY_PEFLAG_PESD0_Msk (0x80000UL)
6341 #define SCU_PARITY_PEFLAG_PESD1_Pos (20UL)
6342 #define SCU_PARITY_PEFLAG_PESD1_Msk (0x100000UL)
6343 #define SCU_PARITY_PEFLAG_PEECAT0_Pos (24UL)
6344 #define SCU_PARITY_PEFLAG_PEECAT0_Msk (0x1000000UL)
6346 /* ------------------------------ SCU_PARITY_PMTPR ------------------------------ */
6347 #define SCU_PARITY_PMTPR_PWR_Pos (0UL)
6348 #define SCU_PARITY_PMTPR_PWR_Msk (0xffUL)
6349 #define SCU_PARITY_PMTPR_PRD_Pos (8UL)
6350 #define SCU_PARITY_PMTPR_PRD_Msk (0xff00UL)
6352 /* ------------------------------ SCU_PARITY_PMTSR ------------------------------ */
6353 #define SCU_PARITY_PMTSR_MTENPS_Pos (0UL)
6354 #define SCU_PARITY_PMTSR_MTENPS_Msk (0x1UL)
6355 #define SCU_PARITY_PMTSR_MTENDS1_Pos (1UL)
6356 #define SCU_PARITY_PMTSR_MTENDS1_Msk (0x2UL)
6357 #define SCU_PARITY_PMTSR_MTENDS2_Pos (2UL)
6358 #define SCU_PARITY_PMTSR_MTENDS2_Msk (0x4UL)
6359 #define SCU_PARITY_PMTSR_MTEU0_Pos (8UL)
6360 #define SCU_PARITY_PMTSR_MTEU0_Msk (0x100UL)
6361 #define SCU_PARITY_PMTSR_MTEU1_Pos (9UL)
6362 #define SCU_PARITY_PMTSR_MTEU1_Msk (0x200UL)
6363 #define SCU_PARITY_PMTSR_MTEU2_Pos (10UL)
6364 #define SCU_PARITY_PMTSR_MTEU2_Msk (0x400UL)
6365 #define SCU_PARITY_PMTSR_MTEMC_Pos (12UL)
6366 #define SCU_PARITY_PMTSR_MTEMC_Msk (0x1000UL)
6367 #define SCU_PARITY_PMTSR_MTEPPRF_Pos (13UL)
6368 #define SCU_PARITY_PMTSR_MTEPPRF_Msk (0x2000UL)
6369 #define SCU_PARITY_PMTSR_MTUSB_Pos (16UL)
6370 #define SCU_PARITY_PMTSR_MTUSB_Msk (0x10000UL)
6371 #define SCU_PARITY_PMTSR_MTETH0TX_Pos (17UL)
6372 #define SCU_PARITY_PMTSR_MTETH0TX_Msk (0x20000UL)
6373 #define SCU_PARITY_PMTSR_MTETH0RX_Pos (18UL)
6374 #define SCU_PARITY_PMTSR_MTETH0RX_Msk (0x40000UL)
6375 #define SCU_PARITY_PMTSR_MTSD0_Pos (19UL)
6376 #define SCU_PARITY_PMTSR_MTSD0_Msk (0x80000UL)
6377 #define SCU_PARITY_PMTSR_MTSD1_Pos (20UL)
6378 #define SCU_PARITY_PMTSR_MTSD1_Msk (0x100000UL)
6379 #define SCU_PARITY_PMTSR_MTECAT0_Pos (24UL)
6380 #define SCU_PARITY_PMTSR_MTECAT0_Msk (0x1000000UL)
6383 /* ================================================================================ */
6384 /* ================ struct 'SCU_TRAP' Position & Mask ================ */
6385 /* ================================================================================ */
6386 
6387 
6388 /* ------------------------------ SCU_TRAP_TRAPSTAT ----------------------------- */
6389 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Pos (0UL)
6390 #define SCU_TRAP_TRAPSTAT_SOSCWDGT_Msk (0x1UL)
6391 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Pos (2UL)
6392 #define SCU_TRAP_TRAPSTAT_SVCOLCKT_Msk (0x4UL)
6393 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Pos (3UL)
6394 #define SCU_TRAP_TRAPSTAT_UVCOLCKT_Msk (0x8UL)
6395 #define SCU_TRAP_TRAPSTAT_PET_Pos (4UL)
6396 #define SCU_TRAP_TRAPSTAT_PET_Msk (0x10UL)
6397 #define SCU_TRAP_TRAPSTAT_BRWNT_Pos (5UL)
6398 #define SCU_TRAP_TRAPSTAT_BRWNT_Msk (0x20UL)
6399 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Pos (6UL)
6400 #define SCU_TRAP_TRAPSTAT_ULPWDGT_Msk (0x40UL)
6401 #define SCU_TRAP_TRAPSTAT_BWERR0T_Pos (7UL)
6402 #define SCU_TRAP_TRAPSTAT_BWERR0T_Msk (0x80UL)
6403 #define SCU_TRAP_TRAPSTAT_BWERR1T_Pos (8UL)
6404 #define SCU_TRAP_TRAPSTAT_BWERR1T_Msk (0x100UL)
6405 #define SCU_TRAP_TRAPSTAT_ECAT0RST_Pos (16UL)
6406 #define SCU_TRAP_TRAPSTAT_ECAT0RST_Msk (0x10000UL)
6408 /* ------------------------------ SCU_TRAP_TRAPRAW ------------------------------ */
6409 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Pos (0UL)
6410 #define SCU_TRAP_TRAPRAW_SOSCWDGT_Msk (0x1UL)
6411 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Pos (2UL)
6412 #define SCU_TRAP_TRAPRAW_SVCOLCKT_Msk (0x4UL)
6413 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Pos (3UL)
6414 #define SCU_TRAP_TRAPRAW_UVCOLCKT_Msk (0x8UL)
6415 #define SCU_TRAP_TRAPRAW_PET_Pos (4UL)
6416 #define SCU_TRAP_TRAPRAW_PET_Msk (0x10UL)
6417 #define SCU_TRAP_TRAPRAW_BRWNT_Pos (5UL)
6418 #define SCU_TRAP_TRAPRAW_BRWNT_Msk (0x20UL)
6419 #define SCU_TRAP_TRAPRAW_ULPWDGT_Pos (6UL)
6420 #define SCU_TRAP_TRAPRAW_ULPWDGT_Msk (0x40UL)
6421 #define SCU_TRAP_TRAPRAW_BWERR0T_Pos (7UL)
6422 #define SCU_TRAP_TRAPRAW_BWERR0T_Msk (0x80UL)
6423 #define SCU_TRAP_TRAPRAW_BWERR1T_Pos (8UL)
6424 #define SCU_TRAP_TRAPRAW_BWERR1T_Msk (0x100UL)
6425 #define SCU_TRAP_TRAPRAW_ECAT0RST_Pos (16UL)
6426 #define SCU_TRAP_TRAPRAW_ECAT0RST_Msk (0x10000UL)
6428 /* ------------------------------ SCU_TRAP_TRAPDIS ------------------------------ */
6429 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Pos (0UL)
6430 #define SCU_TRAP_TRAPDIS_SOSCWDGT_Msk (0x1UL)
6431 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Pos (2UL)
6432 #define SCU_TRAP_TRAPDIS_SVCOLCKT_Msk (0x4UL)
6433 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Pos (3UL)
6434 #define SCU_TRAP_TRAPDIS_UVCOLCKT_Msk (0x8UL)
6435 #define SCU_TRAP_TRAPDIS_PET_Pos (4UL)
6436 #define SCU_TRAP_TRAPDIS_PET_Msk (0x10UL)
6437 #define SCU_TRAP_TRAPDIS_BRWNT_Pos (5UL)
6438 #define SCU_TRAP_TRAPDIS_BRWNT_Msk (0x20UL)
6439 #define SCU_TRAP_TRAPDIS_ULPWDGT_Pos (6UL)
6440 #define SCU_TRAP_TRAPDIS_ULPWDGT_Msk (0x40UL)
6441 #define SCU_TRAP_TRAPDIS_BWERR0T_Pos (7UL)
6442 #define SCU_TRAP_TRAPDIS_BWERR0T_Msk (0x80UL)
6443 #define SCU_TRAP_TRAPDIS_BWERR1T_Pos (8UL)
6444 #define SCU_TRAP_TRAPDIS_BWERR1T_Msk (0x100UL)
6445 #define SCU_TRAP_TRAPDIS_ECAT0RST_Pos (16UL)
6446 #define SCU_TRAP_TRAPDIS_ECAT0RST_Msk (0x10000UL)
6448 /* ------------------------------ SCU_TRAP_TRAPCLR ------------------------------ */
6449 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Pos (0UL)
6450 #define SCU_TRAP_TRAPCLR_SOSCWDGT_Msk (0x1UL)
6451 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Pos (2UL)
6452 #define SCU_TRAP_TRAPCLR_SVCOLCKT_Msk (0x4UL)
6453 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Pos (3UL)
6454 #define SCU_TRAP_TRAPCLR_UVCOLCKT_Msk (0x8UL)
6455 #define SCU_TRAP_TRAPCLR_PET_Pos (4UL)
6456 #define SCU_TRAP_TRAPCLR_PET_Msk (0x10UL)
6457 #define SCU_TRAP_TRAPCLR_BRWNT_Pos (5UL)
6458 #define SCU_TRAP_TRAPCLR_BRWNT_Msk (0x20UL)
6459 #define SCU_TRAP_TRAPCLR_ULPWDGT_Pos (6UL)
6460 #define SCU_TRAP_TRAPCLR_ULPWDGT_Msk (0x40UL)
6461 #define SCU_TRAP_TRAPCLR_BWERR0T_Pos (7UL)
6462 #define SCU_TRAP_TRAPCLR_BWERR0T_Msk (0x80UL)
6463 #define SCU_TRAP_TRAPCLR_BWERR1T_Pos (8UL)
6464 #define SCU_TRAP_TRAPCLR_BWERR1T_Msk (0x100UL)
6465 #define SCU_TRAP_TRAPCLR_ECAT0RST_Pos (16UL)
6466 #define SCU_TRAP_TRAPCLR_ECAT0RST_Msk (0x10000UL)
6468 /* ------------------------------ SCU_TRAP_TRAPSET ------------------------------ */
6469 #define SCU_TRAP_TRAPSET_SOSCWDGT_Pos (0UL)
6470 #define SCU_TRAP_TRAPSET_SOSCWDGT_Msk (0x1UL)
6471 #define SCU_TRAP_TRAPSET_SVCOLCKT_Pos (2UL)
6472 #define SCU_TRAP_TRAPSET_SVCOLCKT_Msk (0x4UL)
6473 #define SCU_TRAP_TRAPSET_UVCOLCKT_Pos (3UL)
6474 #define SCU_TRAP_TRAPSET_UVCOLCKT_Msk (0x8UL)
6475 #define SCU_TRAP_TRAPSET_PET_Pos (4UL)
6476 #define SCU_TRAP_TRAPSET_PET_Msk (0x10UL)
6477 #define SCU_TRAP_TRAPSET_BRWNT_Pos (5UL)
6478 #define SCU_TRAP_TRAPSET_BRWNT_Msk (0x20UL)
6479 #define SCU_TRAP_TRAPSET_ULPWDT_Pos (6UL)
6480 #define SCU_TRAP_TRAPSET_ULPWDT_Msk (0x40UL)
6481 #define SCU_TRAP_TRAPSET_BWERR0T_Pos (7UL)
6482 #define SCU_TRAP_TRAPSET_BWERR0T_Msk (0x80UL)
6483 #define SCU_TRAP_TRAPSET_BWERR1T_Pos (8UL)
6484 #define SCU_TRAP_TRAPSET_BWERR1T_Msk (0x100UL)
6485 #define SCU_TRAP_TRAPSET_ECAT0RST_Pos (16UL)
6486 #define SCU_TRAP_TRAPSET_ECAT0RST_Msk (0x10000UL)
6489 /* ================================================================================ */
6490 /* ================ struct 'SCU_HIBERNATE' Position & Mask ================ */
6491 /* ================================================================================ */
6492 
6493 
6494 /* ---------------------------- SCU_HIBERNATE_HDSTAT ---------------------------- */
6495 #define SCU_HIBERNATE_HDSTAT_EPEV_Pos (0UL)
6496 #define SCU_HIBERNATE_HDSTAT_EPEV_Msk (0x1UL)
6497 #define SCU_HIBERNATE_HDSTAT_ENEV_Pos (1UL)
6498 #define SCU_HIBERNATE_HDSTAT_ENEV_Msk (0x2UL)
6499 #define SCU_HIBERNATE_HDSTAT_RTCEV_Pos (2UL)
6500 #define SCU_HIBERNATE_HDSTAT_RTCEV_Msk (0x4UL)
6501 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Pos (3UL)
6502 #define SCU_HIBERNATE_HDSTAT_ULPWDG_Msk (0x8UL)
6503 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Pos (4UL)
6504 #define SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk (0x10UL)
6506 /* ----------------------------- SCU_HIBERNATE_HDCLR ---------------------------- */
6507 #define SCU_HIBERNATE_HDCLR_EPEV_Pos (0UL)
6508 #define SCU_HIBERNATE_HDCLR_EPEV_Msk (0x1UL)
6509 #define SCU_HIBERNATE_HDCLR_ENEV_Pos (1UL)
6510 #define SCU_HIBERNATE_HDCLR_ENEV_Msk (0x2UL)
6511 #define SCU_HIBERNATE_HDCLR_RTCEV_Pos (2UL)
6512 #define SCU_HIBERNATE_HDCLR_RTCEV_Msk (0x4UL)
6513 #define SCU_HIBERNATE_HDCLR_ULPWDG_Pos (3UL)
6514 #define SCU_HIBERNATE_HDCLR_ULPWDG_Msk (0x8UL)
6516 /* ----------------------------- SCU_HIBERNATE_HDSET ---------------------------- */
6517 #define SCU_HIBERNATE_HDSET_EPEV_Pos (0UL)
6518 #define SCU_HIBERNATE_HDSET_EPEV_Msk (0x1UL)
6519 #define SCU_HIBERNATE_HDSET_ENEV_Pos (1UL)
6520 #define SCU_HIBERNATE_HDSET_ENEV_Msk (0x2UL)
6521 #define SCU_HIBERNATE_HDSET_RTCEV_Pos (2UL)
6522 #define SCU_HIBERNATE_HDSET_RTCEV_Msk (0x4UL)
6523 #define SCU_HIBERNATE_HDSET_ULPWDG_Pos (3UL)
6524 #define SCU_HIBERNATE_HDSET_ULPWDG_Msk (0x8UL)
6526 /* ----------------------------- SCU_HIBERNATE_HDCR ----------------------------- */
6527 #define SCU_HIBERNATE_HDCR_WKPEP_Pos (0UL)
6528 #define SCU_HIBERNATE_HDCR_WKPEP_Msk (0x1UL)
6529 #define SCU_HIBERNATE_HDCR_WKPEN_Pos (1UL)
6530 #define SCU_HIBERNATE_HDCR_WKPEN_Msk (0x2UL)
6531 #define SCU_HIBERNATE_HDCR_RTCE_Pos (2UL)
6532 #define SCU_HIBERNATE_HDCR_RTCE_Msk (0x4UL)
6533 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Pos (3UL)
6534 #define SCU_HIBERNATE_HDCR_ULPWDGEN_Msk (0x8UL)
6535 #define SCU_HIBERNATE_HDCR_HIB_Pos (4UL)
6536 #define SCU_HIBERNATE_HDCR_HIB_Msk (0x10UL)
6537 #define SCU_HIBERNATE_HDCR_RCS_Pos (6UL)
6538 #define SCU_HIBERNATE_HDCR_RCS_Msk (0x40UL)
6539 #define SCU_HIBERNATE_HDCR_STDBYSEL_Pos (7UL)
6540 #define SCU_HIBERNATE_HDCR_STDBYSEL_Msk (0x80UL)
6541 #define SCU_HIBERNATE_HDCR_WKUPSEL_Pos (8UL)
6542 #define SCU_HIBERNATE_HDCR_WKUPSEL_Msk (0x100UL)
6543 #define SCU_HIBERNATE_HDCR_GPI0SEL_Pos (10UL)
6544 #define SCU_HIBERNATE_HDCR_GPI0SEL_Msk (0x400UL)
6545 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Pos (12UL)
6546 #define SCU_HIBERNATE_HDCR_HIBIO0POL_Msk (0x1000UL)
6547 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Pos (13UL)
6548 #define SCU_HIBERNATE_HDCR_HIBIO1POL_Msk (0x2000UL)
6549 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Pos (16UL)
6550 #define SCU_HIBERNATE_HDCR_HIBIO0SEL_Msk (0xf0000UL)
6551 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Pos (20UL)
6552 #define SCU_HIBERNATE_HDCR_HIBIO1SEL_Msk (0xf00000UL)
6554 /* --------------------------- SCU_HIBERNATE_OSCSICTRL -------------------------- */
6555 #define SCU_HIBERNATE_OSCSICTRL_PWD_Pos (0UL)
6556 #define SCU_HIBERNATE_OSCSICTRL_PWD_Msk (0x1UL)
6558 /* --------------------------- SCU_HIBERNATE_OSCULSTAT -------------------------- */
6559 #define SCU_HIBERNATE_OSCULSTAT_X1D_Pos (0UL)
6560 #define SCU_HIBERNATE_OSCULSTAT_X1D_Msk (0x1UL)
6562 /* --------------------------- SCU_HIBERNATE_OSCULCTRL -------------------------- */
6563 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Pos (0UL)
6564 #define SCU_HIBERNATE_OSCULCTRL_X1DEN_Msk (0x1UL)
6565 #define SCU_HIBERNATE_OSCULCTRL_MODE_Pos (4UL)
6566 #define SCU_HIBERNATE_OSCULCTRL_MODE_Msk (0x30UL)
6569 /* ================================================================================ */
6570 /* ================ struct 'SCU_POWER' Position & Mask ================ */
6571 /* ================================================================================ */
6572 
6573 
6574 /* ------------------------------ SCU_POWER_PWRSTAT ----------------------------- */
6575 #define SCU_POWER_PWRSTAT_HIBEN_Pos (0UL)
6576 #define SCU_POWER_PWRSTAT_HIBEN_Msk (0x1UL)
6577 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Pos (16UL)
6578 #define SCU_POWER_PWRSTAT_USBPHYPDQ_Msk (0x10000UL)
6579 #define SCU_POWER_PWRSTAT_USBOTGEN_Pos (17UL)
6580 #define SCU_POWER_PWRSTAT_USBOTGEN_Msk (0x20000UL)
6581 #define SCU_POWER_PWRSTAT_USBPUWQ_Pos (18UL)
6582 #define SCU_POWER_PWRSTAT_USBPUWQ_Msk (0x40000UL)
6584 /* ------------------------------ SCU_POWER_PWRSET ------------------------------ */
6585 #define SCU_POWER_PWRSET_HIB_Pos (0UL)
6586 #define SCU_POWER_PWRSET_HIB_Msk (0x1UL)
6587 #define SCU_POWER_PWRSET_USBPHYPDQ_Pos (16UL)
6588 #define SCU_POWER_PWRSET_USBPHYPDQ_Msk (0x10000UL)
6589 #define SCU_POWER_PWRSET_USBOTGEN_Pos (17UL)
6590 #define SCU_POWER_PWRSET_USBOTGEN_Msk (0x20000UL)
6591 #define SCU_POWER_PWRSET_USBPUWQ_Pos (18UL)
6592 #define SCU_POWER_PWRSET_USBPUWQ_Msk (0x40000UL)
6594 /* ------------------------------ SCU_POWER_PWRCLR ------------------------------ */
6595 #define SCU_POWER_PWRCLR_HIB_Pos (0UL)
6596 #define SCU_POWER_PWRCLR_HIB_Msk (0x1UL)
6597 #define SCU_POWER_PWRCLR_USBPHYPDQ_Pos (16UL)
6598 #define SCU_POWER_PWRCLR_USBPHYPDQ_Msk (0x10000UL)
6599 #define SCU_POWER_PWRCLR_USBOTGEN_Pos (17UL)
6600 #define SCU_POWER_PWRCLR_USBOTGEN_Msk (0x20000UL)
6601 #define SCU_POWER_PWRCLR_USBPUWQ_Pos (18UL)
6602 #define SCU_POWER_PWRCLR_USBPUWQ_Msk (0x40000UL)
6604 /* ------------------------------ SCU_POWER_EVRSTAT ----------------------------- */
6605 #define SCU_POWER_EVRSTAT_OV13_Pos (1UL)
6606 #define SCU_POWER_EVRSTAT_OV13_Msk (0x2UL)
6608 /* ---------------------------- SCU_POWER_EVRVADCSTAT --------------------------- */
6609 #define SCU_POWER_EVRVADCSTAT_VADC13V_Pos (0UL)
6610 #define SCU_POWER_EVRVADCSTAT_VADC13V_Msk (0xffUL)
6611 #define SCU_POWER_EVRVADCSTAT_VADC33V_Pos (8UL)
6612 #define SCU_POWER_EVRVADCSTAT_VADC33V_Msk (0xff00UL)
6614 /* ------------------------------ SCU_POWER_PWRMON ------------------------------ */
6615 #define SCU_POWER_PWRMON_THRS_Pos (0UL)
6616 #define SCU_POWER_PWRMON_THRS_Msk (0xffUL)
6617 #define SCU_POWER_PWRMON_INTV_Pos (8UL)
6618 #define SCU_POWER_PWRMON_INTV_Msk (0xff00UL)
6619 #define SCU_POWER_PWRMON_ENB_Pos (16UL)
6620 #define SCU_POWER_PWRMON_ENB_Msk (0x10000UL)
6623 /* ================================================================================ */
6624 /* ================ struct 'SCU_RESET' Position & Mask ================ */
6625 /* ================================================================================ */
6626 
6627 
6628 /* ------------------------------ SCU_RESET_RSTSTAT ----------------------------- */
6629 #define SCU_RESET_RSTSTAT_RSTSTAT_Pos (0UL)
6630 #define SCU_RESET_RSTSTAT_RSTSTAT_Msk (0xffUL)
6631 #define SCU_RESET_RSTSTAT_HIBWK_Pos (8UL)
6632 #define SCU_RESET_RSTSTAT_HIBWK_Msk (0x100UL)
6633 #define SCU_RESET_RSTSTAT_HIBRS_Pos (9UL)
6634 #define SCU_RESET_RSTSTAT_HIBRS_Msk (0x200UL)
6635 #define SCU_RESET_RSTSTAT_LCKEN_Pos (10UL)
6636 #define SCU_RESET_RSTSTAT_LCKEN_Msk (0x400UL)
6637 #define SCU_RESET_RSTSTAT_ECAT0RS_Pos (12UL)
6638 #define SCU_RESET_RSTSTAT_ECAT0RS_Msk (0x1000UL)
6640 /* ------------------------------ SCU_RESET_RSTSET ------------------------------ */
6641 #define SCU_RESET_RSTSET_HIBWK_Pos (8UL)
6642 #define SCU_RESET_RSTSET_HIBWK_Msk (0x100UL)
6643 #define SCU_RESET_RSTSET_HIBRS_Pos (9UL)
6644 #define SCU_RESET_RSTSET_HIBRS_Msk (0x200UL)
6645 #define SCU_RESET_RSTSET_LCKEN_Pos (10UL)
6646 #define SCU_RESET_RSTSET_LCKEN_Msk (0x400UL)
6647 #define SCU_RESET_RSTSET_ECAT0RS_Pos (12UL)
6648 #define SCU_RESET_RSTSET_ECAT0RS_Msk (0x1000UL)
6650 /* ------------------------------ SCU_RESET_RSTCLR ------------------------------ */
6651 #define SCU_RESET_RSTCLR_RSCLR_Pos (0UL)
6652 #define SCU_RESET_RSTCLR_RSCLR_Msk (0x1UL)
6653 #define SCU_RESET_RSTCLR_HIBWK_Pos (8UL)
6654 #define SCU_RESET_RSTCLR_HIBWK_Msk (0x100UL)
6655 #define SCU_RESET_RSTCLR_HIBRS_Pos (9UL)
6656 #define SCU_RESET_RSTCLR_HIBRS_Msk (0x200UL)
6657 #define SCU_RESET_RSTCLR_LCKEN_Pos (10UL)
6658 #define SCU_RESET_RSTCLR_LCKEN_Msk (0x400UL)
6659 #define SCU_RESET_RSTCLR_ECAT0RS_Pos (12UL)
6660 #define SCU_RESET_RSTCLR_ECAT0RS_Msk (0x1000UL)
6662 /* ------------------------------ SCU_RESET_PRSTAT0 ----------------------------- */
6663 #define SCU_RESET_PRSTAT0_VADCRS_Pos (0UL)
6664 #define SCU_RESET_PRSTAT0_VADCRS_Msk (0x1UL)
6665 #define SCU_RESET_PRSTAT0_DSDRS_Pos (1UL)
6666 #define SCU_RESET_PRSTAT0_DSDRS_Msk (0x2UL)
6667 #define SCU_RESET_PRSTAT0_CCU40RS_Pos (2UL)
6668 #define SCU_RESET_PRSTAT0_CCU40RS_Msk (0x4UL)
6669 #define SCU_RESET_PRSTAT0_CCU41RS_Pos (3UL)
6670 #define SCU_RESET_PRSTAT0_CCU41RS_Msk (0x8UL)
6671 #define SCU_RESET_PRSTAT0_CCU42RS_Pos (4UL)
6672 #define SCU_RESET_PRSTAT0_CCU42RS_Msk (0x10UL)
6673 #define SCU_RESET_PRSTAT0_CCU80RS_Pos (7UL)
6674 #define SCU_RESET_PRSTAT0_CCU80RS_Msk (0x80UL)
6675 #define SCU_RESET_PRSTAT0_CCU81RS_Pos (8UL)
6676 #define SCU_RESET_PRSTAT0_CCU81RS_Msk (0x100UL)
6677 #define SCU_RESET_PRSTAT0_POSIF0RS_Pos (9UL)
6678 #define SCU_RESET_PRSTAT0_POSIF0RS_Msk (0x200UL)
6679 #define SCU_RESET_PRSTAT0_POSIF1RS_Pos (10UL)
6680 #define SCU_RESET_PRSTAT0_POSIF1RS_Msk (0x400UL)
6681 #define SCU_RESET_PRSTAT0_USIC0RS_Pos (11UL)
6682 #define SCU_RESET_PRSTAT0_USIC0RS_Msk (0x800UL)
6683 #define SCU_RESET_PRSTAT0_ERU1RS_Pos (16UL)
6684 #define SCU_RESET_PRSTAT0_ERU1RS_Msk (0x10000UL)
6686 /* ------------------------------ SCU_RESET_PRSET0 ------------------------------ */
6687 #define SCU_RESET_PRSET0_VADCRS_Pos (0UL)
6688 #define SCU_RESET_PRSET0_VADCRS_Msk (0x1UL)
6689 #define SCU_RESET_PRSET0_DSDRS_Pos (1UL)
6690 #define SCU_RESET_PRSET0_DSDRS_Msk (0x2UL)
6691 #define SCU_RESET_PRSET0_CCU40RS_Pos (2UL)
6692 #define SCU_RESET_PRSET0_CCU40RS_Msk (0x4UL)
6693 #define SCU_RESET_PRSET0_CCU41RS_Pos (3UL)
6694 #define SCU_RESET_PRSET0_CCU41RS_Msk (0x8UL)
6695 #define SCU_RESET_PRSET0_CCU42RS_Pos (4UL)
6696 #define SCU_RESET_PRSET0_CCU42RS_Msk (0x10UL)
6697 #define SCU_RESET_PRSET0_CCU80RS_Pos (7UL)
6698 #define SCU_RESET_PRSET0_CCU80RS_Msk (0x80UL)
6699 #define SCU_RESET_PRSET0_CCU81RS_Pos (8UL)
6700 #define SCU_RESET_PRSET0_CCU81RS_Msk (0x100UL)
6701 #define SCU_RESET_PRSET0_POSIF0RS_Pos (9UL)
6702 #define SCU_RESET_PRSET0_POSIF0RS_Msk (0x200UL)
6703 #define SCU_RESET_PRSET0_POSIF1RS_Pos (10UL)
6704 #define SCU_RESET_PRSET0_POSIF1RS_Msk (0x400UL)
6705 #define SCU_RESET_PRSET0_USIC0RS_Pos (11UL)
6706 #define SCU_RESET_PRSET0_USIC0RS_Msk (0x800UL)
6707 #define SCU_RESET_PRSET0_ERU1RS_Pos (16UL)
6708 #define SCU_RESET_PRSET0_ERU1RS_Msk (0x10000UL)
6710 /* ------------------------------ SCU_RESET_PRCLR0 ------------------------------ */
6711 #define SCU_RESET_PRCLR0_VADCRS_Pos (0UL)
6712 #define SCU_RESET_PRCLR0_VADCRS_Msk (0x1UL)
6713 #define SCU_RESET_PRCLR0_DSDRS_Pos (1UL)
6714 #define SCU_RESET_PRCLR0_DSDRS_Msk (0x2UL)
6715 #define SCU_RESET_PRCLR0_CCU40RS_Pos (2UL)
6716 #define SCU_RESET_PRCLR0_CCU40RS_Msk (0x4UL)
6717 #define SCU_RESET_PRCLR0_CCU41RS_Pos (3UL)
6718 #define SCU_RESET_PRCLR0_CCU41RS_Msk (0x8UL)
6719 #define SCU_RESET_PRCLR0_CCU42RS_Pos (4UL)
6720 #define SCU_RESET_PRCLR0_CCU42RS_Msk (0x10UL)
6721 #define SCU_RESET_PRCLR0_CCU80RS_Pos (7UL)
6722 #define SCU_RESET_PRCLR0_CCU80RS_Msk (0x80UL)
6723 #define SCU_RESET_PRCLR0_CCU81RS_Pos (8UL)
6724 #define SCU_RESET_PRCLR0_CCU81RS_Msk (0x100UL)
6725 #define SCU_RESET_PRCLR0_POSIF0RS_Pos (9UL)
6726 #define SCU_RESET_PRCLR0_POSIF0RS_Msk (0x200UL)
6727 #define SCU_RESET_PRCLR0_POSIF1RS_Pos (10UL)
6728 #define SCU_RESET_PRCLR0_POSIF1RS_Msk (0x400UL)
6729 #define SCU_RESET_PRCLR0_USIC0RS_Pos (11UL)
6730 #define SCU_RESET_PRCLR0_USIC0RS_Msk (0x800UL)
6731 #define SCU_RESET_PRCLR0_ERU1RS_Pos (16UL)
6732 #define SCU_RESET_PRCLR0_ERU1RS_Msk (0x10000UL)
6734 /* ------------------------------ SCU_RESET_PRSTAT1 ----------------------------- */
6735 #define SCU_RESET_PRSTAT1_CCU43RS_Pos (0UL)
6736 #define SCU_RESET_PRSTAT1_CCU43RS_Msk (0x1UL)
6737 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Pos (3UL)
6738 #define SCU_RESET_PRSTAT1_LEDTSCU0RS_Msk (0x8UL)
6739 #define SCU_RESET_PRSTAT1_MCAN0RS_Pos (4UL)
6740 #define SCU_RESET_PRSTAT1_MCAN0RS_Msk (0x10UL)
6741 #define SCU_RESET_PRSTAT1_DACRS_Pos (5UL)
6742 #define SCU_RESET_PRSTAT1_DACRS_Msk (0x20UL)
6743 #define SCU_RESET_PRSTAT1_MMCIRS_Pos (6UL)
6744 #define SCU_RESET_PRSTAT1_MMCIRS_Msk (0x40UL)
6745 #define SCU_RESET_PRSTAT1_USIC1RS_Pos (7UL)
6746 #define SCU_RESET_PRSTAT1_USIC1RS_Msk (0x80UL)
6747 #define SCU_RESET_PRSTAT1_USIC2RS_Pos (8UL)
6748 #define SCU_RESET_PRSTAT1_USIC2RS_Msk (0x100UL)
6749 #define SCU_RESET_PRSTAT1_PPORTSRS_Pos (9UL)
6750 #define SCU_RESET_PRSTAT1_PPORTSRS_Msk (0x200UL)
6752 /* ------------------------------ SCU_RESET_PRSET1 ------------------------------ */
6753 #define SCU_RESET_PRSET1_CCU43RS_Pos (0UL)
6754 #define SCU_RESET_PRSET1_CCU43RS_Msk (0x1UL)
6755 #define SCU_RESET_PRSET1_LEDTSCU0RS_Pos (3UL)
6756 #define SCU_RESET_PRSET1_LEDTSCU0RS_Msk (0x8UL)
6757 #define SCU_RESET_PRSET1_MCAN0RS_Pos (4UL)
6758 #define SCU_RESET_PRSET1_MCAN0RS_Msk (0x10UL)
6759 #define SCU_RESET_PRSET1_DACRS_Pos (5UL)
6760 #define SCU_RESET_PRSET1_DACRS_Msk (0x20UL)
6761 #define SCU_RESET_PRSET1_MMCIRS_Pos (6UL)
6762 #define SCU_RESET_PRSET1_MMCIRS_Msk (0x40UL)
6763 #define SCU_RESET_PRSET1_USIC1RS_Pos (7UL)
6764 #define SCU_RESET_PRSET1_USIC1RS_Msk (0x80UL)
6765 #define SCU_RESET_PRSET1_USIC2RS_Pos (8UL)
6766 #define SCU_RESET_PRSET1_USIC2RS_Msk (0x100UL)
6767 #define SCU_RESET_PRSET1_PPORTSRS_Pos (9UL)
6768 #define SCU_RESET_PRSET1_PPORTSRS_Msk (0x200UL)
6770 /* ------------------------------ SCU_RESET_PRCLR1 ------------------------------ */
6771 #define SCU_RESET_PRCLR1_CCU43RS_Pos (0UL)
6772 #define SCU_RESET_PRCLR1_CCU43RS_Msk (0x1UL)
6773 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Pos (3UL)
6774 #define SCU_RESET_PRCLR1_LEDTSCU0RS_Msk (0x8UL)
6775 #define SCU_RESET_PRCLR1_MCAN0RS_Pos (4UL)
6776 #define SCU_RESET_PRCLR1_MCAN0RS_Msk (0x10UL)
6777 #define SCU_RESET_PRCLR1_DACRS_Pos (5UL)
6778 #define SCU_RESET_PRCLR1_DACRS_Msk (0x20UL)
6779 #define SCU_RESET_PRCLR1_MMCIRS_Pos (6UL)
6780 #define SCU_RESET_PRCLR1_MMCIRS_Msk (0x40UL)
6781 #define SCU_RESET_PRCLR1_USIC1RS_Pos (7UL)
6782 #define SCU_RESET_PRCLR1_USIC1RS_Msk (0x80UL)
6783 #define SCU_RESET_PRCLR1_USIC2RS_Pos (8UL)
6784 #define SCU_RESET_PRCLR1_USIC2RS_Msk (0x100UL)
6785 #define SCU_RESET_PRCLR1_PPORTSRS_Pos (9UL)
6786 #define SCU_RESET_PRCLR1_PPORTSRS_Msk (0x200UL)
6788 /* ------------------------------ SCU_RESET_PRSTAT2 ----------------------------- */
6789 #define SCU_RESET_PRSTAT2_WDTRS_Pos (1UL)
6790 #define SCU_RESET_PRSTAT2_WDTRS_Msk (0x2UL)
6791 #define SCU_RESET_PRSTAT2_ETH0RS_Pos (2UL)
6792 #define SCU_RESET_PRSTAT2_ETH0RS_Msk (0x4UL)
6793 #define SCU_RESET_PRSTAT2_DMA0RS_Pos (4UL)
6794 #define SCU_RESET_PRSTAT2_DMA0RS_Msk (0x10UL)
6795 #define SCU_RESET_PRSTAT2_DMA1RS_Pos (5UL)
6796 #define SCU_RESET_PRSTAT2_DMA1RS_Msk (0x20UL)
6797 #define SCU_RESET_PRSTAT2_FCERS_Pos (6UL)
6798 #define SCU_RESET_PRSTAT2_FCERS_Msk (0x40UL)
6799 #define SCU_RESET_PRSTAT2_USBRS_Pos (7UL)
6800 #define SCU_RESET_PRSTAT2_USBRS_Msk (0x80UL)
6801 #define SCU_RESET_PRSTAT2_ECAT0RS_Pos (10UL)
6802 #define SCU_RESET_PRSTAT2_ECAT0RS_Msk (0x400UL)
6804 /* ------------------------------ SCU_RESET_PRSET2 ------------------------------ */
6805 #define SCU_RESET_PRSET2_WDTRS_Pos (1UL)
6806 #define SCU_RESET_PRSET2_WDTRS_Msk (0x2UL)
6807 #define SCU_RESET_PRSET2_ETH0RS_Pos (2UL)
6808 #define SCU_RESET_PRSET2_ETH0RS_Msk (0x4UL)
6809 #define SCU_RESET_PRSET2_DMA0RS_Pos (4UL)
6810 #define SCU_RESET_PRSET2_DMA0RS_Msk (0x10UL)
6811 #define SCU_RESET_PRSET2_DMA1RS_Pos (5UL)
6812 #define SCU_RESET_PRSET2_DMA1RS_Msk (0x20UL)
6813 #define SCU_RESET_PRSET2_FCERS_Pos (6UL)
6814 #define SCU_RESET_PRSET2_FCERS_Msk (0x40UL)
6815 #define SCU_RESET_PRSET2_USBRS_Pos (7UL)
6816 #define SCU_RESET_PRSET2_USBRS_Msk (0x80UL)
6817 #define SCU_RESET_PRSET2_ECAT0RS_Pos (10UL)
6818 #define SCU_RESET_PRSET2_ECAT0RS_Msk (0x400UL)
6820 /* ------------------------------ SCU_RESET_PRCLR2 ------------------------------ */
6821 #define SCU_RESET_PRCLR2_WDTRS_Pos (1UL)
6822 #define SCU_RESET_PRCLR2_WDTRS_Msk (0x2UL)
6823 #define SCU_RESET_PRCLR2_ETH0RS_Pos (2UL)
6824 #define SCU_RESET_PRCLR2_ETH0RS_Msk (0x4UL)
6825 #define SCU_RESET_PRCLR2_DMA0RS_Pos (4UL)
6826 #define SCU_RESET_PRCLR2_DMA0RS_Msk (0x10UL)
6827 #define SCU_RESET_PRCLR2_DMA1RS_Pos (5UL)
6828 #define SCU_RESET_PRCLR2_DMA1RS_Msk (0x20UL)
6829 #define SCU_RESET_PRCLR2_FCERS_Pos (6UL)
6830 #define SCU_RESET_PRCLR2_FCERS_Msk (0x40UL)
6831 #define SCU_RESET_PRCLR2_USBRS_Pos (7UL)
6832 #define SCU_RESET_PRCLR2_USBRS_Msk (0x80UL)
6833 #define SCU_RESET_PRCLR2_ECAT0RS_Pos (10UL)
6834 #define SCU_RESET_PRCLR2_ECAT0RS_Msk (0x400UL)
6836 /* ------------------------------ SCU_RESET_PRSTAT3 ----------------------------- */
6837 #define SCU_RESET_PRSTAT3_EBURS_Pos (2UL)
6838 #define SCU_RESET_PRSTAT3_EBURS_Msk (0x4UL)
6840 /* ------------------------------ SCU_RESET_PRSET3 ------------------------------ */
6841 #define SCU_RESET_PRSET3_EBURS_Pos (2UL)
6842 #define SCU_RESET_PRSET3_EBURS_Msk (0x4UL)
6844 /* ------------------------------ SCU_RESET_PRCLR3 ------------------------------ */
6845 #define SCU_RESET_PRCLR3_EBURS_Pos (2UL)
6846 #define SCU_RESET_PRCLR3_EBURS_Msk (0x4UL)
6849 /* ================================================================================ */
6850 /* ================ Group 'LEDTS' Position & Mask ================ */
6851 /* ================================================================================ */
6852 
6853 
6854 /* ---------------------------------- LEDTS_ID ---------------------------------- */
6855 #define LEDTS_ID_MOD_REV_Pos (0UL)
6856 #define LEDTS_ID_MOD_REV_Msk (0xffUL)
6857 #define LEDTS_ID_MOD_TYPE_Pos (8UL)
6858 #define LEDTS_ID_MOD_TYPE_Msk (0xff00UL)
6859 #define LEDTS_ID_MOD_NUMBER_Pos (16UL)
6860 #define LEDTS_ID_MOD_NUMBER_Msk (0xffff0000UL)
6862 /* -------------------------------- LEDTS_GLOBCTL ------------------------------- */
6863 #define LEDTS_GLOBCTL_TS_EN_Pos (0UL)
6864 #define LEDTS_GLOBCTL_TS_EN_Msk (0x1UL)
6865 #define LEDTS_GLOBCTL_LD_EN_Pos (1UL)
6866 #define LEDTS_GLOBCTL_LD_EN_Msk (0x2UL)
6867 #define LEDTS_GLOBCTL_CMTR_Pos (2UL)
6868 #define LEDTS_GLOBCTL_CMTR_Msk (0x4UL)
6869 #define LEDTS_GLOBCTL_ENSYNC_Pos (3UL)
6870 #define LEDTS_GLOBCTL_ENSYNC_Msk (0x8UL)
6871 #define LEDTS_GLOBCTL_SUSCFG_Pos (8UL)
6872 #define LEDTS_GLOBCTL_SUSCFG_Msk (0x100UL)
6873 #define LEDTS_GLOBCTL_MASKVAL_Pos (9UL)
6874 #define LEDTS_GLOBCTL_MASKVAL_Msk (0xe00UL)
6875 #define LEDTS_GLOBCTL_FENVAL_Pos (12UL)
6876 #define LEDTS_GLOBCTL_FENVAL_Msk (0x1000UL)
6877 #define LEDTS_GLOBCTL_ITS_EN_Pos (13UL)
6878 #define LEDTS_GLOBCTL_ITS_EN_Msk (0x2000UL)
6879 #define LEDTS_GLOBCTL_ITF_EN_Pos (14UL)
6880 #define LEDTS_GLOBCTL_ITF_EN_Msk (0x4000UL)
6881 #define LEDTS_GLOBCTL_ITP_EN_Pos (15UL)
6882 #define LEDTS_GLOBCTL_ITP_EN_Msk (0x8000UL)
6883 #define LEDTS_GLOBCTL_CLK_PS_Pos (16UL)
6884 #define LEDTS_GLOBCTL_CLK_PS_Msk (0xffff0000UL)
6886 /* --------------------------------- LEDTS_FNCTL -------------------------------- */
6887 #define LEDTS_FNCTL_PADT_Pos (0UL)
6888 #define LEDTS_FNCTL_PADT_Msk (0x7UL)
6889 #define LEDTS_FNCTL_PADTSW_Pos (3UL)
6890 #define LEDTS_FNCTL_PADTSW_Msk (0x8UL)
6891 #define LEDTS_FNCTL_EPULL_Pos (4UL)
6892 #define LEDTS_FNCTL_EPULL_Msk (0x10UL)
6893 #define LEDTS_FNCTL_FNCOL_Pos (5UL)
6894 #define LEDTS_FNCTL_FNCOL_Msk (0xe0UL)
6895 #define LEDTS_FNCTL_ACCCNT_Pos (16UL)
6896 #define LEDTS_FNCTL_ACCCNT_Msk (0xf0000UL)
6897 #define LEDTS_FNCTL_TSCCMP_Pos (20UL)
6898 #define LEDTS_FNCTL_TSCCMP_Msk (0x100000UL)
6899 #define LEDTS_FNCTL_TSOEXT_Pos (21UL)
6900 #define LEDTS_FNCTL_TSOEXT_Msk (0x600000UL)
6901 #define LEDTS_FNCTL_TSCTRR_Pos (23UL)
6902 #define LEDTS_FNCTL_TSCTRR_Msk (0x800000UL)
6903 #define LEDTS_FNCTL_TSCTRSAT_Pos (24UL)
6904 #define LEDTS_FNCTL_TSCTRSAT_Msk (0x1000000UL)
6905 #define LEDTS_FNCTL_NR_TSIN_Pos (25UL)
6906 #define LEDTS_FNCTL_NR_TSIN_Msk (0xe000000UL)
6907 #define LEDTS_FNCTL_COLLEV_Pos (28UL)
6908 #define LEDTS_FNCTL_COLLEV_Msk (0x10000000UL)
6909 #define LEDTS_FNCTL_NR_LEDCOL_Pos (29UL)
6910 #define LEDTS_FNCTL_NR_LEDCOL_Msk (0xe0000000UL)
6912 /* --------------------------------- LEDTS_EVFR --------------------------------- */
6913 #define LEDTS_EVFR_TSF_Pos (0UL)
6914 #define LEDTS_EVFR_TSF_Msk (0x1UL)
6915 #define LEDTS_EVFR_TFF_Pos (1UL)
6916 #define LEDTS_EVFR_TFF_Msk (0x2UL)
6917 #define LEDTS_EVFR_TPF_Pos (2UL)
6918 #define LEDTS_EVFR_TPF_Msk (0x4UL)
6919 #define LEDTS_EVFR_TSCTROVF_Pos (3UL)
6920 #define LEDTS_EVFR_TSCTROVF_Msk (0x8UL)
6921 #define LEDTS_EVFR_CTSF_Pos (16UL)
6922 #define LEDTS_EVFR_CTSF_Msk (0x10000UL)
6923 #define LEDTS_EVFR_CTFF_Pos (17UL)
6924 #define LEDTS_EVFR_CTFF_Msk (0x20000UL)
6925 #define LEDTS_EVFR_CTPF_Pos (18UL)
6926 #define LEDTS_EVFR_CTPF_Msk (0x40000UL)
6928 /* --------------------------------- LEDTS_TSVAL -------------------------------- */
6929 #define LEDTS_TSVAL_TSCTRVALR_Pos (0UL)
6930 #define LEDTS_TSVAL_TSCTRVALR_Msk (0xffffUL)
6931 #define LEDTS_TSVAL_TSCTRVAL_Pos (16UL)
6932 #define LEDTS_TSVAL_TSCTRVAL_Msk (0xffff0000UL)
6934 /* --------------------------------- LEDTS_LINE0 -------------------------------- */
6935 #define LEDTS_LINE0_LINE_0_Pos (0UL)
6936 #define LEDTS_LINE0_LINE_0_Msk (0xffUL)
6937 #define LEDTS_LINE0_LINE_1_Pos (8UL)
6938 #define LEDTS_LINE0_LINE_1_Msk (0xff00UL)
6939 #define LEDTS_LINE0_LINE_2_Pos (16UL)
6940 #define LEDTS_LINE0_LINE_2_Msk (0xff0000UL)
6941 #define LEDTS_LINE0_LINE_3_Pos (24UL)
6942 #define LEDTS_LINE0_LINE_3_Msk (0xff000000UL)
6944 /* --------------------------------- LEDTS_LINE1 -------------------------------- */
6945 #define LEDTS_LINE1_LINE_4_Pos (0UL)
6946 #define LEDTS_LINE1_LINE_4_Msk (0xffUL)
6947 #define LEDTS_LINE1_LINE_5_Pos (8UL)
6948 #define LEDTS_LINE1_LINE_5_Msk (0xff00UL)
6949 #define LEDTS_LINE1_LINE_6_Pos (16UL)
6950 #define LEDTS_LINE1_LINE_6_Msk (0xff0000UL)
6951 #define LEDTS_LINE1_LINE_A_Pos (24UL)
6952 #define LEDTS_LINE1_LINE_A_Msk (0xff000000UL)
6954 /* -------------------------------- LEDTS_LDCMP0 -------------------------------- */
6955 #define LEDTS_LDCMP0_CMP_LD0_Pos (0UL)
6956 #define LEDTS_LDCMP0_CMP_LD0_Msk (0xffUL)
6957 #define LEDTS_LDCMP0_CMP_LD1_Pos (8UL)
6958 #define LEDTS_LDCMP0_CMP_LD1_Msk (0xff00UL)
6959 #define LEDTS_LDCMP0_CMP_LD2_Pos (16UL)
6960 #define LEDTS_LDCMP0_CMP_LD2_Msk (0xff0000UL)
6961 #define LEDTS_LDCMP0_CMP_LD3_Pos (24UL)
6962 #define LEDTS_LDCMP0_CMP_LD3_Msk (0xff000000UL)
6964 /* -------------------------------- LEDTS_LDCMP1 -------------------------------- */
6965 #define LEDTS_LDCMP1_CMP_LD4_Pos (0UL)
6966 #define LEDTS_LDCMP1_CMP_LD4_Msk (0xffUL)
6967 #define LEDTS_LDCMP1_CMP_LD5_Pos (8UL)
6968 #define LEDTS_LDCMP1_CMP_LD5_Msk (0xff00UL)
6969 #define LEDTS_LDCMP1_CMP_LD6_Pos (16UL)
6970 #define LEDTS_LDCMP1_CMP_LD6_Msk (0xff0000UL)
6971 #define LEDTS_LDCMP1_CMP_LDA_TSCOM_Pos (24UL)
6972 #define LEDTS_LDCMP1_CMP_LDA_TSCOM_Msk (0xff000000UL)
6974 /* -------------------------------- LEDTS_TSCMP0 -------------------------------- */
6975 #define LEDTS_TSCMP0_CMP_TS0_Pos (0UL)
6976 #define LEDTS_TSCMP0_CMP_TS0_Msk (0xffUL)
6977 #define LEDTS_TSCMP0_CMP_TS1_Pos (8UL)
6978 #define LEDTS_TSCMP0_CMP_TS1_Msk (0xff00UL)
6979 #define LEDTS_TSCMP0_CMP_TS2_Pos (16UL)
6980 #define LEDTS_TSCMP0_CMP_TS2_Msk (0xff0000UL)
6981 #define LEDTS_TSCMP0_CMP_TS3_Pos (24UL)
6982 #define LEDTS_TSCMP0_CMP_TS3_Msk (0xff000000UL)
6984 /* -------------------------------- LEDTS_TSCMP1 -------------------------------- */
6985 #define LEDTS_TSCMP1_CMP_TS4_Pos (0UL)
6986 #define LEDTS_TSCMP1_CMP_TS4_Msk (0xffUL)
6987 #define LEDTS_TSCMP1_CMP_TS5_Pos (8UL)
6988 #define LEDTS_TSCMP1_CMP_TS5_Msk (0xff00UL)
6989 #define LEDTS_TSCMP1_CMP_TS6_Pos (16UL)
6990 #define LEDTS_TSCMP1_CMP_TS6_Msk (0xff0000UL)
6991 #define LEDTS_TSCMP1_CMP_TS7_Pos (24UL)
6992 #define LEDTS_TSCMP1_CMP_TS7_Msk (0xff000000UL)
6995 /* ================================================================================ */
6996 /* ================ struct 'SDMMC' Position & Mask ================ */
6997 /* ================================================================================ */
6998 
6999 
7000 /* ------------------------------ SDMMC_BLOCK_SIZE ------------------------------ */
7001 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Pos (0UL)
7002 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_Msk (0xfffUL)
7003 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Pos (15UL)
7004 #define SDMMC_BLOCK_SIZE_TX_BLOCK_SIZE_12_Msk (0x8000UL)
7006 /* ------------------------------ SDMMC_BLOCK_COUNT ----------------------------- */
7007 #define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Pos (0UL)
7008 #define SDMMC_BLOCK_COUNT_BLOCK_COUNT_Msk (0xffffUL)
7010 /* ------------------------------- SDMMC_ARGUMENT1 ------------------------------ */
7011 #define SDMMC_ARGUMENT1_ARGUMENT1_Pos (0UL)
7012 #define SDMMC_ARGUMENT1_ARGUMENT1_Msk (0xffffffffUL)
7014 /* ----------------------------- SDMMC_TRANSFER_MODE ---------------------------- */
7015 #define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Pos (1UL)
7016 #define SDMMC_TRANSFER_MODE_BLOCK_COUNT_EN_Msk (0x2UL)
7017 #define SDMMC_TRANSFER_MODE_ACMD_EN_Pos (2UL)
7018 #define SDMMC_TRANSFER_MODE_ACMD_EN_Msk (0xcUL)
7019 #define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Pos (4UL)
7020 #define SDMMC_TRANSFER_MODE_TX_DIR_SELECT_Msk (0x10UL)
7021 #define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Pos (5UL)
7022 #define SDMMC_TRANSFER_MODE_MULTI_BLOCK_SELECT_Msk (0x20UL)
7023 #define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Pos (6UL)
7024 #define SDMMC_TRANSFER_MODE_CMD_COMP_ATA_Msk (0x40UL)
7026 /* -------------------------------- SDMMC_COMMAND ------------------------------- */
7027 #define SDMMC_COMMAND_RESP_TYPE_SELECT_Pos (0UL)
7028 #define SDMMC_COMMAND_RESP_TYPE_SELECT_Msk (0x3UL)
7029 #define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Pos (3UL)
7030 #define SDMMC_COMMAND_CMD_CRC_CHECK_EN_Msk (0x8UL)
7031 #define SDMMC_COMMAND_CMD_IND_CHECK_EN_Pos (4UL)
7032 #define SDMMC_COMMAND_CMD_IND_CHECK_EN_Msk (0x10UL)
7033 #define SDMMC_COMMAND_DATA_PRESENT_SELECT_Pos (5UL)
7034 #define SDMMC_COMMAND_DATA_PRESENT_SELECT_Msk (0x20UL)
7035 #define SDMMC_COMMAND_CMD_TYPE_Pos (6UL)
7036 #define SDMMC_COMMAND_CMD_TYPE_Msk (0xc0UL)
7037 #define SDMMC_COMMAND_CMD_IND_Pos (8UL)
7038 #define SDMMC_COMMAND_CMD_IND_Msk (0x3f00UL)
7040 /* ------------------------------- SDMMC_RESPONSE0 ------------------------------ */
7041 #define SDMMC_RESPONSE0_RESPONSE0_Pos (0UL)
7042 #define SDMMC_RESPONSE0_RESPONSE0_Msk (0xffffUL)
7043 #define SDMMC_RESPONSE0_RESPONSE1_Pos (16UL)
7044 #define SDMMC_RESPONSE0_RESPONSE1_Msk (0xffff0000UL)
7046 /* ------------------------------- SDMMC_RESPONSE2 ------------------------------ */
7047 #define SDMMC_RESPONSE2_RESPONSE2_Pos (0UL)
7048 #define SDMMC_RESPONSE2_RESPONSE2_Msk (0xffffUL)
7049 #define SDMMC_RESPONSE2_RESPONSE3_Pos (16UL)
7050 #define SDMMC_RESPONSE2_RESPONSE3_Msk (0xffff0000UL)
7052 /* ------------------------------- SDMMC_RESPONSE4 ------------------------------ */
7053 #define SDMMC_RESPONSE4_RESPONSE4_Pos (0UL)
7054 #define SDMMC_RESPONSE4_RESPONSE4_Msk (0xffffUL)
7055 #define SDMMC_RESPONSE4_RESPONSE5_Pos (16UL)
7056 #define SDMMC_RESPONSE4_RESPONSE5_Msk (0xffff0000UL)
7058 /* ------------------------------- SDMMC_RESPONSE6 ------------------------------ */
7059 #define SDMMC_RESPONSE6_RESPONSE6_Pos (0UL)
7060 #define SDMMC_RESPONSE6_RESPONSE6_Msk (0xffffUL)
7061 #define SDMMC_RESPONSE6_RESPONSE7_Pos (16UL)
7062 #define SDMMC_RESPONSE6_RESPONSE7_Msk (0xffff0000UL)
7064 /* ------------------------------ SDMMC_DATA_BUFFER ----------------------------- */
7065 #define SDMMC_DATA_BUFFER_DATA_BUFFER_Pos (0UL)
7066 #define SDMMC_DATA_BUFFER_DATA_BUFFER_Msk (0xffffffffUL)
7068 /* ----------------------------- SDMMC_PRESENT_STATE ---------------------------- */
7069 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Pos (0UL)
7070 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_CMD_Msk (0x1UL)
7071 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Pos (1UL)
7072 #define SDMMC_PRESENT_STATE_COMMAND_INHIBIT_DAT_Msk (0x2UL)
7073 #define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Pos (2UL)
7074 #define SDMMC_PRESENT_STATE_DAT_LINE_ACTIVE_Msk (0x4UL)
7075 #define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Pos (8UL)
7076 #define SDMMC_PRESENT_STATE_WRITE_TRANSFER_ACTIVE_Msk (0x100UL)
7077 #define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Pos (9UL)
7078 #define SDMMC_PRESENT_STATE_READ_TRANSFER_ACTIVE_Msk (0x200UL)
7079 #define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Pos (10UL)
7080 #define SDMMC_PRESENT_STATE_BUFFER_WRITE_ENABLE_Msk (0x400UL)
7081 #define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Pos (11UL)
7082 #define SDMMC_PRESENT_STATE_BUFFER_READ_ENABLE_Msk (0x800UL)
7083 #define SDMMC_PRESENT_STATE_CARD_INSERTED_Pos (16UL)
7084 #define SDMMC_PRESENT_STATE_CARD_INSERTED_Msk (0x10000UL)
7085 #define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Pos (17UL)
7086 #define SDMMC_PRESENT_STATE_CARD_STATE_STABLE_Msk (0x20000UL)
7087 #define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Pos (18UL)
7088 #define SDMMC_PRESENT_STATE_CARD_DETECT_PIN_LEVEL_Msk (0x40000UL)
7089 #define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Pos (19UL)
7090 #define SDMMC_PRESENT_STATE_WRITE_PROTECT_PIN_LEVEL_Msk (0x80000UL)
7091 #define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Pos (20UL)
7092 #define SDMMC_PRESENT_STATE_DAT_3_0_PIN_LEVEL_Msk (0xf00000UL)
7093 #define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Pos (24UL)
7094 #define SDMMC_PRESENT_STATE_CMD_LINE_LEVEL_Msk (0x1000000UL)
7095 #define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Pos (25UL)
7096 #define SDMMC_PRESENT_STATE_DAT_7_4_PIN_LEVEL_Msk (0x1e000000UL)
7098 /* ------------------------------- SDMMC_HOST_CTRL ------------------------------ */
7099 #define SDMMC_HOST_CTRL_LED_CTRL_Pos (0UL)
7100 #define SDMMC_HOST_CTRL_LED_CTRL_Msk (0x1UL)
7101 #define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Pos (1UL)
7102 #define SDMMC_HOST_CTRL_DATA_TX_WIDTH_Msk (0x2UL)
7103 #define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Pos (2UL)
7104 #define SDMMC_HOST_CTRL_HIGH_SPEED_EN_Msk (0x4UL)
7105 #define SDMMC_HOST_CTRL_SD_8BIT_MODE_Pos (5UL)
7106 #define SDMMC_HOST_CTRL_SD_8BIT_MODE_Msk (0x20UL)
7107 #define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Pos (6UL)
7108 #define SDMMC_HOST_CTRL_CARD_DETECT_TEST_LEVEL_Msk (0x40UL)
7109 #define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Pos (7UL)
7110 #define SDMMC_HOST_CTRL_CARD_DET_SIGNAL_DETECT_Msk (0x80UL)
7112 /* ------------------------------ SDMMC_POWER_CTRL ------------------------------ */
7113 #define SDMMC_POWER_CTRL_SD_BUS_POWER_Pos (0UL)
7114 #define SDMMC_POWER_CTRL_SD_BUS_POWER_Msk (0x1UL)
7115 #define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Pos (1UL)
7116 #define SDMMC_POWER_CTRL_SD_BUS_VOLTAGE_SEL_Msk (0xeUL)
7117 #define SDMMC_POWER_CTRL_HARDWARE_RESET_Pos (4UL)
7118 #define SDMMC_POWER_CTRL_HARDWARE_RESET_Msk (0x10UL)
7120 /* ---------------------------- SDMMC_BLOCK_GAP_CTRL ---------------------------- */
7121 #define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Pos (0UL)
7122 #define SDMMC_BLOCK_GAP_CTRL_STOP_AT_BLOCK_GAP_Msk (0x1UL)
7123 #define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Pos (1UL)
7124 #define SDMMC_BLOCK_GAP_CTRL_CONTINUE_REQ_Msk (0x2UL)
7125 #define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Pos (2UL)
7126 #define SDMMC_BLOCK_GAP_CTRL_READ_WAIT_CTRL_Msk (0x4UL)
7127 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Pos (3UL)
7128 #define SDMMC_BLOCK_GAP_CTRL_INT_AT_BLOCK_GAP_Msk (0x8UL)
7130 /* ------------------------------ SDMMC_WAKEUP_CTRL ----------------------------- */
7131 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Pos (0UL)
7132 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INT_Msk (0x1UL)
7133 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Pos (1UL)
7134 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_INS_Msk (0x2UL)
7135 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Pos (2UL)
7136 #define SDMMC_WAKEUP_CTRL_WAKEUP_EVENT_EN_REM_Msk (0x4UL)
7138 /* ------------------------------ SDMMC_CLOCK_CTRL ------------------------------ */
7139 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Pos (0UL)
7140 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_EN_Msk (0x1UL)
7141 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Pos (1UL)
7142 #define SDMMC_CLOCK_CTRL_INTERNAL_CLOCK_STABLE_Msk (0x2UL)
7143 #define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Pos (2UL)
7144 #define SDMMC_CLOCK_CTRL_SDCLOCK_EN_Msk (0x4UL)
7145 #define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Pos (8UL)
7146 #define SDMMC_CLOCK_CTRL_SDCLK_FREQ_SEL_Msk (0xff00UL)
7148 /* ----------------------------- SDMMC_TIMEOUT_CTRL ----------------------------- */
7149 #define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Pos (0UL)
7150 #define SDMMC_TIMEOUT_CTRL_DAT_TIMEOUT_CNT_VAL_Msk (0xfUL)
7152 /* ------------------------------- SDMMC_SW_RESET ------------------------------- */
7153 #define SDMMC_SW_RESET_SW_RST_ALL_Pos (0UL)
7154 #define SDMMC_SW_RESET_SW_RST_ALL_Msk (0x1UL)
7155 #define SDMMC_SW_RESET_SW_RST_CMD_LINE_Pos (1UL)
7156 #define SDMMC_SW_RESET_SW_RST_CMD_LINE_Msk (0x2UL)
7157 #define SDMMC_SW_RESET_SW_RST_DAT_LINE_Pos (2UL)
7158 #define SDMMC_SW_RESET_SW_RST_DAT_LINE_Msk (0x4UL)
7160 /* ---------------------------- SDMMC_INT_STATUS_NORM --------------------------- */
7161 #define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Pos (0UL)
7162 #define SDMMC_INT_STATUS_NORM_CMD_COMPLETE_Msk (0x1UL)
7163 #define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Pos (1UL)
7164 #define SDMMC_INT_STATUS_NORM_TX_COMPLETE_Msk (0x2UL)
7165 #define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Pos (2UL)
7166 #define SDMMC_INT_STATUS_NORM_BLOCK_GAP_EVENT_Msk (0x4UL)
7167 #define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Pos (4UL)
7168 #define SDMMC_INT_STATUS_NORM_BUFF_WRITE_READY_Msk (0x10UL)
7169 #define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Pos (5UL)
7170 #define SDMMC_INT_STATUS_NORM_BUFF_READ_READY_Msk (0x20UL)
7171 #define SDMMC_INT_STATUS_NORM_CARD_INS_Pos (6UL)
7172 #define SDMMC_INT_STATUS_NORM_CARD_INS_Msk (0x40UL)
7173 #define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Pos (7UL)
7174 #define SDMMC_INT_STATUS_NORM_CARD_REMOVAL_Msk (0x80UL)
7175 #define SDMMC_INT_STATUS_NORM_CARD_INT_Pos (8UL)
7176 #define SDMMC_INT_STATUS_NORM_CARD_INT_Msk (0x100UL)
7177 #define SDMMC_INT_STATUS_NORM_ERR_INT_Pos (15UL)
7178 #define SDMMC_INT_STATUS_NORM_ERR_INT_Msk (0x8000UL)
7180 /* ---------------------------- SDMMC_INT_STATUS_ERR ---------------------------- */
7181 #define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Pos (0UL)
7182 #define SDMMC_INT_STATUS_ERR_CMD_TIMEOUT_ERR_Msk (0x1UL)
7183 #define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Pos (1UL)
7184 #define SDMMC_INT_STATUS_ERR_CMD_CRC_ERR_Msk (0x2UL)
7185 #define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Pos (2UL)
7186 #define SDMMC_INT_STATUS_ERR_CMD_END_BIT_ERR_Msk (0x4UL)
7187 #define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Pos (3UL)
7188 #define SDMMC_INT_STATUS_ERR_CMD_IND_ERR_Msk (0x8UL)
7189 #define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Pos (4UL)
7190 #define SDMMC_INT_STATUS_ERR_DATA_TIMEOUT_ERR_Msk (0x10UL)
7191 #define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Pos (5UL)
7192 #define SDMMC_INT_STATUS_ERR_DATA_CRC_ERR_Msk (0x20UL)
7193 #define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Pos (6UL)
7194 #define SDMMC_INT_STATUS_ERR_DATA_END_BIT_ERR_Msk (0x40UL)
7195 #define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Pos (7UL)
7196 #define SDMMC_INT_STATUS_ERR_CURRENT_LIMIT_ERR_Msk (0x80UL)
7197 #define SDMMC_INT_STATUS_ERR_ACMD_ERR_Pos (8UL)
7198 #define SDMMC_INT_STATUS_ERR_ACMD_ERR_Msk (0x100UL)
7199 #define SDMMC_INT_STATUS_ERR_CEATA_ERR_Pos (13UL)
7200 #define SDMMC_INT_STATUS_ERR_CEATA_ERR_Msk (0x2000UL)
7202 /* -------------------------- SDMMC_EN_INT_STATUS_NORM -------------------------- */
7203 #define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Pos (0UL)
7204 #define SDMMC_EN_INT_STATUS_NORM_CMD_COMPLETE_EN_Msk (0x1UL)
7205 #define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Pos (1UL)
7206 #define SDMMC_EN_INT_STATUS_NORM_TX_COMPLETE_EN_Msk (0x2UL)
7207 #define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Pos (2UL)
7208 #define SDMMC_EN_INT_STATUS_NORM_BLOCK_GAP_EVENT_EN_Msk (0x4UL)
7209 #define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Pos (4UL)
7210 #define SDMMC_EN_INT_STATUS_NORM_BUFF_WRITE_READY_EN_Msk (0x10UL)
7211 #define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Pos (5UL)
7212 #define SDMMC_EN_INT_STATUS_NORM_BUFF_READ_READY_EN_Msk (0x20UL)
7213 #define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Pos (6UL)
7214 #define SDMMC_EN_INT_STATUS_NORM_CARD_INS_EN_Msk (0x40UL)
7215 #define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Pos (7UL)
7216 #define SDMMC_EN_INT_STATUS_NORM_CARD_REMOVAL_EN_Msk (0x80UL)
7217 #define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Pos (8UL)
7218 #define SDMMC_EN_INT_STATUS_NORM_CARD_INT_EN_Msk (0x100UL)
7219 #define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Pos (15UL)
7220 #define SDMMC_EN_INT_STATUS_NORM_FIXED_TO_0_Msk (0x8000UL)
7222 /* --------------------------- SDMMC_EN_INT_STATUS_ERR -------------------------- */
7223 #define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Pos (0UL)
7224 #define SDMMC_EN_INT_STATUS_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x1UL)
7225 #define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Pos (1UL)
7226 #define SDMMC_EN_INT_STATUS_ERR_CMD_CRC_ERR_EN_Msk (0x2UL)
7227 #define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Pos (2UL)
7228 #define SDMMC_EN_INT_STATUS_ERR_CMD_END_BIT_ERR_EN_Msk (0x4UL)
7229 #define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Pos (3UL)
7230 #define SDMMC_EN_INT_STATUS_ERR_CMD_IND_ERR_EN_Msk (0x8UL)
7231 #define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Pos (4UL)
7232 #define SDMMC_EN_INT_STATUS_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x10UL)
7233 #define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Pos (5UL)
7234 #define SDMMC_EN_INT_STATUS_ERR_DATA_CRC_ERR_EN_Msk (0x20UL)
7235 #define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Pos (6UL)
7236 #define SDMMC_EN_INT_STATUS_ERR_DATA_END_BIT_ERR_EN_Msk (0x40UL)
7237 #define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Pos (7UL)
7238 #define SDMMC_EN_INT_STATUS_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x80UL)
7239 #define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Pos (8UL)
7240 #define SDMMC_EN_INT_STATUS_ERR_ACMD_ERR_EN_Msk (0x100UL)
7241 #define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Pos (12UL)
7242 #define SDMMC_EN_INT_STATUS_ERR_TARGET_RESP_ERR_EN_Msk (0x1000UL)
7243 #define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Pos (13UL)
7244 #define SDMMC_EN_INT_STATUS_ERR_CEATA_ERR_EN_Msk (0x2000UL)
7246 /* -------------------------- SDMMC_EN_INT_SIGNAL_NORM -------------------------- */
7247 #define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Pos (0UL)
7248 #define SDMMC_EN_INT_SIGNAL_NORM_CMD_COMPLETE_EN_Msk (0x1UL)
7249 #define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Pos (1UL)
7250 #define SDMMC_EN_INT_SIGNAL_NORM_TX_COMPLETE_EN_Msk (0x2UL)
7251 #define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Pos (2UL)
7252 #define SDMMC_EN_INT_SIGNAL_NORM_BLOCK_GAP_EVENT_EN_Msk (0x4UL)
7253 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Pos (4UL)
7254 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_WRITE_READY_EN_Msk (0x10UL)
7255 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Pos (5UL)
7256 #define SDMMC_EN_INT_SIGNAL_NORM_BUFF_READ_READY_EN_Msk (0x20UL)
7257 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Pos (6UL)
7258 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INS_EN_Msk (0x40UL)
7259 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Pos (7UL)
7260 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_REMOVAL_EN_Msk (0x80UL)
7261 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Pos (8UL)
7262 #define SDMMC_EN_INT_SIGNAL_NORM_CARD_INT_EN_Msk (0x100UL)
7263 #define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Pos (15UL)
7264 #define SDMMC_EN_INT_SIGNAL_NORM_FIXED_TO_0_Msk (0x8000UL)
7266 /* --------------------------- SDMMC_EN_INT_SIGNAL_ERR -------------------------- */
7267 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Pos (0UL)
7268 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_TIMEOUT_ERR_EN_Msk (0x1UL)
7269 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Pos (1UL)
7270 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_CRC_ERR_EN_Msk (0x2UL)
7271 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Pos (2UL)
7272 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_END_BIT_ERR_EN_Msk (0x4UL)
7273 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Pos (3UL)
7274 #define SDMMC_EN_INT_SIGNAL_ERR_CMD_IND_ERR_EN_Msk (0x8UL)
7275 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Pos (4UL)
7276 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_TIMEOUT_ERR_EN_Msk (0x10UL)
7277 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Pos (5UL)
7278 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_CRC_ERR_EN_Msk (0x20UL)
7279 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Pos (6UL)
7280 #define SDMMC_EN_INT_SIGNAL_ERR_DATA_END_BIT_ERR_EN_Msk (0x40UL)
7281 #define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Pos (7UL)
7282 #define SDMMC_EN_INT_SIGNAL_ERR_CURRENT_LIMIT_ERR_EN_Msk (0x80UL)
7283 #define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Pos (8UL)
7284 #define SDMMC_EN_INT_SIGNAL_ERR_ACMD_ERR_EN_Msk (0x100UL)
7285 #define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Pos (12UL)
7286 #define SDMMC_EN_INT_SIGNAL_ERR_TARGET_RESP_ERR_EN_Msk (0x1000UL)
7287 #define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Pos (13UL)
7288 #define SDMMC_EN_INT_SIGNAL_ERR_CEATA_ERR_EN_Msk (0x2000UL)
7290 /* ---------------------------- SDMMC_ACMD_ERR_STATUS --------------------------- */
7291 #define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Pos (0UL)
7292 #define SDMMC_ACMD_ERR_STATUS_ACMD12_NOT_EXEC_ERR_Msk (0x1UL)
7293 #define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Pos (1UL)
7294 #define SDMMC_ACMD_ERR_STATUS_ACMD_TIMEOUT_ERR_Msk (0x2UL)
7295 #define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Pos (2UL)
7296 #define SDMMC_ACMD_ERR_STATUS_ACMD_CRC_ERR_Msk (0x4UL)
7297 #define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Pos (3UL)
7298 #define SDMMC_ACMD_ERR_STATUS_ACMD_END_BIT_ERR_Msk (0x8UL)
7299 #define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Pos (4UL)
7300 #define SDMMC_ACMD_ERR_STATUS_ACMD_IND_ERR_Msk (0x10UL)
7301 #define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Pos (7UL)
7302 #define SDMMC_ACMD_ERR_STATUS_CMD_NOT_ISSUED_BY_ACMD12_ERR_Msk (0x80UL)
7304 /* ----------------------------- SDMMC_CAPABILITIES ----------------------------- */
7305 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_FREQ_Pos (0UL)
7306 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_FREQ_Msk (0x3fUL)
7307 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_UNIT_Pos (7UL)
7308 #define SDMMC_CAPABILITIES_TIMEOUT_CLOCK_UNIT_Msk (0x80UL)
7309 #define SDMMC_CAPABILITIES_BASE_SD_CLOCK_FREQ_Pos (8UL)
7310 #define SDMMC_CAPABILITIES_BASE_SD_CLOCK_FREQ_Msk (0xff00UL)
7311 #define SDMMC_CAPABILITIES_MAX_BLOCK_LENGTH_Pos (16UL)
7312 #define SDMMC_CAPABILITIES_MAX_BLOCK_LENGTH_Msk (0x30000UL)
7313 #define SDMMC_CAPABILITIES_EXT_MEDIA_BUS_SUPPORT_Pos (18UL)
7314 #define SDMMC_CAPABILITIES_EXT_MEDIA_BUS_SUPPORT_Msk (0x40000UL)
7315 #define SDMMC_CAPABILITIES_ADMA2_SUPPORT_Pos (19UL)
7316 #define SDMMC_CAPABILITIES_ADMA2_SUPPORT_Msk (0x80000UL)
7317 #define SDMMC_CAPABILITIES_HIGH_SPEED_SUPPORT_Pos (21UL)
7318 #define SDMMC_CAPABILITIES_HIGH_SPEED_SUPPORT_Msk (0x200000UL)
7319 #define SDMMC_CAPABILITIES_SDMA_SUPPORT_Pos (22UL)
7320 #define SDMMC_CAPABILITIES_SDMA_SUPPORT_Msk (0x400000UL)
7321 #define SDMMC_CAPABILITIES_SUSPEND_RESUME_SUPPORT_Pos (23UL)
7322 #define SDMMC_CAPABILITIES_SUSPEND_RESUME_SUPPORT_Msk (0x800000UL)
7323 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3_3V_Pos (24UL)
7324 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3_3V_Msk (0x1000000UL)
7325 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3V_Pos (25UL)
7326 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_3V_Msk (0x2000000UL)
7327 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_1_8V_Pos (26UL)
7328 #define SDMMC_CAPABILITIES_VOLTAGE_SUPPORT_1_8V_Msk (0x4000000UL)
7329 #define SDMMC_CAPABILITIES_SYSBUS_64_SUPPORT_Pos (28UL)
7330 #define SDMMC_CAPABILITIES_SYSBUS_64_SUPPORT_Msk (0x10000000UL)
7331 #define SDMMC_CAPABILITIES_ASYNC_INT_SUPPORT_Pos (29UL)
7332 #define SDMMC_CAPABILITIES_ASYNC_INT_SUPPORT_Msk (0x20000000UL)
7333 #define SDMMC_CAPABILITIES_SLOT_TYPE_Pos (30UL)
7334 #define SDMMC_CAPABILITIES_SLOT_TYPE_Msk (0xc0000000UL)
7336 /* ---------------------------- SDMMC_CAPABILITIES_HI --------------------------- */
7337 #define SDMMC_CAPABILITIES_HI_SDR50_SUPPORT_Pos (0UL)
7338 #define SDMMC_CAPABILITIES_HI_SDR50_SUPPORT_Msk (0x1UL)
7339 #define SDMMC_CAPABILITIES_HI_SDR104_SUPPORT_Pos (1UL)
7340 #define SDMMC_CAPABILITIES_HI_SDR104_SUPPORT_Msk (0x2UL)
7341 #define SDMMC_CAPABILITIES_HI_DDR50_SUPPORT_Pos (2UL)
7342 #define SDMMC_CAPABILITIES_HI_DDR50_SUPPORT_Msk (0x4UL)
7343 #define SDMMC_CAPABILITIES_HI_DRV_A_SUPPORT_Pos (4UL)
7344 #define SDMMC_CAPABILITIES_HI_DRV_A_SUPPORT_Msk (0x10UL)
7345 #define SDMMC_CAPABILITIES_HI_DRV_C_SUPPORT_Pos (5UL)
7346 #define SDMMC_CAPABILITIES_HI_DRV_C_SUPPORT_Msk (0x20UL)
7347 #define SDMMC_CAPABILITIES_HI_DRV_D_SUPPORT_Pos (6UL)
7348 #define SDMMC_CAPABILITIES_HI_DRV_D_SUPPORT_Msk (0x40UL)
7349 #define SDMMC_CAPABILITIES_HI_TIM_CNT_RETUNE_Pos (8UL)
7350 #define SDMMC_CAPABILITIES_HI_TIM_CNT_RETUNE_Msk (0xf00UL)
7351 #define SDMMC_CAPABILITIES_HI_USE_TUNING_SDR50_Pos (13UL)
7352 #define SDMMC_CAPABILITIES_HI_USE_TUNING_SDR50_Msk (0x2000UL)
7353 #define SDMMC_CAPABILITIES_HI_RE_TUNING_MODES_Pos (14UL)
7354 #define SDMMC_CAPABILITIES_HI_RE_TUNING_MODES_Msk (0xc000UL)
7355 #define SDMMC_CAPABILITIES_HI_CLK_MULT_Pos (16UL)
7356 #define SDMMC_CAPABILITIES_HI_CLK_MULT_Msk (0xff0000UL)
7358 /* ---------------------------- SDMMC_MAX_CURRENT_CAP --------------------------- */
7359 #define SDMMC_MAX_CURRENT_CAP_MAX_CURRENT_FOR_3_3V_Pos (0UL)
7360 #define SDMMC_MAX_CURRENT_CAP_MAX_CURRENT_FOR_3_3V_Msk (0xffUL)
7362 /* ---------------------- SDMMC_FORCE_EVENT_ACMD_ERR_STATUS --------------------- */
7363 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Pos (0UL)
7364 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_NOT_EXEC_Msk (0x1UL)
7365 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Pos (1UL)
7366 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_TIMEOUT_ERR_Msk (0x2UL)
7367 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Pos (2UL)
7368 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_CRC_ERR_Msk (0x4UL)
7369 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Pos (3UL)
7370 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_END_BIT_ERR_Msk (0x8UL)
7371 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Pos (4UL)
7372 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_ACMD_IND_ERR_Msk (0x10UL)
7373 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Pos (7UL)
7374 #define SDMMC_FORCE_EVENT_ACMD_ERR_STATUS_FE_CMD_NOT_ISSUED_ACMD12_ERR_Msk (0x80UL)
7376 /* ------------------------ SDMMC_FORCE_EVENT_ERR_STATUS ------------------------ */
7377 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Pos (0UL)
7378 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_TIMEOUT_ERR_Msk (0x1UL)
7379 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Pos (1UL)
7380 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_CRC_ERR_Msk (0x2UL)
7381 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Pos (2UL)
7382 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_END_BIT_ERR_Msk (0x4UL)
7383 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Pos (3UL)
7384 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CMD_IND_ERR_Msk (0x8UL)
7385 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Pos (4UL)
7386 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_TIMEOUT_ERR_Msk (0x10UL)
7387 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Pos (5UL)
7388 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_CRC_ERR_Msk (0x20UL)
7389 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Pos (6UL)
7390 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_DATA_END_BIT_ERR_Msk (0x40UL)
7391 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Pos (7UL)
7392 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CURRENT_LIMIT_ERR_Msk (0x80UL)
7393 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Pos (8UL)
7394 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_ACMD12_ERR_Msk (0x100UL)
7395 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Pos (12UL)
7396 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_TARGET_RESPONSE_ERR_Msk (0x1000UL)
7397 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Pos (13UL)
7398 #define SDMMC_FORCE_EVENT_ERR_STATUS_FE_CEATA_ERR_Msk (0x2000UL)
7400 /* ------------------------------- SDMMC_DEBUG_SEL ------------------------------ */
7401 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Pos (0UL)
7402 #define SDMMC_DEBUG_SEL_DEBUG_SEL_Msk (0x1UL)
7404 /* ---------------------------- SDMMC_SLOT_INT_STATUS --------------------------- */
7405 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Pos (0UL)
7406 #define SDMMC_SLOT_INT_STATUS_SLOT_INT_STATUS_Msk (0xffUL)
7409 /* ================================================================================ */
7410 /* ================ struct 'EBU' Position & Mask ================ */
7411 /* ================================================================================ */
7412 
7413 
7414 /* ----------------------------------- EBU_CLC ---------------------------------- */
7415 #define EBU_CLC_DISR_Pos (0UL)
7416 #define EBU_CLC_DISR_Msk (0x1UL)
7417 #define EBU_CLC_DISS_Pos (1UL)
7418 #define EBU_CLC_DISS_Msk (0x2UL)
7419 #define EBU_CLC_SYNC_Pos (16UL)
7420 #define EBU_CLC_SYNC_Msk (0x10000UL)
7421 #define EBU_CLC_DIV2_Pos (17UL)
7422 #define EBU_CLC_DIV2_Msk (0x20000UL)
7423 #define EBU_CLC_EBUDIV_Pos (18UL)
7424 #define EBU_CLC_EBUDIV_Msk (0xc0000UL)
7425 #define EBU_CLC_SYNCACK_Pos (20UL)
7426 #define EBU_CLC_SYNCACK_Msk (0x100000UL)
7427 #define EBU_CLC_DIV2ACK_Pos (21UL)
7428 #define EBU_CLC_DIV2ACK_Msk (0x200000UL)
7429 #define EBU_CLC_EBUDIVACK_Pos (22UL)
7430 #define EBU_CLC_EBUDIVACK_Msk (0xc00000UL)
7432 /* --------------------------------- EBU_MODCON --------------------------------- */
7433 #define EBU_MODCON_STS_Pos (0UL)
7434 #define EBU_MODCON_STS_Msk (0x1UL)
7435 #define EBU_MODCON_LCKABRT_Pos (1UL)
7436 #define EBU_MODCON_LCKABRT_Msk (0x2UL)
7437 #define EBU_MODCON_SDTRI_Pos (2UL)
7438 #define EBU_MODCON_SDTRI_Msk (0x4UL)
7439 #define EBU_MODCON_EXTLOCK_Pos (4UL)
7440 #define EBU_MODCON_EXTLOCK_Msk (0x10UL)
7441 #define EBU_MODCON_ARBSYNC_Pos (5UL)
7442 #define EBU_MODCON_ARBSYNC_Msk (0x20UL)
7443 #define EBU_MODCON_ARBMODE_Pos (6UL)
7444 #define EBU_MODCON_ARBMODE_Msk (0xc0UL)
7445 #define EBU_MODCON_TIMEOUTC_Pos (8UL)
7446 #define EBU_MODCON_TIMEOUTC_Msk (0xff00UL)
7447 #define EBU_MODCON_LOCKTIMEOUT_Pos (16UL)
7448 #define EBU_MODCON_LOCKTIMEOUT_Msk (0xff0000UL)
7449 #define EBU_MODCON_GLOBALCS_Pos (24UL)
7450 #define EBU_MODCON_GLOBALCS_Msk (0xf000000UL)
7451 #define EBU_MODCON_ACCSINH_Pos (28UL)
7452 #define EBU_MODCON_ACCSINH_Msk (0x10000000UL)
7453 #define EBU_MODCON_ACCSINHACK_Pos (29UL)
7454 #define EBU_MODCON_ACCSINHACK_Msk (0x20000000UL)
7455 #define EBU_MODCON_ALE_Pos (31UL)
7456 #define EBU_MODCON_ALE_Msk (0x80000000UL)
7458 /* ----------------------------------- EBU_ID ----------------------------------- */
7459 #define EBU_ID_MOD_REV_Pos (0UL)
7460 #define EBU_ID_MOD_REV_Msk (0xffUL)
7461 #define EBU_ID_MOD_TYPE_Pos (8UL)
7462 #define EBU_ID_MOD_TYPE_Msk (0xff00UL)
7463 #define EBU_ID_MOD_NUMBER_Pos (16UL)
7464 #define EBU_ID_MOD_NUMBER_Msk (0xffff0000UL)
7466 /* --------------------------------- EBU_USERCON -------------------------------- */
7467 #define EBU_USERCON_DIP_Pos (0UL)
7468 #define EBU_USERCON_DIP_Msk (0x1UL)
7469 #define EBU_USERCON_ADDIO_Pos (16UL)
7470 #define EBU_USERCON_ADDIO_Msk (0x1ff0000UL)
7471 #define EBU_USERCON_ADVIO_Pos (25UL)
7472 #define EBU_USERCON_ADVIO_Msk (0x2000000UL)
7474 /* -------------------------------- EBU_ADDRSEL0 -------------------------------- */
7475 #define EBU_ADDRSEL0_REGENAB_Pos (0UL)
7476 #define EBU_ADDRSEL0_REGENAB_Msk (0x1UL)
7477 #define EBU_ADDRSEL0_ALTENAB_Pos (1UL)
7478 #define EBU_ADDRSEL0_ALTENAB_Msk (0x2UL)
7479 #define EBU_ADDRSEL0_WPROT_Pos (2UL)
7480 #define EBU_ADDRSEL0_WPROT_Msk (0x4UL)
7482 /* -------------------------------- EBU_ADDRSEL1 -------------------------------- */
7483 #define EBU_ADDRSEL1_REGENAB_Pos (0UL)
7484 #define EBU_ADDRSEL1_REGENAB_Msk (0x1UL)
7485 #define EBU_ADDRSEL1_ALTENAB_Pos (1UL)
7486 #define EBU_ADDRSEL1_ALTENAB_Msk (0x2UL)
7487 #define EBU_ADDRSEL1_WPROT_Pos (2UL)
7488 #define EBU_ADDRSEL1_WPROT_Msk (0x4UL)
7490 /* -------------------------------- EBU_ADDRSEL2 -------------------------------- */
7491 #define EBU_ADDRSEL2_REGENAB_Pos (0UL)
7492 #define EBU_ADDRSEL2_REGENAB_Msk (0x1UL)
7493 #define EBU_ADDRSEL2_ALTENAB_Pos (1UL)
7494 #define EBU_ADDRSEL2_ALTENAB_Msk (0x2UL)
7495 #define EBU_ADDRSEL2_WPROT_Pos (2UL)
7496 #define EBU_ADDRSEL2_WPROT_Msk (0x4UL)
7498 /* -------------------------------- EBU_ADDRSEL3 -------------------------------- */
7499 #define EBU_ADDRSEL3_REGENAB_Pos (0UL)
7500 #define EBU_ADDRSEL3_REGENAB_Msk (0x1UL)
7501 #define EBU_ADDRSEL3_ALTENAB_Pos (1UL)
7502 #define EBU_ADDRSEL3_ALTENAB_Msk (0x2UL)
7503 #define EBU_ADDRSEL3_WPROT_Pos (2UL)
7504 #define EBU_ADDRSEL3_WPROT_Msk (0x4UL)
7506 /* -------------------------------- EBU_BUSRCON0 -------------------------------- */
7507 #define EBU_BUSRCON0_FETBLEN_Pos (0UL)
7508 #define EBU_BUSRCON0_FETBLEN_Msk (0x7UL)
7509 #define EBU_BUSRCON0_FBBMSEL_Pos (3UL)
7510 #define EBU_BUSRCON0_FBBMSEL_Msk (0x8UL)
7511 #define EBU_BUSRCON0_BFSSS_Pos (4UL)
7512 #define EBU_BUSRCON0_BFSSS_Msk (0x10UL)
7513 #define EBU_BUSRCON0_FDBKEN_Pos (5UL)
7514 #define EBU_BUSRCON0_FDBKEN_Msk (0x20UL)
7515 #define EBU_BUSRCON0_BFCMSEL_Pos (6UL)
7516 #define EBU_BUSRCON0_BFCMSEL_Msk (0x40UL)
7517 #define EBU_BUSRCON0_NAA_Pos (7UL)
7518 #define EBU_BUSRCON0_NAA_Msk (0x80UL)
7519 #define EBU_BUSRCON0_ECSE_Pos (16UL)
7520 #define EBU_BUSRCON0_ECSE_Msk (0x10000UL)
7521 #define EBU_BUSRCON0_EBSE_Pos (17UL)
7522 #define EBU_BUSRCON0_EBSE_Msk (0x20000UL)
7523 #define EBU_BUSRCON0_DBA_Pos (18UL)
7524 #define EBU_BUSRCON0_DBA_Msk (0x40000UL)
7525 #define EBU_BUSRCON0_WAITINV_Pos (19UL)
7526 #define EBU_BUSRCON0_WAITINV_Msk (0x80000UL)
7527 #define EBU_BUSRCON0_BCGEN_Pos (20UL)
7528 #define EBU_BUSRCON0_BCGEN_Msk (0x300000UL)
7529 #define EBU_BUSRCON0_PORTW_Pos (22UL)
7530 #define EBU_BUSRCON0_PORTW_Msk (0xc00000UL)
7531 #define EBU_BUSRCON0_WAIT_Pos (24UL)
7532 #define EBU_BUSRCON0_WAIT_Msk (0x3000000UL)
7533 #define EBU_BUSRCON0_AAP_Pos (26UL)
7534 #define EBU_BUSRCON0_AAP_Msk (0x4000000UL)
7535 #define EBU_BUSRCON0_AGEN_Pos (28UL)
7536 #define EBU_BUSRCON0_AGEN_Msk (0xf0000000UL)
7538 /* --------------------------------- EBU_BUSRAP0 -------------------------------- */
7539 #define EBU_BUSRAP0_RDDTACS_Pos (0UL)
7540 #define EBU_BUSRAP0_RDDTACS_Msk (0xfUL)
7541 #define EBU_BUSRAP0_RDRECOVC_Pos (4UL)
7542 #define EBU_BUSRAP0_RDRECOVC_Msk (0x70UL)
7543 #define EBU_BUSRAP0_WAITRDC_Pos (7UL)
7544 #define EBU_BUSRAP0_WAITRDC_Msk (0xf80UL)
7545 #define EBU_BUSRAP0_DATAC_Pos (12UL)
7546 #define EBU_BUSRAP0_DATAC_Msk (0xf000UL)
7547 #define EBU_BUSRAP0_EXTCLOCK_Pos (16UL)
7548 #define EBU_BUSRAP0_EXTCLOCK_Msk (0x30000UL)
7549 #define EBU_BUSRAP0_EXTDATA_Pos (18UL)
7550 #define EBU_BUSRAP0_EXTDATA_Msk (0xc0000UL)
7551 #define EBU_BUSRAP0_CMDDELAY_Pos (20UL)
7552 #define EBU_BUSRAP0_CMDDELAY_Msk (0xf00000UL)
7553 #define EBU_BUSRAP0_AHOLDC_Pos (24UL)
7554 #define EBU_BUSRAP0_AHOLDC_Msk (0xf000000UL)
7555 #define EBU_BUSRAP0_ADDRC_Pos (28UL)
7556 #define EBU_BUSRAP0_ADDRC_Msk (0xf0000000UL)
7558 /* -------------------------------- EBU_BUSWCON0 -------------------------------- */
7559 #define EBU_BUSWCON0_FETBLEN_Pos (0UL)
7560 #define EBU_BUSWCON0_FETBLEN_Msk (0x7UL)
7561 #define EBU_BUSWCON0_FBBMSEL_Pos (3UL)
7562 #define EBU_BUSWCON0_FBBMSEL_Msk (0x8UL)
7563 #define EBU_BUSWCON0_NAA_Pos (7UL)
7564 #define EBU_BUSWCON0_NAA_Msk (0x80UL)
7565 #define EBU_BUSWCON0_ECSE_Pos (16UL)
7566 #define EBU_BUSWCON0_ECSE_Msk (0x10000UL)
7567 #define EBU_BUSWCON0_EBSE_Pos (17UL)
7568 #define EBU_BUSWCON0_EBSE_Msk (0x20000UL)
7569 #define EBU_BUSWCON0_WAITINV_Pos (19UL)
7570 #define EBU_BUSWCON0_WAITINV_Msk (0x80000UL)
7571 #define EBU_BUSWCON0_BCGEN_Pos (20UL)
7572 #define EBU_BUSWCON0_BCGEN_Msk (0x300000UL)
7573 #define EBU_BUSWCON0_PORTW_Pos (22UL)
7574 #define EBU_BUSWCON0_PORTW_Msk (0xc00000UL)
7575 #define EBU_BUSWCON0_WAIT_Pos (24UL)
7576 #define EBU_BUSWCON0_WAIT_Msk (0x3000000UL)
7577 #define EBU_BUSWCON0_AAP_Pos (26UL)
7578 #define EBU_BUSWCON0_AAP_Msk (0x4000000UL)
7579 #define EBU_BUSWCON0_LOCKCS_Pos (27UL)
7580 #define EBU_BUSWCON0_LOCKCS_Msk (0x8000000UL)
7581 #define EBU_BUSWCON0_AGEN_Pos (28UL)
7582 #define EBU_BUSWCON0_AGEN_Msk (0xf0000000UL)
7584 /* --------------------------------- EBU_BUSWAP0 -------------------------------- */
7585 #define EBU_BUSWAP0_WRDTACS_Pos (0UL)
7586 #define EBU_BUSWAP0_WRDTACS_Msk (0xfUL)
7587 #define EBU_BUSWAP0_WRRECOVC_Pos (4UL)
7588 #define EBU_BUSWAP0_WRRECOVC_Msk (0x70UL)
7589 #define EBU_BUSWAP0_WAITWRC_Pos (7UL)
7590 #define EBU_BUSWAP0_WAITWRC_Msk (0xf80UL)
7591 #define EBU_BUSWAP0_DATAC_Pos (12UL)
7592 #define EBU_BUSWAP0_DATAC_Msk (0xf000UL)
7593 #define EBU_BUSWAP0_EXTCLOCK_Pos (16UL)
7594 #define EBU_BUSWAP0_EXTCLOCK_Msk (0x30000UL)
7595 #define EBU_BUSWAP0_EXTDATA_Pos (18UL)
7596 #define EBU_BUSWAP0_EXTDATA_Msk (0xc0000UL)
7597 #define EBU_BUSWAP0_CMDDELAY_Pos (20UL)
7598 #define EBU_BUSWAP0_CMDDELAY_Msk (0xf00000UL)
7599 #define EBU_BUSWAP0_AHOLDC_Pos (24UL)
7600 #define EBU_BUSWAP0_AHOLDC_Msk (0xf000000UL)
7601 #define EBU_BUSWAP0_ADDRC_Pos (28UL)
7602 #define EBU_BUSWAP0_ADDRC_Msk (0xf0000000UL)
7604 /* -------------------------------- EBU_BUSRCON1 -------------------------------- */
7605 #define EBU_BUSRCON1_FETBLEN_Pos (0UL)
7606 #define EBU_BUSRCON1_FETBLEN_Msk (0x7UL)
7607 #define EBU_BUSRCON1_FBBMSEL_Pos (3UL)
7608 #define EBU_BUSRCON1_FBBMSEL_Msk (0x8UL)
7609 #define EBU_BUSRCON1_BFSSS_Pos (4UL)
7610 #define EBU_BUSRCON1_BFSSS_Msk (0x10UL)
7611 #define EBU_BUSRCON1_FDBKEN_Pos (5UL)
7612 #define EBU_BUSRCON1_FDBKEN_Msk (0x20UL)
7613 #define EBU_BUSRCON1_BFCMSEL_Pos (6UL)
7614 #define EBU_BUSRCON1_BFCMSEL_Msk (0x40UL)
7615 #define EBU_BUSRCON1_NAA_Pos (7UL)
7616 #define EBU_BUSRCON1_NAA_Msk (0x80UL)
7617 #define EBU_BUSRCON1_ECSE_Pos (16UL)
7618 #define EBU_BUSRCON1_ECSE_Msk (0x10000UL)
7619 #define EBU_BUSRCON1_EBSE_Pos (17UL)
7620 #define EBU_BUSRCON1_EBSE_Msk (0x20000UL)
7621 #define EBU_BUSRCON1_DBA_Pos (18UL)
7622 #define EBU_BUSRCON1_DBA_Msk (0x40000UL)
7623 #define EBU_BUSRCON1_WAITINV_Pos (19UL)
7624 #define EBU_BUSRCON1_WAITINV_Msk (0x80000UL)
7625 #define EBU_BUSRCON1_BCGEN_Pos (20UL)
7626 #define EBU_BUSRCON1_BCGEN_Msk (0x300000UL)
7627 #define EBU_BUSRCON1_PORTW_Pos (22UL)
7628 #define EBU_BUSRCON1_PORTW_Msk (0xc00000UL)
7629 #define EBU_BUSRCON1_WAIT_Pos (24UL)
7630 #define EBU_BUSRCON1_WAIT_Msk (0x3000000UL)
7631 #define EBU_BUSRCON1_AAP_Pos (26UL)
7632 #define EBU_BUSRCON1_AAP_Msk (0x4000000UL)
7633 #define EBU_BUSRCON1_AGEN_Pos (28UL)
7634 #define EBU_BUSRCON1_AGEN_Msk (0xf0000000UL)
7636 /* --------------------------------- EBU_BUSRAP1 -------------------------------- */
7637 #define EBU_BUSRAP1_RDDTACS_Pos (0UL)
7638 #define EBU_BUSRAP1_RDDTACS_Msk (0xfUL)
7639 #define EBU_BUSRAP1_RDRECOVC_Pos (4UL)
7640 #define EBU_BUSRAP1_RDRECOVC_Msk (0x70UL)
7641 #define EBU_BUSRAP1_WAITRDC_Pos (7UL)
7642 #define EBU_BUSRAP1_WAITRDC_Msk (0xf80UL)
7643 #define EBU_BUSRAP1_DATAC_Pos (12UL)
7644 #define EBU_BUSRAP1_DATAC_Msk (0xf000UL)
7645 #define EBU_BUSRAP1_EXTCLOCK_Pos (16UL)
7646 #define EBU_BUSRAP1_EXTCLOCK_Msk (0x30000UL)
7647 #define EBU_BUSRAP1_EXTDATA_Pos (18UL)
7648 #define EBU_BUSRAP1_EXTDATA_Msk (0xc0000UL)
7649 #define EBU_BUSRAP1_CMDDELAY_Pos (20UL)
7650 #define EBU_BUSRAP1_CMDDELAY_Msk (0xf00000UL)
7651 #define EBU_BUSRAP1_AHOLDC_Pos (24UL)
7652 #define EBU_BUSRAP1_AHOLDC_Msk (0xf000000UL)
7653 #define EBU_BUSRAP1_ADDRC_Pos (28UL)
7654 #define EBU_BUSRAP1_ADDRC_Msk (0xf0000000UL)
7656 /* -------------------------------- EBU_BUSWCON1 -------------------------------- */
7657 #define EBU_BUSWCON1_FETBLEN_Pos (0UL)
7658 #define EBU_BUSWCON1_FETBLEN_Msk (0x7UL)
7659 #define EBU_BUSWCON1_FBBMSEL_Pos (3UL)
7660 #define EBU_BUSWCON1_FBBMSEL_Msk (0x8UL)
7661 #define EBU_BUSWCON1_NAA_Pos (7UL)
7662 #define EBU_BUSWCON1_NAA_Msk (0x80UL)
7663 #define EBU_BUSWCON1_ECSE_Pos (16UL)
7664 #define EBU_BUSWCON1_ECSE_Msk (0x10000UL)
7665 #define EBU_BUSWCON1_EBSE_Pos (17UL)
7666 #define EBU_BUSWCON1_EBSE_Msk (0x20000UL)
7667 #define EBU_BUSWCON1_WAITINV_Pos (19UL)
7668 #define EBU_BUSWCON1_WAITINV_Msk (0x80000UL)
7669 #define EBU_BUSWCON1_BCGEN_Pos (20UL)
7670 #define EBU_BUSWCON1_BCGEN_Msk (0x300000UL)
7671 #define EBU_BUSWCON1_PORTW_Pos (22UL)
7672 #define EBU_BUSWCON1_PORTW_Msk (0xc00000UL)
7673 #define EBU_BUSWCON1_WAIT_Pos (24UL)
7674 #define EBU_BUSWCON1_WAIT_Msk (0x3000000UL)
7675 #define EBU_BUSWCON1_AAP_Pos (26UL)
7676 #define EBU_BUSWCON1_AAP_Msk (0x4000000UL)
7677 #define EBU_BUSWCON1_LOCKCS_Pos (27UL)
7678 #define EBU_BUSWCON1_LOCKCS_Msk (0x8000000UL)
7679 #define EBU_BUSWCON1_AGEN_Pos (28UL)
7680 #define EBU_BUSWCON1_AGEN_Msk (0xf0000000UL)
7682 /* --------------------------------- EBU_BUSWAP1 -------------------------------- */
7683 #define EBU_BUSWAP1_WRDTACS_Pos (0UL)
7684 #define EBU_BUSWAP1_WRDTACS_Msk (0xfUL)
7685 #define EBU_BUSWAP1_WRRECOVC_Pos (4UL)
7686 #define EBU_BUSWAP1_WRRECOVC_Msk (0x70UL)
7687 #define EBU_BUSWAP1_WAITWRC_Pos (7UL)
7688 #define EBU_BUSWAP1_WAITWRC_Msk (0xf80UL)
7689 #define EBU_BUSWAP1_DATAC_Pos (12UL)
7690 #define EBU_BUSWAP1_DATAC_Msk (0xf000UL)
7691 #define EBU_BUSWAP1_EXTCLOCK_Pos (16UL)
7692 #define EBU_BUSWAP1_EXTCLOCK_Msk (0x30000UL)
7693 #define EBU_BUSWAP1_EXTDATA_Pos (18UL)
7694 #define EBU_BUSWAP1_EXTDATA_Msk (0xc0000UL)
7695 #define EBU_BUSWAP1_CMDDELAY_Pos (20UL)
7696 #define EBU_BUSWAP1_CMDDELAY_Msk (0xf00000UL)
7697 #define EBU_BUSWAP1_AHOLDC_Pos (24UL)
7698 #define EBU_BUSWAP1_AHOLDC_Msk (0xf000000UL)
7699 #define EBU_BUSWAP1_ADDRC_Pos (28UL)
7700 #define EBU_BUSWAP1_ADDRC_Msk (0xf0000000UL)
7702 /* -------------------------------- EBU_BUSRCON2 -------------------------------- */
7703 #define EBU_BUSRCON2_FETBLEN_Pos (0UL)
7704 #define EBU_BUSRCON2_FETBLEN_Msk (0x7UL)
7705 #define EBU_BUSRCON2_FBBMSEL_Pos (3UL)
7706 #define EBU_BUSRCON2_FBBMSEL_Msk (0x8UL)
7707 #define EBU_BUSRCON2_BFSSS_Pos (4UL)
7708 #define EBU_BUSRCON2_BFSSS_Msk (0x10UL)
7709 #define EBU_BUSRCON2_FDBKEN_Pos (5UL)
7710 #define EBU_BUSRCON2_FDBKEN_Msk (0x20UL)
7711 #define EBU_BUSRCON2_BFCMSEL_Pos (6UL)
7712 #define EBU_BUSRCON2_BFCMSEL_Msk (0x40UL)
7713 #define EBU_BUSRCON2_NAA_Pos (7UL)
7714 #define EBU_BUSRCON2_NAA_Msk (0x80UL)
7715 #define EBU_BUSRCON2_ECSE_Pos (16UL)
7716 #define EBU_BUSRCON2_ECSE_Msk (0x10000UL)
7717 #define EBU_BUSRCON2_EBSE_Pos (17UL)
7718 #define EBU_BUSRCON2_EBSE_Msk (0x20000UL)
7719 #define EBU_BUSRCON2_DBA_Pos (18UL)
7720 #define EBU_BUSRCON2_DBA_Msk (0x40000UL)
7721 #define EBU_BUSRCON2_WAITINV_Pos (19UL)
7722 #define EBU_BUSRCON2_WAITINV_Msk (0x80000UL)
7723 #define EBU_BUSRCON2_BCGEN_Pos (20UL)
7724 #define EBU_BUSRCON2_BCGEN_Msk (0x300000UL)
7725 #define EBU_BUSRCON2_PORTW_Pos (22UL)
7726 #define EBU_BUSRCON2_PORTW_Msk (0xc00000UL)
7727 #define EBU_BUSRCON2_WAIT_Pos (24UL)
7728 #define EBU_BUSRCON2_WAIT_Msk (0x3000000UL)
7729 #define EBU_BUSRCON2_AAP_Pos (26UL)
7730 #define EBU_BUSRCON2_AAP_Msk (0x4000000UL)
7731 #define EBU_BUSRCON2_AGEN_Pos (28UL)
7732 #define EBU_BUSRCON2_AGEN_Msk (0xf0000000UL)
7734 /* --------------------------------- EBU_BUSRAP2 -------------------------------- */
7735 #define EBU_BUSRAP2_RDDTACS_Pos (0UL)
7736 #define EBU_BUSRAP2_RDDTACS_Msk (0xfUL)
7737 #define EBU_BUSRAP2_RDRECOVC_Pos (4UL)
7738 #define EBU_BUSRAP2_RDRECOVC_Msk (0x70UL)
7739 #define EBU_BUSRAP2_WAITRDC_Pos (7UL)
7740 #define EBU_BUSRAP2_WAITRDC_Msk (0xf80UL)
7741 #define EBU_BUSRAP2_DATAC_Pos (12UL)
7742 #define EBU_BUSRAP2_DATAC_Msk (0xf000UL)
7743 #define EBU_BUSRAP2_EXTCLOCK_Pos (16UL)
7744 #define EBU_BUSRAP2_EXTCLOCK_Msk (0x30000UL)
7745 #define EBU_BUSRAP2_EXTDATA_Pos (18UL)
7746 #define EBU_BUSRAP2_EXTDATA_Msk (0xc0000UL)
7747 #define EBU_BUSRAP2_CMDDELAY_Pos (20UL)
7748 #define EBU_BUSRAP2_CMDDELAY_Msk (0xf00000UL)
7749 #define EBU_BUSRAP2_AHOLDC_Pos (24UL)
7750 #define EBU_BUSRAP2_AHOLDC_Msk (0xf000000UL)
7751 #define EBU_BUSRAP2_ADDRC_Pos (28UL)
7752 #define EBU_BUSRAP2_ADDRC_Msk (0xf0000000UL)
7754 /* -------------------------------- EBU_BUSWCON2 -------------------------------- */
7755 #define EBU_BUSWCON2_FETBLEN_Pos (0UL)
7756 #define EBU_BUSWCON2_FETBLEN_Msk (0x7UL)
7757 #define EBU_BUSWCON2_FBBMSEL_Pos (3UL)
7758 #define EBU_BUSWCON2_FBBMSEL_Msk (0x8UL)
7759 #define EBU_BUSWCON2_NAA_Pos (7UL)
7760 #define EBU_BUSWCON2_NAA_Msk (0x80UL)
7761 #define EBU_BUSWCON2_ECSE_Pos (16UL)
7762 #define EBU_BUSWCON2_ECSE_Msk (0x10000UL)
7763 #define EBU_BUSWCON2_EBSE_Pos (17UL)
7764 #define EBU_BUSWCON2_EBSE_Msk (0x20000UL)
7765 #define EBU_BUSWCON2_WAITINV_Pos (19UL)
7766 #define EBU_BUSWCON2_WAITINV_Msk (0x80000UL)
7767 #define EBU_BUSWCON2_BCGEN_Pos (20UL)
7768 #define EBU_BUSWCON2_BCGEN_Msk (0x300000UL)
7769 #define EBU_BUSWCON2_PORTW_Pos (22UL)
7770 #define EBU_BUSWCON2_PORTW_Msk (0xc00000UL)
7771 #define EBU_BUSWCON2_WAIT_Pos (24UL)
7772 #define EBU_BUSWCON2_WAIT_Msk (0x3000000UL)
7773 #define EBU_BUSWCON2_AAP_Pos (26UL)
7774 #define EBU_BUSWCON2_AAP_Msk (0x4000000UL)
7775 #define EBU_BUSWCON2_LOCKCS_Pos (27UL)
7776 #define EBU_BUSWCON2_LOCKCS_Msk (0x8000000UL)
7777 #define EBU_BUSWCON2_AGEN_Pos (28UL)
7778 #define EBU_BUSWCON2_AGEN_Msk (0xf0000000UL)
7780 /* --------------------------------- EBU_BUSWAP2 -------------------------------- */
7781 #define EBU_BUSWAP2_WRDTACS_Pos (0UL)
7782 #define EBU_BUSWAP2_WRDTACS_Msk (0xfUL)
7783 #define EBU_BUSWAP2_WRRECOVC_Pos (4UL)
7784 #define EBU_BUSWAP2_WRRECOVC_Msk (0x70UL)
7785 #define EBU_BUSWAP2_WAITWRC_Pos (7UL)
7786 #define EBU_BUSWAP2_WAITWRC_Msk (0xf80UL)
7787 #define EBU_BUSWAP2_DATAC_Pos (12UL)
7788 #define EBU_BUSWAP2_DATAC_Msk (0xf000UL)
7789 #define EBU_BUSWAP2_EXTCLOCK_Pos (16UL)
7790 #define EBU_BUSWAP2_EXTCLOCK_Msk (0x30000UL)
7791 #define EBU_BUSWAP2_EXTDATA_Pos (18UL)
7792 #define EBU_BUSWAP2_EXTDATA_Msk (0xc0000UL)
7793 #define EBU_BUSWAP2_CMDDELAY_Pos (20UL)
7794 #define EBU_BUSWAP2_CMDDELAY_Msk (0xf00000UL)
7795 #define EBU_BUSWAP2_AHOLDC_Pos (24UL)
7796 #define EBU_BUSWAP2_AHOLDC_Msk (0xf000000UL)
7797 #define EBU_BUSWAP2_ADDRC_Pos (28UL)
7798 #define EBU_BUSWAP2_ADDRC_Msk (0xf0000000UL)
7800 /* -------------------------------- EBU_BUSRCON3 -------------------------------- */
7801 #define EBU_BUSRCON3_FETBLEN_Pos (0UL)
7802 #define EBU_BUSRCON3_FETBLEN_Msk (0x7UL)
7803 #define EBU_BUSRCON3_FBBMSEL_Pos (3UL)
7804 #define EBU_BUSRCON3_FBBMSEL_Msk (0x8UL)
7805 #define EBU_BUSRCON3_BFSSS_Pos (4UL)
7806 #define EBU_BUSRCON3_BFSSS_Msk (0x10UL)
7807 #define EBU_BUSRCON3_FDBKEN_Pos (5UL)
7808 #define EBU_BUSRCON3_FDBKEN_Msk (0x20UL)
7809 #define EBU_BUSRCON3_BFCMSEL_Pos (6UL)
7810 #define EBU_BUSRCON3_BFCMSEL_Msk (0x40UL)
7811 #define EBU_BUSRCON3_NAA_Pos (7UL)
7812 #define EBU_BUSRCON3_NAA_Msk (0x80UL)
7813 #define EBU_BUSRCON3_ECSE_Pos (16UL)
7814 #define EBU_BUSRCON3_ECSE_Msk (0x10000UL)
7815 #define EBU_BUSRCON3_EBSE_Pos (17UL)
7816 #define EBU_BUSRCON3_EBSE_Msk (0x20000UL)
7817 #define EBU_BUSRCON3_DBA_Pos (18UL)
7818 #define EBU_BUSRCON3_DBA_Msk (0x40000UL)
7819 #define EBU_BUSRCON3_WAITINV_Pos (19UL)
7820 #define EBU_BUSRCON3_WAITINV_Msk (0x80000UL)
7821 #define EBU_BUSRCON3_BCGEN_Pos (20UL)
7822 #define EBU_BUSRCON3_BCGEN_Msk (0x300000UL)
7823 #define EBU_BUSRCON3_PORTW_Pos (22UL)
7824 #define EBU_BUSRCON3_PORTW_Msk (0xc00000UL)
7825 #define EBU_BUSRCON3_WAIT_Pos (24UL)
7826 #define EBU_BUSRCON3_WAIT_Msk (0x3000000UL)
7827 #define EBU_BUSRCON3_AAP_Pos (26UL)
7828 #define EBU_BUSRCON3_AAP_Msk (0x4000000UL)
7829 #define EBU_BUSRCON3_AGEN_Pos (28UL)
7830 #define EBU_BUSRCON3_AGEN_Msk (0xf0000000UL)
7832 /* --------------------------------- EBU_BUSRAP3 -------------------------------- */
7833 #define EBU_BUSRAP3_RDDTACS_Pos (0UL)
7834 #define EBU_BUSRAP3_RDDTACS_Msk (0xfUL)
7835 #define EBU_BUSRAP3_RDRECOVC_Pos (4UL)
7836 #define EBU_BUSRAP3_RDRECOVC_Msk (0x70UL)
7837 #define EBU_BUSRAP3_WAITRDC_Pos (7UL)
7838 #define EBU_BUSRAP3_WAITRDC_Msk (0xf80UL)
7839 #define EBU_BUSRAP3_DATAC_Pos (12UL)
7840 #define EBU_BUSRAP3_DATAC_Msk (0xf000UL)
7841 #define EBU_BUSRAP3_EXTCLOCK_Pos (16UL)
7842 #define EBU_BUSRAP3_EXTCLOCK_Msk (0x30000UL)
7843 #define EBU_BUSRAP3_EXTDATA_Pos (18UL)
7844 #define EBU_BUSRAP3_EXTDATA_Msk (0xc0000UL)
7845 #define EBU_BUSRAP3_CMDDELAY_Pos (20UL)
7846 #define EBU_BUSRAP3_CMDDELAY_Msk (0xf00000UL)
7847 #define EBU_BUSRAP3_AHOLDC_Pos (24UL)
7848 #define EBU_BUSRAP3_AHOLDC_Msk (0xf000000UL)
7849 #define EBU_BUSRAP3_ADDRC_Pos (28UL)
7850 #define EBU_BUSRAP3_ADDRC_Msk (0xf0000000UL)
7852 /* -------------------------------- EBU_BUSWCON3 -------------------------------- */
7853 #define EBU_BUSWCON3_FETBLEN_Pos (0UL)
7854 #define EBU_BUSWCON3_FETBLEN_Msk (0x7UL)
7855 #define EBU_BUSWCON3_FBBMSEL_Pos (3UL)
7856 #define EBU_BUSWCON3_FBBMSEL_Msk (0x8UL)
7857 #define EBU_BUSWCON3_NAA_Pos (7UL)
7858 #define EBU_BUSWCON3_NAA_Msk (0x80UL)
7859 #define EBU_BUSWCON3_ECSE_Pos (16UL)
7860 #define EBU_BUSWCON3_ECSE_Msk (0x10000UL)
7861 #define EBU_BUSWCON3_EBSE_Pos (17UL)
7862 #define EBU_BUSWCON3_EBSE_Msk (0x20000UL)
7863 #define EBU_BUSWCON3_WAITINV_Pos (19UL)
7864 #define EBU_BUSWCON3_WAITINV_Msk (0x80000UL)
7865 #define EBU_BUSWCON3_BCGEN_Pos (20UL)
7866 #define EBU_BUSWCON3_BCGEN_Msk (0x300000UL)
7867 #define EBU_BUSWCON3_PORTW_Pos (22UL)
7868 #define EBU_BUSWCON3_PORTW_Msk (0xc00000UL)
7869 #define EBU_BUSWCON3_WAIT_Pos (24UL)
7870 #define EBU_BUSWCON3_WAIT_Msk (0x3000000UL)
7871 #define EBU_BUSWCON3_AAP_Pos (26UL)
7872 #define EBU_BUSWCON3_AAP_Msk (0x4000000UL)
7873 #define EBU_BUSWCON3_LOCKCS_Pos (27UL)
7874 #define EBU_BUSWCON3_LOCKCS_Msk (0x8000000UL)
7875 #define EBU_BUSWCON3_AGEN_Pos (28UL)
7876 #define EBU_BUSWCON3_AGEN_Msk (0xf0000000UL)
7878 /* --------------------------------- EBU_BUSWAP3 -------------------------------- */
7879 #define EBU_BUSWAP3_WRDTACS_Pos (0UL)
7880 #define EBU_BUSWAP3_WRDTACS_Msk (0xfUL)
7881 #define EBU_BUSWAP3_WRRECOVC_Pos (4UL)
7882 #define EBU_BUSWAP3_WRRECOVC_Msk (0x70UL)
7883 #define EBU_BUSWAP3_WAITWRC_Pos (7UL)
7884 #define EBU_BUSWAP3_WAITWRC_Msk (0xf80UL)
7885 #define EBU_BUSWAP3_DATAC_Pos (12UL)
7886 #define EBU_BUSWAP3_DATAC_Msk (0xf000UL)
7887 #define EBU_BUSWAP3_EXTCLOCK_Pos (16UL)
7888 #define EBU_BUSWAP3_EXTCLOCK_Msk (0x30000UL)
7889 #define EBU_BUSWAP3_EXTDATA_Pos (18UL)
7890 #define EBU_BUSWAP3_EXTDATA_Msk (0xc0000UL)
7891 #define EBU_BUSWAP3_CMDDELAY_Pos (20UL)
7892 #define EBU_BUSWAP3_CMDDELAY_Msk (0xf00000UL)
7893 #define EBU_BUSWAP3_AHOLDC_Pos (24UL)
7894 #define EBU_BUSWAP3_AHOLDC_Msk (0xf000000UL)
7895 #define EBU_BUSWAP3_ADDRC_Pos (28UL)
7896 #define EBU_BUSWAP3_ADDRC_Msk (0xf0000000UL)
7898 /* --------------------------------- EBU_SDRMCON -------------------------------- */
7899 #define EBU_SDRMCON_CRAS_Pos (0UL)
7900 #define EBU_SDRMCON_CRAS_Msk (0xfUL)
7901 #define EBU_SDRMCON_CRFSH_Pos (4UL)
7902 #define EBU_SDRMCON_CRFSH_Msk (0xf0UL)
7903 #define EBU_SDRMCON_CRSC_Pos (8UL)
7904 #define EBU_SDRMCON_CRSC_Msk (0x300UL)
7905 #define EBU_SDRMCON_CRP_Pos (10UL)
7906 #define EBU_SDRMCON_CRP_Msk (0xc00UL)
7907 #define EBU_SDRMCON_AWIDTH_Pos (12UL)
7908 #define EBU_SDRMCON_AWIDTH_Msk (0x3000UL)
7909 #define EBU_SDRMCON_CRCD_Pos (14UL)
7910 #define EBU_SDRMCON_CRCD_Msk (0xc000UL)
7911 #define EBU_SDRMCON_CRC_Pos (16UL)
7912 #define EBU_SDRMCON_CRC_Msk (0x70000UL)
7913 #define EBU_SDRMCON_ROWM_Pos (19UL)
7914 #define EBU_SDRMCON_ROWM_Msk (0x380000UL)
7915 #define EBU_SDRMCON_BANKM_Pos (22UL)
7916 #define EBU_SDRMCON_BANKM_Msk (0x1c00000UL)
7917 #define EBU_SDRMCON_CRCE_Pos (25UL)
7918 #define EBU_SDRMCON_CRCE_Msk (0xe000000UL)
7919 #define EBU_SDRMCON_CLKDIS_Pos (28UL)
7920 #define EBU_SDRMCON_CLKDIS_Msk (0x10000000UL)
7921 #define EBU_SDRMCON_PWR_MODE_Pos (29UL)
7922 #define EBU_SDRMCON_PWR_MODE_Msk (0x60000000UL)
7923 #define EBU_SDRMCON_SDCMSEL_Pos (31UL)
7924 #define EBU_SDRMCON_SDCMSEL_Msk (0x80000000UL)
7926 /* --------------------------------- EBU_SDRMOD --------------------------------- */
7927 #define EBU_SDRMOD_BURSTL_Pos (0UL)
7928 #define EBU_SDRMOD_BURSTL_Msk (0x7UL)
7929 #define EBU_SDRMOD_BTYP_Pos (3UL)
7930 #define EBU_SDRMOD_BTYP_Msk (0x8UL)
7931 #define EBU_SDRMOD_CASLAT_Pos (4UL)
7932 #define EBU_SDRMOD_CASLAT_Msk (0x70UL)
7933 #define EBU_SDRMOD_OPMODE_Pos (7UL)
7934 #define EBU_SDRMOD_OPMODE_Msk (0x3f80UL)
7935 #define EBU_SDRMOD_COLDSTART_Pos (15UL)
7936 #define EBU_SDRMOD_COLDSTART_Msk (0x8000UL)
7937 #define EBU_SDRMOD_XOPM_Pos (16UL)
7938 #define EBU_SDRMOD_XOPM_Msk (0xfff0000UL)
7939 #define EBU_SDRMOD_XBA_Pos (28UL)
7940 #define EBU_SDRMOD_XBA_Msk (0xf0000000UL)
7942 /* --------------------------------- EBU_SDRMREF -------------------------------- */
7943 #define EBU_SDRMREF_REFRESHC_Pos (0UL)
7944 #define EBU_SDRMREF_REFRESHC_Msk (0x3fUL)
7945 #define EBU_SDRMREF_REFRESHR_Pos (6UL)
7946 #define EBU_SDRMREF_REFRESHR_Msk (0x1c0UL)
7947 #define EBU_SDRMREF_SELFREXST_Pos (9UL)
7948 #define EBU_SDRMREF_SELFREXST_Msk (0x200UL)
7949 #define EBU_SDRMREF_SELFREX_Pos (10UL)
7950 #define EBU_SDRMREF_SELFREX_Msk (0x400UL)
7951 #define EBU_SDRMREF_SELFRENST_Pos (11UL)
7952 #define EBU_SDRMREF_SELFRENST_Msk (0x800UL)
7953 #define EBU_SDRMREF_SELFREN_Pos (12UL)
7954 #define EBU_SDRMREF_SELFREN_Msk (0x1000UL)
7955 #define EBU_SDRMREF_AUTOSELFR_Pos (13UL)
7956 #define EBU_SDRMREF_AUTOSELFR_Msk (0x2000UL)
7957 #define EBU_SDRMREF_ERFSHC_Pos (14UL)
7958 #define EBU_SDRMREF_ERFSHC_Msk (0xc000UL)
7959 #define EBU_SDRMREF_SELFREX_DLY_Pos (16UL)
7960 #define EBU_SDRMREF_SELFREX_DLY_Msk (0xff0000UL)
7961 #define EBU_SDRMREF_ARFSH_Pos (24UL)
7962 #define EBU_SDRMREF_ARFSH_Msk (0x1000000UL)
7963 #define EBU_SDRMREF_RES_DLY_Pos (25UL)
7964 #define EBU_SDRMREF_RES_DLY_Msk (0xe000000UL)
7966 /* --------------------------------- EBU_SDRSTAT -------------------------------- */
7967 #define EBU_SDRSTAT_REFERR_Pos (0UL)
7968 #define EBU_SDRSTAT_REFERR_Msk (0x1UL)
7969 #define EBU_SDRSTAT_SDRMBUSY_Pos (1UL)
7970 #define EBU_SDRSTAT_SDRMBUSY_Msk (0x2UL)
7971 #define EBU_SDRSTAT_SDERR_Pos (2UL)
7972 #define EBU_SDRSTAT_SDERR_Msk (0x4UL)
7975 /* ================================================================================ */
7976 /* ================ struct 'ETH0_CON' Position & Mask ================ */
7977 /* ================================================================================ */
7978 
7979 
7980 /* ------------------------------ ETH0_CON_ETH0_CON ----------------------------- */
7981 #define ETH_CON_RXD0_Pos (0UL)
7982 #define ETH_CON_RXD0_Msk (0x3UL)
7983 #define ETH_CON_RXD1_Pos (2UL)
7984 #define ETH_CON_RXD1_Msk (0xcUL)
7985 #define ETH_CON_RXD2_Pos (4UL)
7986 #define ETH_CON_RXD2_Msk (0x30UL)
7987 #define ETH_CON_RXD3_Pos (6UL)
7988 #define ETH_CON_RXD3_Msk (0xc0UL)
7989 #define ETH_CON_CLK_RMII_Pos (8UL)
7990 #define ETH_CON_CLK_RMII_Msk (0x300UL)
7991 #define ETH_CON_CRS_DV_Pos (10UL)
7992 #define ETH_CON_CRS_DV_Msk (0xc00UL)
7993 #define ETH_CON_CRS_Pos (12UL)
7994 #define ETH_CON_CRS_Msk (0x3000UL)
7995 #define ETH_CON_RXER_Pos (14UL)
7996 #define ETH_CON_RXER_Msk (0xc000UL)
7997 #define ETH_CON_COL_Pos (16UL)
7998 #define ETH_CON_COL_Msk (0x30000UL)
7999 #define ETH_CON_CLK_TX_Pos (18UL)
8000 #define ETH_CON_CLK_TX_Msk (0xc0000UL)
8001 #define ETH_CON_MDIO_Pos (22UL)
8002 #define ETH_CON_MDIO_Msk (0xc00000UL)
8003 #define ETH_CON_INFSEL_Pos (26UL)
8004 #define ETH_CON_INFSEL_Msk (0x4000000UL)
8007 /* ================================================================================ */
8008 /* ================ Group 'ETH' Position & Mask ================ */
8009 /* ================================================================================ */
8010 
8011 
8012 /* ---------------------------- ETH_MAC_CONFIGURATION --------------------------- */
8013 #define ETH_MAC_CONFIGURATION_PRELEN_Pos (0UL)
8014 #define ETH_MAC_CONFIGURATION_PRELEN_Msk (0x3UL)
8015 #define ETH_MAC_CONFIGURATION_RE_Pos (2UL)
8016 #define ETH_MAC_CONFIGURATION_RE_Msk (0x4UL)
8017 #define ETH_MAC_CONFIGURATION_TE_Pos (3UL)
8018 #define ETH_MAC_CONFIGURATION_TE_Msk (0x8UL)
8019 #define ETH_MAC_CONFIGURATION_DC_Pos (4UL)
8020 #define ETH_MAC_CONFIGURATION_DC_Msk (0x10UL)
8021 #define ETH_MAC_CONFIGURATION_BL_Pos (5UL)
8022 #define ETH_MAC_CONFIGURATION_BL_Msk (0x60UL)
8023 #define ETH_MAC_CONFIGURATION_ACS_Pos (7UL)
8024 #define ETH_MAC_CONFIGURATION_ACS_Msk (0x80UL)
8025 #define ETH_MAC_CONFIGURATION_DR_Pos (9UL)
8026 #define ETH_MAC_CONFIGURATION_DR_Msk (0x200UL)
8027 #define ETH_MAC_CONFIGURATION_IPC_Pos (10UL)
8028 #define ETH_MAC_CONFIGURATION_IPC_Msk (0x400UL)
8029 #define ETH_MAC_CONFIGURATION_DM_Pos (11UL)
8030 #define ETH_MAC_CONFIGURATION_DM_Msk (0x800UL)
8031 #define ETH_MAC_CONFIGURATION_LM_Pos (12UL)
8032 #define ETH_MAC_CONFIGURATION_LM_Msk (0x1000UL)
8033 #define ETH_MAC_CONFIGURATION_DO_Pos (13UL)
8034 #define ETH_MAC_CONFIGURATION_DO_Msk (0x2000UL)
8035 #define ETH_MAC_CONFIGURATION_FES_Pos (14UL)
8036 #define ETH_MAC_CONFIGURATION_FES_Msk (0x4000UL)
8037 #define ETH_MAC_CONFIGURATION_DCRS_Pos (16UL)
8038 #define ETH_MAC_CONFIGURATION_DCRS_Msk (0x10000UL)
8039 #define ETH_MAC_CONFIGURATION_IFG_Pos (17UL)
8040 #define ETH_MAC_CONFIGURATION_IFG_Msk (0xe0000UL)
8041 #define ETH_MAC_CONFIGURATION_JE_Pos (20UL)
8042 #define ETH_MAC_CONFIGURATION_JE_Msk (0x100000UL)
8043 #define ETH_MAC_CONFIGURATION_BE_Pos (21UL)
8044 #define ETH_MAC_CONFIGURATION_BE_Msk (0x200000UL)
8045 #define ETH_MAC_CONFIGURATION_JD_Pos (22UL)
8046 #define ETH_MAC_CONFIGURATION_JD_Msk (0x400000UL)
8047 #define ETH_MAC_CONFIGURATION_WD_Pos (23UL)
8048 #define ETH_MAC_CONFIGURATION_WD_Msk (0x800000UL)
8049 #define ETH_MAC_CONFIGURATION_TC_Pos (24UL)
8050 #define ETH_MAC_CONFIGURATION_TC_Msk (0x1000000UL)
8051 #define ETH_MAC_CONFIGURATION_CST_Pos (25UL)
8052 #define ETH_MAC_CONFIGURATION_CST_Msk (0x2000000UL)
8053 #define ETH_MAC_CONFIGURATION_TWOKPE_Pos (27UL)
8054 #define ETH_MAC_CONFIGURATION_TWOKPE_Msk (0x8000000UL)
8055 #define ETH_MAC_CONFIGURATION_SARC_Pos (28UL)
8056 #define ETH_MAC_CONFIGURATION_SARC_Msk (0x70000000UL)
8058 /* ---------------------------- ETH_MAC_FRAME_FILTER ---------------------------- */
8059 #define ETH_MAC_FRAME_FILTER_PR_Pos (0UL)
8060 #define ETH_MAC_FRAME_FILTER_PR_Msk (0x1UL)
8061 #define ETH_MAC_FRAME_FILTER_HUC_Pos (1UL)
8062 #define ETH_MAC_FRAME_FILTER_HUC_Msk (0x2UL)
8063 #define ETH_MAC_FRAME_FILTER_HMC_Pos (2UL)
8064 #define ETH_MAC_FRAME_FILTER_HMC_Msk (0x4UL)
8065 #define ETH_MAC_FRAME_FILTER_DAIF_Pos (3UL)
8066 #define ETH_MAC_FRAME_FILTER_DAIF_Msk (0x8UL)
8067 #define ETH_MAC_FRAME_FILTER_PM_Pos (4UL)
8068 #define ETH_MAC_FRAME_FILTER_PM_Msk (0x10UL)
8069 #define ETH_MAC_FRAME_FILTER_DBF_Pos (5UL)
8070 #define ETH_MAC_FRAME_FILTER_DBF_Msk (0x20UL)
8071 #define ETH_MAC_FRAME_FILTER_PCF_Pos (6UL)
8072 #define ETH_MAC_FRAME_FILTER_PCF_Msk (0xc0UL)
8073 #define ETH_MAC_FRAME_FILTER_SAIF_Pos (8UL)
8074 #define ETH_MAC_FRAME_FILTER_SAIF_Msk (0x100UL)
8075 #define ETH_MAC_FRAME_FILTER_SAF_Pos (9UL)
8076 #define ETH_MAC_FRAME_FILTER_SAF_Msk (0x200UL)
8077 #define ETH_MAC_FRAME_FILTER_HPF_Pos (10UL)
8078 #define ETH_MAC_FRAME_FILTER_HPF_Msk (0x400UL)
8079 #define ETH_MAC_FRAME_FILTER_VTFE_Pos (16UL)
8080 #define ETH_MAC_FRAME_FILTER_VTFE_Msk (0x10000UL)
8081 #define ETH_MAC_FRAME_FILTER_IPFE_Pos (20UL)
8082 #define ETH_MAC_FRAME_FILTER_IPFE_Msk (0x100000UL)
8083 #define ETH_MAC_FRAME_FILTER_DNTU_Pos (21UL)
8084 #define ETH_MAC_FRAME_FILTER_DNTU_Msk (0x200000UL)
8085 #define ETH_MAC_FRAME_FILTER_RA_Pos (31UL)
8086 #define ETH_MAC_FRAME_FILTER_RA_Msk (0x80000000UL)
8088 /* ----------------------------- ETH_HASH_TABLE_HIGH ---------------------------- */
8089 #define ETH_HASH_TABLE_HIGH_HTH_Pos (0UL)
8090 #define ETH_HASH_TABLE_HIGH_HTH_Msk (0xffffffffUL)
8092 /* ----------------------------- ETH_HASH_TABLE_LOW ----------------------------- */
8093 #define ETH_HASH_TABLE_LOW_HTL_Pos (0UL)
8094 #define ETH_HASH_TABLE_LOW_HTL_Msk (0xffffffffUL)
8096 /* ------------------------------ ETH_GMII_ADDRESS ------------------------------ */
8097 #define ETH_GMII_ADDRESS_MB_Pos (0UL)
8098 #define ETH_GMII_ADDRESS_MB_Msk (0x1UL)
8099 #define ETH_GMII_ADDRESS_MW_Pos (1UL)
8100 #define ETH_GMII_ADDRESS_MW_Msk (0x2UL)
8101 #define ETH_GMII_ADDRESS_CR_Pos (2UL)
8102 #define ETH_GMII_ADDRESS_CR_Msk (0x3cUL)
8103 #define ETH_GMII_ADDRESS_MR_Pos (6UL)
8104 #define ETH_GMII_ADDRESS_MR_Msk (0x7c0UL)
8105 #define ETH_GMII_ADDRESS_PA_Pos (11UL)
8106 #define ETH_GMII_ADDRESS_PA_Msk (0xf800UL)
8108 /* -------------------------------- ETH_GMII_DATA ------------------------------- */
8109 #define ETH_GMII_DATA_MD_Pos (0UL)
8110 #define ETH_GMII_DATA_MD_Msk (0xffffUL)
8112 /* ------------------------------ ETH_FLOW_CONTROL ------------------------------ */
8113 #define ETH_FLOW_CONTROL_FCA_BPA_Pos (0UL)
8114 #define ETH_FLOW_CONTROL_FCA_BPA_Msk (0x1UL)
8115 #define ETH_FLOW_CONTROL_TFE_Pos (1UL)
8116 #define ETH_FLOW_CONTROL_TFE_Msk (0x2UL)
8117 #define ETH_FLOW_CONTROL_RFE_Pos (2UL)
8118 #define ETH_FLOW_CONTROL_RFE_Msk (0x4UL)
8119 #define ETH_FLOW_CONTROL_UP_Pos (3UL)
8120 #define ETH_FLOW_CONTROL_UP_Msk (0x8UL)
8121 #define ETH_FLOW_CONTROL_PLT_Pos (4UL)
8122 #define ETH_FLOW_CONTROL_PLT_Msk (0x30UL)
8123 #define ETH_FLOW_CONTROL_DZPQ_Pos (7UL)
8124 #define ETH_FLOW_CONTROL_DZPQ_Msk (0x80UL)
8125 #define ETH_FLOW_CONTROL_PT_Pos (16UL)
8126 #define ETH_FLOW_CONTROL_PT_Msk (0xffff0000UL)
8128 /* -------------------------------- ETH_VLAN_TAG -------------------------------- */
8129 #define ETH_VLAN_TAG_VL_Pos (0UL)
8130 #define ETH_VLAN_TAG_VL_Msk (0xffffUL)
8131 #define ETH_VLAN_TAG_ETV_Pos (16UL)
8132 #define ETH_VLAN_TAG_ETV_Msk (0x10000UL)
8133 #define ETH_VLAN_TAG_VTIM_Pos (17UL)
8134 #define ETH_VLAN_TAG_VTIM_Msk (0x20000UL)
8135 #define ETH_VLAN_TAG_ESVL_Pos (18UL)
8136 #define ETH_VLAN_TAG_ESVL_Msk (0x40000UL)
8137 #define ETH_VLAN_TAG_VTHM_Pos (19UL)
8138 #define ETH_VLAN_TAG_VTHM_Msk (0x80000UL)
8140 /* --------------------------------- ETH_VERSION -------------------------------- */
8141 #define ETH_VERSION_SNPSVER_Pos (0UL)
8142 #define ETH_VERSION_SNPSVER_Msk (0xffUL)
8143 #define ETH_VERSION_USERVER_Pos (8UL)
8144 #define ETH_VERSION_USERVER_Msk (0xff00UL)
8146 /* ---------------------------------- ETH_DEBUG --------------------------------- */
8147 #define ETH_DEBUG_RPESTS_Pos (0UL)
8148 #define ETH_DEBUG_RPESTS_Msk (0x1UL)
8149 #define ETH_DEBUG_RFCFCSTS_Pos (1UL)
8150 #define ETH_DEBUG_RFCFCSTS_Msk (0x6UL)
8151 #define ETH_DEBUG_RWCSTS_Pos (4UL)
8152 #define ETH_DEBUG_RWCSTS_Msk (0x10UL)
8153 #define ETH_DEBUG_RRCSTS_Pos (5UL)
8154 #define ETH_DEBUG_RRCSTS_Msk (0x60UL)
8155 #define ETH_DEBUG_RXFSTS_Pos (8UL)
8156 #define ETH_DEBUG_RXFSTS_Msk (0x300UL)
8157 #define ETH_DEBUG_TPESTS_Pos (16UL)
8158 #define ETH_DEBUG_TPESTS_Msk (0x10000UL)
8159 #define ETH_DEBUG_TFCSTS_Pos (17UL)
8160 #define ETH_DEBUG_TFCSTS_Msk (0x60000UL)
8161 #define ETH_DEBUG_TXPAUSED_Pos (19UL)
8162 #define ETH_DEBUG_TXPAUSED_Msk (0x80000UL)
8163 #define ETH_DEBUG_TRCSTS_Pos (20UL)
8164 #define ETH_DEBUG_TRCSTS_Msk (0x300000UL)
8165 #define ETH_DEBUG_TWCSTS_Pos (22UL)
8166 #define ETH_DEBUG_TWCSTS_Msk (0x400000UL)
8167 #define ETH_DEBUG_TXFSTS_Pos (24UL)
8168 #define ETH_DEBUG_TXFSTS_Msk (0x1000000UL)
8169 #define ETH_DEBUG_TXSTSFSTS_Pos (25UL)
8170 #define ETH_DEBUG_TXSTSFSTS_Msk (0x2000000UL)
8172 /* ----------------------- ETH_REMOTE_WAKE_UP_FRAME_FILTER ---------------------- */
8173 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Pos (0UL)
8174 #define ETH_REMOTE_WAKE_UP_FRAME_FILTER_WKUPFRMFTR_Msk (0xffffffffUL)
8176 /* --------------------------- ETH_PMT_CONTROL_STATUS --------------------------- */
8177 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Pos (0UL)
8178 #define ETH_PMT_CONTROL_STATUS_PWRDWN_Msk (0x1UL)
8179 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Pos (1UL)
8180 #define ETH_PMT_CONTROL_STATUS_MGKPKTEN_Msk (0x2UL)
8181 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Pos (2UL)
8182 #define ETH_PMT_CONTROL_STATUS_RWKPKTEN_Msk (0x4UL)
8183 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Pos (5UL)
8184 #define ETH_PMT_CONTROL_STATUS_MGKPRCVD_Msk (0x20UL)
8185 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Pos (6UL)
8186 #define ETH_PMT_CONTROL_STATUS_RWKPRCVD_Msk (0x40UL)
8187 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Pos (9UL)
8188 #define ETH_PMT_CONTROL_STATUS_GLBLUCAST_Msk (0x200UL)
8189 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Pos (31UL)
8190 #define ETH_PMT_CONTROL_STATUS_RWKFILTRST_Msk (0x80000000UL)
8192 /* ---------------------------- ETH_INTERRUPT_STATUS ---------------------------- */
8193 #define ETH_INTERRUPT_STATUS_PMTIS_Pos (3UL)
8194 #define ETH_INTERRUPT_STATUS_PMTIS_Msk (0x8UL)
8195 #define ETH_INTERRUPT_STATUS_MMCIS_Pos (4UL)
8196 #define ETH_INTERRUPT_STATUS_MMCIS_Msk (0x10UL)
8197 #define ETH_INTERRUPT_STATUS_MMCRXIS_Pos (5UL)
8198 #define ETH_INTERRUPT_STATUS_MMCRXIS_Msk (0x20UL)
8199 #define ETH_INTERRUPT_STATUS_MMCTXIS_Pos (6UL)
8200 #define ETH_INTERRUPT_STATUS_MMCTXIS_Msk (0x40UL)
8201 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Pos (7UL)
8202 #define ETH_INTERRUPT_STATUS_MMCRXIPIS_Msk (0x80UL)
8203 #define ETH_INTERRUPT_STATUS_TSIS_Pos (9UL)
8204 #define ETH_INTERRUPT_STATUS_TSIS_Msk (0x200UL)
8206 /* ----------------------------- ETH_INTERRUPT_MASK ----------------------------- */
8207 #define ETH_INTERRUPT_MASK_PMTIM_Pos (3UL)
8208 #define ETH_INTERRUPT_MASK_PMTIM_Msk (0x8UL)
8209 #define ETH_INTERRUPT_MASK_TSIM_Pos (9UL)
8210 #define ETH_INTERRUPT_MASK_TSIM_Msk (0x200UL)
8212 /* ---------------------------- ETH_MAC_ADDRESS0_HIGH --------------------------- */
8213 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Pos (0UL)
8214 #define ETH_MAC_ADDRESS0_HIGH_ADDRHI_Msk (0xffffUL)
8215 #define ETH_MAC_ADDRESS0_HIGH_AE_Pos (31UL)
8216 #define ETH_MAC_ADDRESS0_HIGH_AE_Msk (0x80000000UL)
8218 /* ---------------------------- ETH_MAC_ADDRESS0_LOW ---------------------------- */
8219 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Pos (0UL)
8220 #define ETH_MAC_ADDRESS0_LOW_ADDRLO_Msk (0xffffffffUL)
8222 /* ---------------------------- ETH_MAC_ADDRESS1_HIGH --------------------------- */
8223 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Pos (0UL)
8224 #define ETH_MAC_ADDRESS1_HIGH_ADDRHI_Msk (0xffffUL)
8225 #define ETH_MAC_ADDRESS1_HIGH_MBC_Pos (24UL)
8226 #define ETH_MAC_ADDRESS1_HIGH_MBC_Msk (0x3f000000UL)
8227 #define ETH_MAC_ADDRESS1_HIGH_SA_Pos (30UL)
8228 #define ETH_MAC_ADDRESS1_HIGH_SA_Msk (0x40000000UL)
8229 #define ETH_MAC_ADDRESS1_HIGH_AE_Pos (31UL)
8230 #define ETH_MAC_ADDRESS1_HIGH_AE_Msk (0x80000000UL)
8232 /* ---------------------------- ETH_MAC_ADDRESS1_LOW ---------------------------- */
8233 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Pos (0UL)
8234 #define ETH_MAC_ADDRESS1_LOW_ADDRLO_Msk (0xffffffffUL)
8236 /* ---------------------------- ETH_MAC_ADDRESS2_HIGH --------------------------- */
8237 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Pos (0UL)
8238 #define ETH_MAC_ADDRESS2_HIGH_ADDRHI_Msk (0xffffUL)
8239 #define ETH_MAC_ADDRESS2_HIGH_MBC_Pos (24UL)
8240 #define ETH_MAC_ADDRESS2_HIGH_MBC_Msk (0x3f000000UL)
8241 #define ETH_MAC_ADDRESS2_HIGH_SA_Pos (30UL)
8242 #define ETH_MAC_ADDRESS2_HIGH_SA_Msk (0x40000000UL)
8243 #define ETH_MAC_ADDRESS2_HIGH_AE_Pos (31UL)
8244 #define ETH_MAC_ADDRESS2_HIGH_AE_Msk (0x80000000UL)
8246 /* ---------------------------- ETH_MAC_ADDRESS2_LOW ---------------------------- */
8247 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Pos (0UL)
8248 #define ETH_MAC_ADDRESS2_LOW_ADDRLO_Msk (0xffffffffUL)
8250 /* ---------------------------- ETH_MAC_ADDRESS3_HIGH --------------------------- */
8251 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Pos (0UL)
8252 #define ETH_MAC_ADDRESS3_HIGH_ADDRHI_Msk (0xffffUL)
8253 #define ETH_MAC_ADDRESS3_HIGH_MBC_Pos (24UL)
8254 #define ETH_MAC_ADDRESS3_HIGH_MBC_Msk (0x3f000000UL)
8255 #define ETH_MAC_ADDRESS3_HIGH_SA_Pos (30UL)
8256 #define ETH_MAC_ADDRESS3_HIGH_SA_Msk (0x40000000UL)
8257 #define ETH_MAC_ADDRESS3_HIGH_AE_Pos (31UL)
8258 #define ETH_MAC_ADDRESS3_HIGH_AE_Msk (0x80000000UL)
8260 /* ---------------------------- ETH_MAC_ADDRESS3_LOW ---------------------------- */
8261 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Pos (0UL)
8262 #define ETH_MAC_ADDRESS3_LOW_ADDRLO_Msk (0xffffffffUL)
8264 /* ------------------------------- ETH_MMC_CONTROL ------------------------------ */
8265 #define ETH_MMC_CONTROL_CNTRST_Pos (0UL)
8266 #define ETH_MMC_CONTROL_CNTRST_Msk (0x1UL)
8267 #define ETH_MMC_CONTROL_CNTSTOPRO_Pos (1UL)
8268 #define ETH_MMC_CONTROL_CNTSTOPRO_Msk (0x2UL)
8269 #define ETH_MMC_CONTROL_RSTONRD_Pos (2UL)
8270 #define ETH_MMC_CONTROL_RSTONRD_Msk (0x4UL)
8271 #define ETH_MMC_CONTROL_CNTFREEZ_Pos (3UL)
8272 #define ETH_MMC_CONTROL_CNTFREEZ_Msk (0x8UL)
8273 #define ETH_MMC_CONTROL_CNTPRST_Pos (4UL)
8274 #define ETH_MMC_CONTROL_CNTPRST_Msk (0x10UL)
8275 #define ETH_MMC_CONTROL_CNTPRSTLVL_Pos (5UL)
8276 #define ETH_MMC_CONTROL_CNTPRSTLVL_Msk (0x20UL)
8277 #define ETH_MMC_CONTROL_UCDBC_Pos (8UL)
8278 #define ETH_MMC_CONTROL_UCDBC_Msk (0x100UL)
8280 /* -------------------------- ETH_MMC_RECEIVE_INTERRUPT ------------------------- */
8281 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Pos (0UL)
8282 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBFRMIS_Msk (0x1UL)
8283 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Pos (1UL)
8284 #define ETH_MMC_RECEIVE_INTERRUPT_RXGBOCTIS_Msk (0x2UL)
8285 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Pos (2UL)
8286 #define ETH_MMC_RECEIVE_INTERRUPT_RXGOCTIS_Msk (0x4UL)
8287 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Pos (3UL)
8288 #define ETH_MMC_RECEIVE_INTERRUPT_RXBCGFIS_Msk (0x8UL)
8289 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Pos (4UL)
8290 #define ETH_MMC_RECEIVE_INTERRUPT_RXMCGFIS_Msk (0x10UL)
8291 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Pos (5UL)
8292 #define ETH_MMC_RECEIVE_INTERRUPT_RXCRCERFIS_Msk (0x20UL)
8293 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Pos (6UL)
8294 #define ETH_MMC_RECEIVE_INTERRUPT_RXALGNERFIS_Msk (0x40UL)
8295 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Pos (7UL)
8296 #define ETH_MMC_RECEIVE_INTERRUPT_RXRUNTFIS_Msk (0x80UL)
8297 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Pos (8UL)
8298 #define ETH_MMC_RECEIVE_INTERRUPT_RXJABERFIS_Msk (0x100UL)
8299 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Pos (9UL)
8300 #define ETH_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS_Msk (0x200UL)
8301 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Pos (10UL)
8302 #define ETH_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS_Msk (0x400UL)
8303 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Pos (11UL)
8304 #define ETH_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS_Msk (0x800UL)
8305 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Pos (12UL)
8306 #define ETH_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS_Msk (0x1000UL)
8307 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Pos (13UL)
8308 #define ETH_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS_Msk (0x2000UL)
8309 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Pos (14UL)
8310 #define ETH_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS_Msk (0x4000UL)
8311 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Pos (15UL)
8312 #define ETH_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS_Msk (0x8000UL)
8313 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Pos (16UL)
8314 #define ETH_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS_Msk (0x10000UL)
8315 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Pos (17UL)
8316 #define ETH_MMC_RECEIVE_INTERRUPT_RXUCGFIS_Msk (0x20000UL)
8317 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Pos (18UL)
8318 #define ETH_MMC_RECEIVE_INTERRUPT_RXLENERFIS_Msk (0x40000UL)
8319 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Pos (19UL)
8320 #define ETH_MMC_RECEIVE_INTERRUPT_RXORANGEFIS_Msk (0x80000UL)
8321 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Pos (20UL)
8322 #define ETH_MMC_RECEIVE_INTERRUPT_RXPAUSFIS_Msk (0x100000UL)
8323 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Pos (21UL)
8324 #define ETH_MMC_RECEIVE_INTERRUPT_RXFOVFIS_Msk (0x200000UL)
8325 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Pos (22UL)
8326 #define ETH_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS_Msk (0x400000UL)
8327 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Pos (23UL)
8328 #define ETH_MMC_RECEIVE_INTERRUPT_RXWDOGFIS_Msk (0x800000UL)
8329 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Pos (24UL)
8330 #define ETH_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS_Msk (0x1000000UL)
8331 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Pos (25UL)
8332 #define ETH_MMC_RECEIVE_INTERRUPT_RXCTRLFIS_Msk (0x2000000UL)
8334 /* ------------------------- ETH_MMC_TRANSMIT_INTERRUPT ------------------------- */
8335 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Pos (0UL)
8336 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS_Msk (0x1UL)
8337 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Pos (1UL)
8338 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS_Msk (0x2UL)
8339 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Pos (2UL)
8340 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGFIS_Msk (0x4UL)
8341 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Pos (3UL)
8342 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGFIS_Msk (0x8UL)
8343 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Pos (4UL)
8344 #define ETH_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS_Msk (0x10UL)
8345 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Pos (5UL)
8346 #define ETH_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS_Msk (0x20UL)
8347 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Pos (6UL)
8348 #define ETH_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS_Msk (0x40UL)
8349 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Pos (7UL)
8350 #define ETH_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS_Msk (0x80UL)
8351 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Pos (8UL)
8352 #define ETH_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS_Msk (0x100UL)
8353 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Pos (9UL)
8354 #define ETH_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS_Msk (0x200UL)
8355 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Pos (10UL)
8356 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS_Msk (0x400UL)
8357 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Pos (11UL)
8358 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS_Msk (0x800UL)
8359 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Pos (12UL)
8360 #define ETH_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS_Msk (0x1000UL)
8361 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Pos (13UL)
8362 #define ETH_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS_Msk (0x2000UL)
8363 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Pos (14UL)
8364 #define ETH_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS_Msk (0x4000UL)
8365 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Pos (15UL)
8366 #define ETH_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS_Msk (0x8000UL)
8367 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Pos (16UL)
8368 #define ETH_MMC_TRANSMIT_INTERRUPT_TXDEFFIS_Msk (0x10000UL)
8369 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Pos (17UL)
8370 #define ETH_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS_Msk (0x20000UL)
8371 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Pos (18UL)
8372 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS_Msk (0x40000UL)
8373 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Pos (19UL)
8374 #define ETH_MMC_TRANSMIT_INTERRUPT_TXCARERFIS_Msk (0x80000UL)
8375 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Pos (20UL)
8376 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGOCTIS_Msk (0x100000UL)
8377 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Pos (21UL)
8378 #define ETH_MMC_TRANSMIT_INTERRUPT_TXGFRMIS_Msk (0x200000UL)
8379 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Pos (22UL)
8380 #define ETH_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS_Msk (0x400000UL)
8381 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Pos (23UL)
8382 #define ETH_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS_Msk (0x800000UL)
8383 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Pos (24UL)
8384 #define ETH_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS_Msk (0x1000000UL)
8385 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Pos (25UL)
8386 #define ETH_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS_Msk (0x2000000UL)
8388 /* ----------------------- ETH_MMC_RECEIVE_INTERRUPT_MASK ----------------------- */
8389 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Pos (0UL)
8390 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM_Msk (0x1UL)
8391 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Pos (1UL)
8392 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM_Msk (0x2UL)
8393 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Pos (2UL)
8394 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM_Msk (0x4UL)
8395 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Pos (3UL)
8396 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM_Msk (0x8UL)
8397 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Pos (4UL)
8398 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM_Msk (0x10UL)
8399 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Pos (5UL)
8400 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM_Msk (0x20UL)
8401 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Pos (6UL)
8402 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM_Msk (0x40UL)
8403 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Pos (7UL)
8404 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM_Msk (0x80UL)
8405 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Pos (8UL)
8406 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM_Msk (0x100UL)
8407 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Pos (9UL)
8408 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM_Msk (0x200UL)
8409 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Pos (10UL)
8410 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM_Msk (0x400UL)
8411 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Pos (11UL)
8412 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM_Msk (0x800UL)
8413 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Pos (12UL)
8414 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM_Msk (0x1000UL)
8415 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Pos (13UL)
8416 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM_Msk (0x2000UL)
8417 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Pos (14UL)
8418 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM_Msk (0x4000UL)
8419 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Pos (15UL)
8420 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM_Msk (0x8000UL)
8421 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Pos (16UL)
8422 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM_Msk (0x10000UL)
8423 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Pos (17UL)
8424 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM_Msk (0x20000UL)
8425 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Pos (18UL)
8426 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM_Msk (0x40000UL)
8427 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Pos (19UL)
8428 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM_Msk (0x80000UL)
8429 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Pos (20UL)
8430 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM_Msk (0x100000UL)
8431 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Pos (21UL)
8432 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM_Msk (0x200000UL)
8433 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Pos (22UL)
8434 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM_Msk (0x400000UL)
8435 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Pos (23UL)
8436 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM_Msk (0x800000UL)
8437 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Pos (24UL)
8438 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM_Msk (0x1000000UL)
8439 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Pos (25UL)
8440 #define ETH_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM_Msk (0x2000000UL)
8442 /* ----------------------- ETH_MMC_TRANSMIT_INTERRUPT_MASK ---------------------- */
8443 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Pos (0UL)
8444 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM_Msk (0x1UL)
8445 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Pos (1UL)
8446 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM_Msk (0x2UL)
8447 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Pos (2UL)
8448 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM_Msk (0x4UL)
8449 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Pos (3UL)
8450 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM_Msk (0x8UL)
8451 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Pos (4UL)
8452 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM_Msk (0x10UL)
8453 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Pos (5UL)
8454 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM_Msk (0x20UL)
8455 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Pos (6UL)
8456 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM_Msk (0x40UL)
8457 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Pos (7UL)
8458 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM_Msk (0x80UL)
8459 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Pos (8UL)
8460 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM_Msk (0x100UL)
8461 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Pos (9UL)
8462 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM_Msk (0x200UL)
8463 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Pos (10UL)
8464 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM_Msk (0x400UL)
8465 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Pos (11UL)
8466 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM_Msk (0x800UL)
8467 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Pos (12UL)
8468 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM_Msk (0x1000UL)
8469 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Pos (13UL)
8470 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM_Msk (0x2000UL)
8471 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Pos (14UL)
8472 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM_Msk (0x4000UL)
8473 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Pos (15UL)
8474 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM_Msk (0x8000UL)
8475 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Pos (16UL)
8476 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM_Msk (0x10000UL)
8477 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Pos (17UL)
8478 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM_Msk (0x20000UL)
8479 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Pos (18UL)
8480 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM_Msk (0x40000UL)
8481 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Pos (19UL)
8482 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM_Msk (0x80000UL)
8483 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Pos (20UL)
8484 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM_Msk (0x100000UL)
8485 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Pos (21UL)
8486 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM_Msk (0x200000UL)
8487 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Pos (22UL)
8488 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM_Msk (0x400000UL)
8489 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Pos (23UL)
8490 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM_Msk (0x800000UL)
8491 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Pos (24UL)
8492 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM_Msk (0x1000000UL)
8493 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Pos (25UL)
8494 #define ETH_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM_Msk (0x2000000UL)
8496 /* ------------------------- ETH_TX_OCTET_COUNT_GOOD_BAD ------------------------ */
8497 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Pos (0UL)
8498 #define ETH_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_Msk (0xffffffffUL)
8500 /* ------------------------- ETH_TX_FRAME_COUNT_GOOD_BAD ------------------------ */
8501 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Pos (0UL)
8502 #define ETH_TX_FRAME_COUNT_GOOD_BAD_TXFRMGB_Msk (0xffffffffUL)
8504 /* ------------------------ ETH_TX_BROADCAST_FRAMES_GOOD ------------------------ */
8505 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Pos (0UL)
8506 #define ETH_TX_BROADCAST_FRAMES_GOOD_TXBCASTG_Msk (0xffffffffUL)
8508 /* ------------------------ ETH_TX_MULTICAST_FRAMES_GOOD ------------------------ */
8509 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Pos (0UL)
8510 #define ETH_TX_MULTICAST_FRAMES_GOOD_TXMCASTG_Msk (0xffffffffUL)
8512 /* ----------------------- ETH_TX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */
8513 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Pos (0UL)
8514 #define ETH_TX_64OCTETS_FRAMES_GOOD_BAD_TX64OCTGB_Msk (0xffffffffUL)
8516 /* -------------------- ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */
8517 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Pos (0UL)
8518 #define ETH_TX_65TO127OCTETS_FRAMES_GOOD_BAD_TX65_127OCTGB_Msk (0xffffffffUL)
8520 /* -------------------- ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */
8521 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Pos (0UL)
8522 #define ETH_TX_128TO255OCTETS_FRAMES_GOOD_BAD_TX128_255OCTGB_Msk (0xffffffffUL)
8524 /* -------------------- ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */
8525 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Pos (0UL)
8526 #define ETH_TX_256TO511OCTETS_FRAMES_GOOD_BAD_TX256_511OCTGB_Msk (0xffffffffUL)
8528 /* ------------------- ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */
8529 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Pos (0UL)
8530 #define ETH_TX_512TO1023OCTETS_FRAMES_GOOD_BAD_TX512_1023OCTGB_Msk (0xffffffffUL)
8532 /* ------------------- ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */
8533 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Pos (0UL)
8534 #define ETH_TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_TX1024_MAXOCTGB_Msk (0xffffffffUL)
8536 /* ----------------------- ETH_TX_UNICAST_FRAMES_GOOD_BAD ----------------------- */
8537 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Pos (0UL)
8538 #define ETH_TX_UNICAST_FRAMES_GOOD_BAD_TXUCASTGB_Msk (0xffffffffUL)
8540 /* ---------------------- ETH_TX_MULTICAST_FRAMES_GOOD_BAD ---------------------- */
8541 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Pos (0UL)
8542 #define ETH_TX_MULTICAST_FRAMES_GOOD_BAD_TXMCASTGB_Msk (0xffffffffUL)
8544 /* ---------------------- ETH_TX_BROADCAST_FRAMES_GOOD_BAD ---------------------- */
8545 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Pos (0UL)
8546 #define ETH_TX_BROADCAST_FRAMES_GOOD_BAD_TXBCASTGB_Msk (0xffffffffUL)
8548 /* ------------------------ ETH_TX_UNDERFLOW_ERROR_FRAMES ----------------------- */
8549 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Pos (0UL)
8550 #define ETH_TX_UNDERFLOW_ERROR_FRAMES_TXUNDRFLW_Msk (0xffffffffUL)
8552 /* --------------------- ETH_TX_SINGLE_COLLISION_GOOD_FRAMES -------------------- */
8553 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Pos (0UL)
8554 #define ETH_TX_SINGLE_COLLISION_GOOD_FRAMES_TXSNGLCOLG_Msk (0xffffffffUL)
8556 /* -------------------- ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES ------------------- */
8557 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Pos (0UL)
8558 #define ETH_TX_MULTIPLE_COLLISION_GOOD_FRAMES_TXMULTCOLG_Msk (0xffffffffUL)
8560 /* --------------------------- ETH_TX_DEFERRED_FRAMES --------------------------- */
8561 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Pos (0UL)
8562 #define ETH_TX_DEFERRED_FRAMES_TXDEFRD_Msk (0xffffffffUL)
8564 /* ------------------------ ETH_TX_LATE_COLLISION_FRAMES ------------------------ */
8565 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Pos (0UL)
8566 #define ETH_TX_LATE_COLLISION_FRAMES_TXLATECOL_Msk (0xffffffffUL)
8568 /* ---------------------- ETH_TX_EXCESSIVE_COLLISION_FRAMES --------------------- */
8569 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Pos (0UL)
8570 #define ETH_TX_EXCESSIVE_COLLISION_FRAMES_TXEXSCOL_Msk (0xffffffffUL)
8572 /* ------------------------- ETH_TX_CARRIER_ERROR_FRAMES ------------------------ */
8573 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Pos (0UL)
8574 #define ETH_TX_CARRIER_ERROR_FRAMES_TXCARR_Msk (0xffffffffUL)
8576 /* --------------------------- ETH_TX_OCTET_COUNT_GOOD -------------------------- */
8577 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Pos (0UL)
8578 #define ETH_TX_OCTET_COUNT_GOOD_TXOCTG_Msk (0xffffffffUL)
8580 /* --------------------------- ETH_TX_FRAME_COUNT_GOOD -------------------------- */
8581 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Pos (0UL)
8582 #define ETH_TX_FRAME_COUNT_GOOD_TXFRMG_Msk (0xffffffffUL)
8584 /* ----------------------- ETH_TX_EXCESSIVE_DEFERRAL_ERROR ---------------------- */
8585 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Pos (0UL)
8586 #define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_Msk (0xffffffffUL)
8588 /* ----------------------------- ETH_TX_PAUSE_FRAMES ---------------------------- */
8589 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Pos (0UL)
8590 #define ETH_TX_PAUSE_FRAMES_TXPAUSE_Msk (0xffffffffUL)
8592 /* --------------------------- ETH_TX_VLAN_FRAMES_GOOD -------------------------- */
8593 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Pos (0UL)
8594 #define ETH_TX_VLAN_FRAMES_GOOD_TXVLANG_Msk (0xffffffffUL)
8596 /* -------------------------- ETH_TX_OSIZE_FRAMES_GOOD -------------------------- */
8597 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Pos (0UL)
8598 #define ETH_TX_OSIZE_FRAMES_GOOD_TXOSIZG_Msk (0xffffffffUL)
8600 /* ------------------------ ETH_RX_FRAMES_COUNT_GOOD_BAD ------------------------ */
8601 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Pos (0UL)
8602 #define ETH_RX_FRAMES_COUNT_GOOD_BAD_RXFRMGB_Msk (0xffffffffUL)
8604 /* ------------------------- ETH_RX_OCTET_COUNT_GOOD_BAD ------------------------ */
8605 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Pos (0UL)
8606 #define ETH_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_Msk (0xffffffffUL)
8608 /* --------------------------- ETH_RX_OCTET_COUNT_GOOD -------------------------- */
8609 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Pos (0UL)
8610 #define ETH_RX_OCTET_COUNT_GOOD_RXOCTG_Msk (0xffffffffUL)
8612 /* ------------------------ ETH_RX_BROADCAST_FRAMES_GOOD ------------------------ */
8613 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Pos (0UL)
8614 #define ETH_RX_BROADCAST_FRAMES_GOOD_RXBCASTG_Msk (0xffffffffUL)
8616 /* ------------------------ ETH_RX_MULTICAST_FRAMES_GOOD ------------------------ */
8617 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Pos (0UL)
8618 #define ETH_RX_MULTICAST_FRAMES_GOOD_RXMCASTG_Msk (0xffffffffUL)
8620 /* --------------------------- ETH_RX_CRC_ERROR_FRAMES -------------------------- */
8621 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Pos (0UL)
8622 #define ETH_RX_CRC_ERROR_FRAMES_RXCRCERR_Msk (0xffffffffUL)
8624 /* ------------------------ ETH_RX_ALIGNMENT_ERROR_FRAMES ----------------------- */
8625 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Pos (0UL)
8626 #define ETH_RX_ALIGNMENT_ERROR_FRAMES_RXALGNERR_Msk (0xffffffffUL)
8628 /* -------------------------- ETH_RX_RUNT_ERROR_FRAMES -------------------------- */
8629 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Pos (0UL)
8630 #define ETH_RX_RUNT_ERROR_FRAMES_RXRUNTERR_Msk (0xffffffffUL)
8632 /* ------------------------- ETH_RX_JABBER_ERROR_FRAMES ------------------------- */
8633 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Pos (0UL)
8634 #define ETH_RX_JABBER_ERROR_FRAMES_RXJABERR_Msk (0xffffffffUL)
8636 /* ------------------------ ETH_RX_UNDERSIZE_FRAMES_GOOD ------------------------ */
8637 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Pos (0UL)
8638 #define ETH_RX_UNDERSIZE_FRAMES_GOOD_RXUNDERSZG_Msk (0xffffffffUL)
8640 /* ------------------------- ETH_RX_OVERSIZE_FRAMES_GOOD ------------------------ */
8641 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Pos (0UL)
8642 #define ETH_RX_OVERSIZE_FRAMES_GOOD_RXOVERSZG_Msk (0xffffffffUL)
8644 /* ----------------------- ETH_RX_64OCTETS_FRAMES_GOOD_BAD ---------------------- */
8645 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Pos (0UL)
8646 #define ETH_RX_64OCTETS_FRAMES_GOOD_BAD_RX64OCTGB_Msk (0xffffffffUL)
8648 /* -------------------- ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD -------------------- */
8649 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Pos (0UL)
8650 #define ETH_RX_65TO127OCTETS_FRAMES_GOOD_BAD_RX65_127OCTGB_Msk (0xffffffffUL)
8652 /* -------------------- ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD ------------------- */
8653 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Pos (0UL)
8654 #define ETH_RX_128TO255OCTETS_FRAMES_GOOD_BAD_RX128_255OCTGB_Msk (0xffffffffUL)
8656 /* -------------------- ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD ------------------- */
8657 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Pos (0UL)
8658 #define ETH_RX_256TO511OCTETS_FRAMES_GOOD_BAD_RX256_511OCTGB_Msk (0xffffffffUL)
8660 /* ------------------- ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD ------------------- */
8661 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Pos (0UL)
8662 #define ETH_RX_512TO1023OCTETS_FRAMES_GOOD_BAD_RX512_1023OCTGB_Msk (0xffffffffUL)
8664 /* ------------------- ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD ------------------- */
8665 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Pos (0UL)
8666 #define ETH_RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD_RX1024_MAXOCTGB_Msk (0xffffffffUL)
8668 /* ------------------------- ETH_RX_UNICAST_FRAMES_GOOD ------------------------- */
8669 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Pos (0UL)
8670 #define ETH_RX_UNICAST_FRAMES_GOOD_RXUCASTG_Msk (0xffffffffUL)
8672 /* ------------------------- ETH_RX_LENGTH_ERROR_FRAMES ------------------------- */
8673 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Pos (0UL)
8674 #define ETH_RX_LENGTH_ERROR_FRAMES_RXLENERR_Msk (0xffffffffUL)
8676 /* ----------------------- ETH_RX_OUT_OF_RANGE_TYPE_FRAMES ---------------------- */
8677 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Pos (0UL)
8678 #define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_RXOUTOFRNG_Msk (0xffffffffUL)
8680 /* ----------------------------- ETH_RX_PAUSE_FRAMES ---------------------------- */
8681 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Pos (0UL)
8682 #define ETH_RX_PAUSE_FRAMES_RXPAUSEFRM_Msk (0xffffffffUL)
8684 /* ------------------------- ETH_RX_FIFO_OVERFLOW_FRAMES ------------------------ */
8685 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Pos (0UL)
8686 #define ETH_RX_FIFO_OVERFLOW_FRAMES_RXFIFOOVFL_Msk (0xffffffffUL)
8688 /* ------------------------- ETH_RX_VLAN_FRAMES_GOOD_BAD ------------------------ */
8689 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Pos (0UL)
8690 #define ETH_RX_VLAN_FRAMES_GOOD_BAD_RXVLANFRGB_Msk (0xffffffffUL)
8692 /* ------------------------ ETH_RX_WATCHDOG_ERROR_FRAMES ------------------------ */
8693 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Pos (0UL)
8694 #define ETH_RX_WATCHDOG_ERROR_FRAMES_RXWDGERR_Msk (0xffffffffUL)
8696 /* ------------------------- ETH_RX_RECEIVE_ERROR_FRAMES ------------------------ */
8697 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Pos (0UL)
8698 #define ETH_RX_RECEIVE_ERROR_FRAMES_RXRCVERR_Msk (0xffffffffUL)
8700 /* ------------------------- ETH_RX_CONTROL_FRAMES_GOOD ------------------------- */
8701 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Pos (0UL)
8702 #define ETH_RX_CONTROL_FRAMES_GOOD_RXCTRLG_Msk (0xffffffffUL)
8704 /* --------------------- ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK --------------------- */
8705 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Pos (0UL)
8706 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM_Msk (0x1UL)
8707 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Pos (1UL)
8708 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM_Msk (0x2UL)
8709 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Pos (2UL)
8710 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM_Msk (0x4UL)
8711 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Pos (3UL)
8712 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM_Msk (0x8UL)
8713 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Pos (4UL)
8714 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM_Msk (0x10UL)
8715 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Pos (5UL)
8716 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM_Msk (0x20UL)
8717 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Pos (6UL)
8718 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM_Msk (0x40UL)
8719 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Pos (7UL)
8720 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM_Msk (0x80UL)
8721 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Pos (8UL)
8722 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM_Msk (0x100UL)
8723 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Pos (9UL)
8724 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM_Msk (0x200UL)
8725 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Pos (10UL)
8726 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM_Msk (0x400UL)
8727 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Pos (11UL)
8728 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM_Msk (0x800UL)
8729 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Pos (12UL)
8730 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM_Msk (0x1000UL)
8731 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Pos (13UL)
8732 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM_Msk (0x2000UL)
8733 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Pos (16UL)
8734 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM_Msk (0x10000UL)
8735 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Pos (17UL)
8736 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM_Msk (0x20000UL)
8737 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Pos (18UL)
8738 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM_Msk (0x40000UL)
8739 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Pos (19UL)
8740 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM_Msk (0x80000UL)
8741 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Pos (20UL)
8742 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM_Msk (0x100000UL)
8743 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Pos (21UL)
8744 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM_Msk (0x200000UL)
8745 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Pos (22UL)
8746 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM_Msk (0x400000UL)
8747 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Pos (23UL)
8748 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM_Msk (0x800000UL)
8749 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Pos (24UL)
8750 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM_Msk (0x1000000UL)
8751 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Pos (25UL)
8752 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM_Msk (0x2000000UL)
8753 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Pos (26UL)
8754 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM_Msk (0x4000000UL)
8755 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Pos (27UL)
8756 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM_Msk (0x8000000UL)
8757 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Pos (28UL)
8758 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM_Msk (0x10000000UL)
8759 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Pos (29UL)
8760 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM_Msk (0x20000000UL)
8762 /* ------------------------ ETH_MMC_IPC_RECEIVE_INTERRUPT ----------------------- */
8763 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Pos (0UL)
8764 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS_Msk (0x1UL)
8765 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Pos (1UL)
8766 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS_Msk (0x2UL)
8767 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Pos (2UL)
8768 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS_Msk (0x4UL)
8769 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Pos (3UL)
8770 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS_Msk (0x8UL)
8771 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Pos (4UL)
8772 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS_Msk (0x10UL)
8773 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Pos (5UL)
8774 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS_Msk (0x20UL)
8775 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Pos (6UL)
8776 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS_Msk (0x40UL)
8777 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Pos (7UL)
8778 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS_Msk (0x80UL)
8779 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Pos (8UL)
8780 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS_Msk (0x100UL)
8781 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Pos (9UL)
8782 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS_Msk (0x200UL)
8783 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Pos (10UL)
8784 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS_Msk (0x400UL)
8785 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Pos (11UL)
8786 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS_Msk (0x800UL)
8787 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Pos (12UL)
8788 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS_Msk (0x1000UL)
8789 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Pos (13UL)
8790 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS_Msk (0x2000UL)
8791 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Pos (16UL)
8792 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS_Msk (0x10000UL)
8793 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Pos (17UL)
8794 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS_Msk (0x20000UL)
8795 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Pos (18UL)
8796 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS_Msk (0x40000UL)
8797 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Pos (19UL)
8798 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS_Msk (0x80000UL)
8799 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Pos (20UL)
8800 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS_Msk (0x100000UL)
8801 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Pos (21UL)
8802 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS_Msk (0x200000UL)
8803 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Pos (22UL)
8804 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS_Msk (0x400000UL)
8805 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Pos (23UL)
8806 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS_Msk (0x800000UL)
8807 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Pos (24UL)
8808 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS_Msk (0x1000000UL)
8809 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Pos (25UL)
8810 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS_Msk (0x2000000UL)
8811 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Pos (26UL)
8812 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS_Msk (0x4000000UL)
8813 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Pos (27UL)
8814 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS_Msk (0x8000000UL)
8815 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Pos (28UL)
8816 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS_Msk (0x10000000UL)
8817 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Pos (29UL)
8818 #define ETH_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS_Msk (0x20000000UL)
8820 /* --------------------------- ETH_RXIPV4_GOOD_FRAMES --------------------------- */
8821 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Pos (0UL)
8822 #define ETH_RXIPV4_GOOD_FRAMES_RXIPV4GDFRM_Msk (0xffffffffUL)
8824 /* ----------------------- ETH_RXIPV4_HEADER_ERROR_FRAMES ----------------------- */
8825 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Pos (0UL)
8826 #define ETH_RXIPV4_HEADER_ERROR_FRAMES_RXIPV4HDRERRFRM_Msk (0xffffffffUL)
8828 /* ------------------------ ETH_RXIPV4_NO_PAYLOAD_FRAMES ------------------------ */
8829 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Pos (0UL)
8830 #define ETH_RXIPV4_NO_PAYLOAD_FRAMES_RXIPV4NOPAYFRM_Msk (0xffffffffUL)
8832 /* ------------------------ ETH_RXIPV4_FRAGMENTED_FRAMES ------------------------ */
8833 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Pos (0UL)
8834 #define ETH_RXIPV4_FRAGMENTED_FRAMES_RXIPV4FRAGFRM_Msk (0xffffffffUL)
8836 /* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES ------------------ */
8837 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Pos (0UL)
8838 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_RXIPV4UDSBLFRM_Msk (0xffffffffUL)
8840 /* --------------------------- ETH_RXIPV6_GOOD_FRAMES --------------------------- */
8841 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Pos (0UL)
8842 #define ETH_RXIPV6_GOOD_FRAMES_RXIPV6GDFRM_Msk (0xffffffffUL)
8844 /* ----------------------- ETH_RXIPV6_HEADER_ERROR_FRAMES ----------------------- */
8845 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Pos (0UL)
8846 #define ETH_RXIPV6_HEADER_ERROR_FRAMES_RXIPV6HDRERRFRM_Msk (0xffffffffUL)
8848 /* ------------------------ ETH_RXIPV6_NO_PAYLOAD_FRAMES ------------------------ */
8849 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Pos (0UL)
8850 #define ETH_RXIPV6_NO_PAYLOAD_FRAMES_RXIPV6NOPAYFRM_Msk (0xffffffffUL)
8852 /* ---------------------------- ETH_RXUDP_GOOD_FRAMES --------------------------- */
8853 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Pos (0UL)
8854 #define ETH_RXUDP_GOOD_FRAMES_RXUDPGDFRM_Msk (0xffffffffUL)
8856 /* --------------------------- ETH_RXUDP_ERROR_FRAMES --------------------------- */
8857 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Pos (0UL)
8858 #define ETH_RXUDP_ERROR_FRAMES_RXUDPERRFRM_Msk (0xffffffffUL)
8860 /* ---------------------------- ETH_RXTCP_GOOD_FRAMES --------------------------- */
8861 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Pos (0UL)
8862 #define ETH_RXTCP_GOOD_FRAMES_RXTCPGDFRM_Msk (0xffffffffUL)
8864 /* --------------------------- ETH_RXTCP_ERROR_FRAMES --------------------------- */
8865 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Pos (0UL)
8866 #define ETH_RXTCP_ERROR_FRAMES_RXTCPERRFRM_Msk (0xffffffffUL)
8868 /* --------------------------- ETH_RXICMP_GOOD_FRAMES --------------------------- */
8869 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Pos (0UL)
8870 #define ETH_RXICMP_GOOD_FRAMES_RXICMPGDFRM_Msk (0xffffffffUL)
8872 /* --------------------------- ETH_RXICMP_ERROR_FRAMES -------------------------- */
8873 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Pos (0UL)
8874 #define ETH_RXICMP_ERROR_FRAMES_RXICMPERRFRM_Msk (0xffffffffUL)
8876 /* --------------------------- ETH_RXIPV4_GOOD_OCTETS --------------------------- */
8877 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Pos (0UL)
8878 #define ETH_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_Msk (0xffffffffUL)
8880 /* ----------------------- ETH_RXIPV4_HEADER_ERROR_OCTETS ----------------------- */
8881 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Pos (0UL)
8882 #define ETH_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_Msk (0xffffffffUL)
8884 /* ------------------------ ETH_RXIPV4_NO_PAYLOAD_OCTETS ------------------------ */
8885 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Pos (0UL)
8886 #define ETH_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_Msk (0xffffffffUL)
8888 /* ------------------------ ETH_RXIPV4_FRAGMENTED_OCTETS ------------------------ */
8889 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Pos (0UL)
8890 #define ETH_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_Msk (0xffffffffUL)
8892 /* ------------------- ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS ------------------- */
8893 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Pos (0UL)
8894 #define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_Msk (0xffffffffUL)
8896 /* --------------------------- ETH_RXIPV6_GOOD_OCTETS --------------------------- */
8897 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Pos (0UL)
8898 #define ETH_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_Msk (0xffffffffUL)
8900 /* ----------------------- ETH_RXIPV6_HEADER_ERROR_OCTETS ----------------------- */
8901 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Pos (0UL)
8902 #define ETH_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_Msk (0xffffffffUL)
8904 /* ------------------------ ETH_RXIPV6_NO_PAYLOAD_OCTETS ------------------------ */
8905 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Pos (0UL)
8906 #define ETH_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_Msk (0xffffffffUL)
8908 /* ---------------------------- ETH_RXUDP_GOOD_OCTETS --------------------------- */
8909 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Pos (0UL)
8910 #define ETH_RXUDP_GOOD_OCTETS_RXUDPGDOCT_Msk (0xffffffffUL)
8912 /* --------------------------- ETH_RXUDP_ERROR_OCTETS --------------------------- */
8913 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Pos (0UL)
8914 #define ETH_RXUDP_ERROR_OCTETS_RXUDPERROCT_Msk (0xffffffffUL)
8916 /* ---------------------------- ETH_RXTCP_GOOD_OCTETS --------------------------- */
8917 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Pos (0UL)
8918 #define ETH_RXTCP_GOOD_OCTETS_RXTCPGDOCT_Msk (0xffffffffUL)
8920 /* --------------------------- ETH_RXTCP_ERROR_OCTETS --------------------------- */
8921 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Pos (0UL)
8922 #define ETH_RXTCP_ERROR_OCTETS_RXTCPERROCT_Msk (0xffffffffUL)
8924 /* --------------------------- ETH_RXICMP_GOOD_OCTETS --------------------------- */
8925 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Pos (0UL)
8926 #define ETH_RXICMP_GOOD_OCTETS_RXICMPGDOCT_Msk (0xffffffffUL)
8928 /* --------------------------- ETH_RXICMP_ERROR_OCTETS -------------------------- */
8929 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Pos (0UL)
8930 #define ETH_RXICMP_ERROR_OCTETS_RXICMPERROCT_Msk (0xffffffffUL)
8932 /* ---------------------------- ETH_TIMESTAMP_CONTROL --------------------------- */
8933 #define ETH_TIMESTAMP_CONTROL_TSENA_Pos (0UL)
8934 #define ETH_TIMESTAMP_CONTROL_TSENA_Msk (0x1UL)
8935 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Pos (1UL)
8936 #define ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk (0x2UL)
8937 #define ETH_TIMESTAMP_CONTROL_TSINIT_Pos (2UL)
8938 #define ETH_TIMESTAMP_CONTROL_TSINIT_Msk (0x4UL)
8939 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Pos (3UL)
8940 #define ETH_TIMESTAMP_CONTROL_TSUPDT_Msk (0x8UL)
8941 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Pos (4UL)
8942 #define ETH_TIMESTAMP_CONTROL_TSTRIG_Msk (0x10UL)
8943 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Pos (5UL)
8944 #define ETH_TIMESTAMP_CONTROL_TSADDREG_Msk (0x20UL)
8945 #define ETH_TIMESTAMP_CONTROL_TSENALL_Pos (8UL)
8946 #define ETH_TIMESTAMP_CONTROL_TSENALL_Msk (0x100UL)
8947 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Pos (9UL)
8948 #define ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk (0x200UL)
8949 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Pos (10UL)
8950 #define ETH_TIMESTAMP_CONTROL_TSVER2ENA_Msk (0x400UL)
8951 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Pos (11UL)
8952 #define ETH_TIMESTAMP_CONTROL_TSIPENA_Msk (0x800UL)
8953 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Pos (12UL)
8954 #define ETH_TIMESTAMP_CONTROL_TSIPV6ENA_Msk (0x1000UL)
8955 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Pos (13UL)
8956 #define ETH_TIMESTAMP_CONTROL_TSIPV4ENA_Msk (0x2000UL)
8957 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Pos (14UL)
8958 #define ETH_TIMESTAMP_CONTROL_TSEVNTENA_Msk (0x4000UL)
8959 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Pos (15UL)
8960 #define ETH_TIMESTAMP_CONTROL_TSMSTRENA_Msk (0x8000UL)
8961 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Pos (16UL)
8962 #define ETH_TIMESTAMP_CONTROL_SNAPTYPSEL_Msk (0x30000UL)
8963 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Pos (18UL)
8964 #define ETH_TIMESTAMP_CONTROL_TSENMACADDR_Msk (0x40000UL)
8966 /* -------------------------- ETH_SUB_SECOND_INCREMENT -------------------------- */
8967 #define ETH_SUB_SECOND_INCREMENT_SSINC_Pos (0UL)
8968 #define ETH_SUB_SECOND_INCREMENT_SSINC_Msk (0xffUL)
8970 /* --------------------------- ETH_SYSTEM_TIME_SECONDS -------------------------- */
8971 #define ETH_SYSTEM_TIME_SECONDS_TSS_Pos (0UL)
8972 #define ETH_SYSTEM_TIME_SECONDS_TSS_Msk (0xffffffffUL)
8974 /* ------------------------- ETH_SYSTEM_TIME_NANOSECONDS ------------------------ */
8975 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Pos (0UL)
8976 #define ETH_SYSTEM_TIME_NANOSECONDS_TSSS_Msk (0x7fffffffUL)
8978 /* ----------------------- ETH_SYSTEM_TIME_SECONDS_UPDATE ----------------------- */
8979 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Pos (0UL)
8980 #define ETH_SYSTEM_TIME_SECONDS_UPDATE_TSS_Msk (0xffffffffUL)
8982 /* --------------------- ETH_SYSTEM_TIME_NANOSECONDS_UPDATE --------------------- */
8983 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Pos (0UL)
8984 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_Msk (0x7fffffffUL)
8985 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Pos (31UL)
8986 #define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_Msk (0x80000000UL)
8988 /* ---------------------------- ETH_TIMESTAMP_ADDEND ---------------------------- */
8989 #define ETH_TIMESTAMP_ADDEND_TSAR_Pos (0UL)
8990 #define ETH_TIMESTAMP_ADDEND_TSAR_Msk (0xffffffffUL)
8992 /* --------------------------- ETH_TARGET_TIME_SECONDS -------------------------- */
8993 #define ETH_TARGET_TIME_SECONDS_TSTR_Pos (0UL)
8994 #define ETH_TARGET_TIME_SECONDS_TSTR_Msk (0xffffffffUL)
8996 /* ------------------------- ETH_TARGET_TIME_NANOSECONDS ------------------------ */
8997 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Pos (0UL)
8998 #define ETH_TARGET_TIME_NANOSECONDS_TTSLO_Msk (0x7fffffffUL)
8999 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Pos (31UL)
9000 #define ETH_TARGET_TIME_NANOSECONDS_TRGTBUSY_Msk (0x80000000UL)
9002 /* --------------------- ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS -------------------- */
9003 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Pos (0UL)
9004 #define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_Msk (0xffffUL)
9006 /* ---------------------------- ETH_TIMESTAMP_STATUS ---------------------------- */
9007 #define ETH_TIMESTAMP_STATUS_TSSOVF_Pos (0UL)
9008 #define ETH_TIMESTAMP_STATUS_TSSOVF_Msk (0x1UL)
9009 #define ETH_TIMESTAMP_STATUS_TSTARGT_Pos (1UL)
9010 #define ETH_TIMESTAMP_STATUS_TSTARGT_Msk (0x2UL)
9011 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Pos (3UL)
9012 #define ETH_TIMESTAMP_STATUS_TSTRGTERR_Msk (0x8UL)
9013 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Pos (4UL)
9014 #define ETH_TIMESTAMP_STATUS_TSTARGT1_Msk (0x10UL)
9015 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Pos (5UL)
9016 #define ETH_TIMESTAMP_STATUS_TSTRGTERR1_Msk (0x20UL)
9017 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Pos (6UL)
9018 #define ETH_TIMESTAMP_STATUS_TSTARGT2_Msk (0x40UL)
9019 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Pos (7UL)
9020 #define ETH_TIMESTAMP_STATUS_TSTRGTERR2_Msk (0x80UL)
9021 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Pos (8UL)
9022 #define ETH_TIMESTAMP_STATUS_TSTARGT3_Msk (0x100UL)
9023 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Pos (9UL)
9024 #define ETH_TIMESTAMP_STATUS_TSTRGTERR3_Msk (0x200UL)
9026 /* -------------------------------- ETH_BUS_MODE -------------------------------- */
9027 #define ETH_BUS_MODE_SWR_Pos (0UL)
9028 #define ETH_BUS_MODE_SWR_Msk (0x1UL)
9029 #define ETH_BUS_MODE_DA_Pos (1UL)
9030 #define ETH_BUS_MODE_DA_Msk (0x2UL)
9031 #define ETH_BUS_MODE_DSL_Pos (2UL)
9032 #define ETH_BUS_MODE_DSL_Msk (0x7cUL)
9033 #define ETH_BUS_MODE_ATDS_Pos (7UL)
9034 #define ETH_BUS_MODE_ATDS_Msk (0x80UL)
9035 #define ETH_BUS_MODE_PBL_Pos (8UL)
9036 #define ETH_BUS_MODE_PBL_Msk (0x3f00UL)
9037 #define ETH_BUS_MODE_PR_Pos (14UL)
9038 #define ETH_BUS_MODE_PR_Msk (0xc000UL)
9039 #define ETH_BUS_MODE_FB_Pos (16UL)
9040 #define ETH_BUS_MODE_FB_Msk (0x10000UL)
9041 #define ETH_BUS_MODE_RPBL_Pos (17UL)
9042 #define ETH_BUS_MODE_RPBL_Msk (0x7e0000UL)
9043 #define ETH_BUS_MODE_USP_Pos (23UL)
9044 #define ETH_BUS_MODE_USP_Msk (0x800000UL)
9045 #define ETH_BUS_MODE_PBLX8_Pos (24UL)
9046 #define ETH_BUS_MODE_PBLX8_Msk (0x1000000UL)
9047 #define ETH_BUS_MODE_AAL_Pos (25UL)
9048 #define ETH_BUS_MODE_AAL_Msk (0x2000000UL)
9049 #define ETH_BUS_MODE_MB_Pos (26UL)
9050 #define ETH_BUS_MODE_MB_Msk (0x4000000UL)
9051 #define ETH_BUS_MODE_TXPR_Pos (27UL)
9052 #define ETH_BUS_MODE_TXPR_Msk (0x8000000UL)
9053 #define ETH_BUS_MODE_PRWG_Pos (28UL)
9054 #define ETH_BUS_MODE_PRWG_Msk (0x30000000UL)
9056 /* -------------------------- ETH_TRANSMIT_POLL_DEMAND -------------------------- */
9057 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Pos (0UL)
9058 #define ETH_TRANSMIT_POLL_DEMAND_TPD_Msk (0xffffffffUL)
9060 /* --------------------------- ETH_RECEIVE_POLL_DEMAND -------------------------- */
9061 #define ETH_RECEIVE_POLL_DEMAND_RPD_Pos (0UL)
9062 #define ETH_RECEIVE_POLL_DEMAND_RPD_Msk (0xffffffffUL)
9064 /* --------------------- ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS -------------------- */
9065 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Pos (2UL)
9066 #define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_RDESLA_32bit_Msk (0xfffffffcUL)
9068 /* -------------------- ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS -------------------- */
9069 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Pos (2UL)
9070 #define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_TDESLA_32bit_Msk (0xfffffffcUL)
9072 /* --------------------------------- ETH_STATUS --------------------------------- */
9073 #define ETH_STATUS_TI_Pos (0UL)
9074 #define ETH_STATUS_TI_Msk (0x1UL)
9075 #define ETH_STATUS_TPS_Pos (1UL)
9076 #define ETH_STATUS_TPS_Msk (0x2UL)
9077 #define ETH_STATUS_TU_Pos (2UL)
9078 #define ETH_STATUS_TU_Msk (0x4UL)
9079 #define ETH_STATUS_TJT_Pos (3UL)
9080 #define ETH_STATUS_TJT_Msk (0x8UL)
9081 #define ETH_STATUS_OVF_Pos (4UL)
9082 #define ETH_STATUS_OVF_Msk (0x10UL)
9083 #define ETH_STATUS_UNF_Pos (5UL)
9084 #define ETH_STATUS_UNF_Msk (0x20UL)
9085 #define ETH_STATUS_RI_Pos (6UL)
9086 #define ETH_STATUS_RI_Msk (0x40UL)
9087 #define ETH_STATUS_RU_Pos (7UL)
9088 #define ETH_STATUS_RU_Msk (0x80UL)
9089 #define ETH_STATUS_RPS_Pos (8UL)
9090 #define ETH_STATUS_RPS_Msk (0x100UL)
9091 #define ETH_STATUS_RWT_Pos (9UL)
9092 #define ETH_STATUS_RWT_Msk (0x200UL)
9093 #define ETH_STATUS_ETI_Pos (10UL)
9094 #define ETH_STATUS_ETI_Msk (0x400UL)
9095 #define ETH_STATUS_FBI_Pos (13UL)
9096 #define ETH_STATUS_FBI_Msk (0x2000UL)
9097 #define ETH_STATUS_ERI_Pos (14UL)
9098 #define ETH_STATUS_ERI_Msk (0x4000UL)
9099 #define ETH_STATUS_AIS_Pos (15UL)
9100 #define ETH_STATUS_AIS_Msk (0x8000UL)
9101 #define ETH_STATUS_NIS_Pos (16UL)
9102 #define ETH_STATUS_NIS_Msk (0x10000UL)
9103 #define ETH_STATUS_RS_Pos (17UL)
9104 #define ETH_STATUS_RS_Msk (0xe0000UL)
9105 #define ETH_STATUS_TS_Pos (20UL)
9106 #define ETH_STATUS_TS_Msk (0x700000UL)
9107 #define ETH_STATUS_EB_Pos (23UL)
9108 #define ETH_STATUS_EB_Msk (0x3800000UL)
9109 #define ETH_STATUS_EMI_Pos (27UL)
9110 #define ETH_STATUS_EMI_Msk (0x8000000UL)
9111 #define ETH_STATUS_EPI_Pos (28UL)
9112 #define ETH_STATUS_EPI_Msk (0x10000000UL)
9113 #define ETH_STATUS_TTI_Pos (29UL)
9114 #define ETH_STATUS_TTI_Msk (0x20000000UL)
9116 /* ----------------------------- ETH_OPERATION_MODE ----------------------------- */
9117 #define ETH_OPERATION_MODE_SR_Pos (1UL)
9118 #define ETH_OPERATION_MODE_SR_Msk (0x2UL)
9119 #define ETH_OPERATION_MODE_OSF_Pos (2UL)
9120 #define ETH_OPERATION_MODE_OSF_Msk (0x4UL)
9121 #define ETH_OPERATION_MODE_RTC_Pos (3UL)
9122 #define ETH_OPERATION_MODE_RTC_Msk (0x18UL)
9123 #define ETH_OPERATION_MODE_FUF_Pos (6UL)
9124 #define ETH_OPERATION_MODE_FUF_Msk (0x40UL)
9125 #define ETH_OPERATION_MODE_FEF_Pos (7UL)
9126 #define ETH_OPERATION_MODE_FEF_Msk (0x80UL)
9127 #define ETH_OPERATION_MODE_ST_Pos (13UL)
9128 #define ETH_OPERATION_MODE_ST_Msk (0x2000UL)
9129 #define ETH_OPERATION_MODE_TTC_Pos (14UL)
9130 #define ETH_OPERATION_MODE_TTC_Msk (0x1c000UL)
9131 #define ETH_OPERATION_MODE_FTF_Pos (20UL)
9132 #define ETH_OPERATION_MODE_FTF_Msk (0x100000UL)
9133 #define ETH_OPERATION_MODE_TSF_Pos (21UL)
9134 #define ETH_OPERATION_MODE_TSF_Msk (0x200000UL)
9135 #define ETH_OPERATION_MODE_DFF_Pos (24UL)
9136 #define ETH_OPERATION_MODE_DFF_Msk (0x1000000UL)
9137 #define ETH_OPERATION_MODE_RSF_Pos (25UL)
9138 #define ETH_OPERATION_MODE_RSF_Msk (0x2000000UL)
9139 #define ETH_OPERATION_MODE_DT_Pos (26UL)
9140 #define ETH_OPERATION_MODE_DT_Msk (0x4000000UL)
9142 /* ---------------------------- ETH_INTERRUPT_ENABLE ---------------------------- */
9143 #define ETH_INTERRUPT_ENABLE_TIE_Pos (0UL)
9144 #define ETH_INTERRUPT_ENABLE_TIE_Msk (0x1UL)
9145 #define ETH_INTERRUPT_ENABLE_TSE_Pos (1UL)
9146 #define ETH_INTERRUPT_ENABLE_TSE_Msk (0x2UL)
9147 #define ETH_INTERRUPT_ENABLE_TUE_Pos (2UL)
9148 #define ETH_INTERRUPT_ENABLE_TUE_Msk (0x4UL)
9149 #define ETH_INTERRUPT_ENABLE_TJE_Pos (3UL)
9150 #define ETH_INTERRUPT_ENABLE_TJE_Msk (0x8UL)
9151 #define ETH_INTERRUPT_ENABLE_OVE_Pos (4UL)
9152 #define ETH_INTERRUPT_ENABLE_OVE_Msk (0x10UL)
9153 #define ETH_INTERRUPT_ENABLE_UNE_Pos (5UL)
9154 #define ETH_INTERRUPT_ENABLE_UNE_Msk (0x20UL)
9155 #define ETH_INTERRUPT_ENABLE_RIE_Pos (6UL)
9156 #define ETH_INTERRUPT_ENABLE_RIE_Msk (0x40UL)
9157 #define ETH_INTERRUPT_ENABLE_RUE_Pos (7UL)
9158 #define ETH_INTERRUPT_ENABLE_RUE_Msk (0x80UL)
9159 #define ETH_INTERRUPT_ENABLE_RSE_Pos (8UL)
9160 #define ETH_INTERRUPT_ENABLE_RSE_Msk (0x100UL)
9161 #define ETH_INTERRUPT_ENABLE_RWE_Pos (9UL)
9162 #define ETH_INTERRUPT_ENABLE_RWE_Msk (0x200UL)
9163 #define ETH_INTERRUPT_ENABLE_ETE_Pos (10UL)
9164 #define ETH_INTERRUPT_ENABLE_ETE_Msk (0x400UL)
9165 #define ETH_INTERRUPT_ENABLE_FBE_Pos (13UL)
9166 #define ETH_INTERRUPT_ENABLE_FBE_Msk (0x2000UL)
9167 #define ETH_INTERRUPT_ENABLE_ERE_Pos (14UL)
9168 #define ETH_INTERRUPT_ENABLE_ERE_Msk (0x4000UL)
9169 #define ETH_INTERRUPT_ENABLE_AIE_Pos (15UL)
9170 #define ETH_INTERRUPT_ENABLE_AIE_Msk (0x8000UL)
9171 #define ETH_INTERRUPT_ENABLE_NIE_Pos (16UL)
9172 #define ETH_INTERRUPT_ENABLE_NIE_Msk (0x10000UL)
9174 /* ---------------- ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER ---------------- */
9175 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Pos (0UL)
9176 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISFRMCNT_Msk (0xffffUL)
9177 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Pos (16UL)
9178 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_MISCNTOVF_Msk (0x10000UL)
9179 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Pos (17UL)
9180 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFFRMCNT_Msk (0xffe0000UL)
9181 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Pos (28UL)
9182 #define ETH_MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER_OVFCNTOVF_Msk (0x10000000UL)
9184 /* -------------------- ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER -------------------- */
9185 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Pos (0UL)
9186 #define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_RIWT_Msk (0xffUL)
9188 /* ------------------------------- ETH_AHB_STATUS ------------------------------- */
9189 #define ETH_AHB_STATUS_AHBMS_Pos (0UL)
9190 #define ETH_AHB_STATUS_AHBMS_Msk (0x1UL)
9192 /* -------------------- ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR -------------------- */
9193 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Pos (0UL)
9194 #define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_CURTDESAPTR_Msk (0xffffffffUL)
9196 /* --------------------- ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR -------------------- */
9197 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Pos (0UL)
9198 #define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_CURRDESAPTR_Msk (0xffffffffUL)
9200 /* ------------------ ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS ------------------ */
9201 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Pos (0UL)
9202 #define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_CURTBUFAPTR_Msk (0xffffffffUL)
9204 /* ------------------- ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS ------------------ */
9205 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Pos (0UL)
9206 #define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_CURRBUFAPTR_Msk (0xffffffffUL)
9208 /* ------------------------------- ETH_HW_FEATURE ------------------------------- */
9209 #define ETH_HW_FEATURE_MIISEL_Pos (0UL)
9210 #define ETH_HW_FEATURE_MIISEL_Msk (0x1UL)
9211 #define ETH_HW_FEATURE_GMIISEL_Pos (1UL)
9212 #define ETH_HW_FEATURE_GMIISEL_Msk (0x2UL)
9213 #define ETH_HW_FEATURE_HDSEL_Pos (2UL)
9214 #define ETH_HW_FEATURE_HDSEL_Msk (0x4UL)
9215 #define ETH_HW_FEATURE_EXTHASHEN_Pos (3UL)
9216 #define ETH_HW_FEATURE_EXTHASHEN_Msk (0x8UL)
9217 #define ETH_HW_FEATURE_HASHSEL_Pos (4UL)
9218 #define ETH_HW_FEATURE_HASHSEL_Msk (0x10UL)
9219 #define ETH_HW_FEATURE_ADDMACADRSEL_Pos (5UL)
9220 #define ETH_HW_FEATURE_ADDMACADRSEL_Msk (0x20UL)
9221 #define ETH_HW_FEATURE_PCSSEL_Pos (6UL)
9222 #define ETH_HW_FEATURE_PCSSEL_Msk (0x40UL)
9223 #define ETH_HW_FEATURE_L3L4FLTREN_Pos (7UL)
9224 #define ETH_HW_FEATURE_L3L4FLTREN_Msk (0x80UL)
9225 #define ETH_HW_FEATURE_SMASEL_Pos (8UL)
9226 #define ETH_HW_FEATURE_SMASEL_Msk (0x100UL)
9227 #define ETH_HW_FEATURE_RWKSEL_Pos (9UL)
9228 #define ETH_HW_FEATURE_RWKSEL_Msk (0x200UL)
9229 #define ETH_HW_FEATURE_MGKSEL_Pos (10UL)
9230 #define ETH_HW_FEATURE_MGKSEL_Msk (0x400UL)
9231 #define ETH_HW_FEATURE_MMCSEL_Pos (11UL)
9232 #define ETH_HW_FEATURE_MMCSEL_Msk (0x800UL)
9233 #define ETH_HW_FEATURE_TSVER1SEL_Pos (12UL)
9234 #define ETH_HW_FEATURE_TSVER1SEL_Msk (0x1000UL)
9235 #define ETH_HW_FEATURE_TSVER2SEL_Pos (13UL)
9236 #define ETH_HW_FEATURE_TSVER2SEL_Msk (0x2000UL)
9237 #define ETH_HW_FEATURE_EEESEL_Pos (14UL)
9238 #define ETH_HW_FEATURE_EEESEL_Msk (0x4000UL)
9239 #define ETH_HW_FEATURE_AVSEL_Pos (15UL)
9240 #define ETH_HW_FEATURE_AVSEL_Msk (0x8000UL)
9241 #define ETH_HW_FEATURE_TXCOESEL_Pos (16UL)
9242 #define ETH_HW_FEATURE_TXCOESEL_Msk (0x10000UL)
9243 #define ETH_HW_FEATURE_RXTYP1COE_Pos (17UL)
9244 #define ETH_HW_FEATURE_RXTYP1COE_Msk (0x20000UL)
9245 #define ETH_HW_FEATURE_RXTYP2COE_Pos (18UL)
9246 #define ETH_HW_FEATURE_RXTYP2COE_Msk (0x40000UL)
9247 #define ETH_HW_FEATURE_RXFIFOSIZE_Pos (19UL)
9248 #define ETH_HW_FEATURE_RXFIFOSIZE_Msk (0x80000UL)
9249 #define ETH_HW_FEATURE_RXCHCNT_Pos (20UL)
9250 #define ETH_HW_FEATURE_RXCHCNT_Msk (0x300000UL)
9251 #define ETH_HW_FEATURE_TXCHCNT_Pos (22UL)
9252 #define ETH_HW_FEATURE_TXCHCNT_Msk (0xc00000UL)
9253 #define ETH_HW_FEATURE_ENHDESSEL_Pos (24UL)
9254 #define ETH_HW_FEATURE_ENHDESSEL_Msk (0x1000000UL)
9255 #define ETH_HW_FEATURE_INTTSEN_Pos (25UL)
9256 #define ETH_HW_FEATURE_INTTSEN_Msk (0x2000000UL)
9257 #define ETH_HW_FEATURE_FLEXIPPSEN_Pos (26UL)
9258 #define ETH_HW_FEATURE_FLEXIPPSEN_Msk (0x4000000UL)
9259 #define ETH_HW_FEATURE_SAVLANINS_Pos (27UL)
9260 #define ETH_HW_FEATURE_SAVLANINS_Msk (0x8000000UL)
9261 #define ETH_HW_FEATURE_ACTPHYIF_Pos (28UL)
9262 #define ETH_HW_FEATURE_ACTPHYIF_Msk (0x70000000UL)
9265 /* ================================================================================ */
9266 /* ================ struct 'ECAT0_CON' Position & Mask ================ */
9267 /* ================================================================================ */
9268 
9269 
9270 /* -------------------------------- ECAT0_CON_CON ------------------------------- */
9271 #define ECAT0_CON_CON_ECATRSTEN_Pos (0UL)
9272 #define ECAT0_CON_CON_ECATRSTEN_Msk (0x1UL)
9273 #define ECAT0_CON_CON_LATCHIN0SEL_Pos (8UL)
9274 #define ECAT0_CON_CON_LATCHIN0SEL_Msk (0x300UL)
9275 #define ECAT0_CON_CON_LATCHIN0_Pos (11UL)
9276 #define ECAT0_CON_CON_LATCHIN0_Msk (0x800UL)
9277 #define ECAT0_CON_CON_LATCHIN1SEL_Pos (12UL)
9278 #define ECAT0_CON_CON_LATCHIN1SEL_Msk (0x3000UL)
9279 #define ECAT0_CON_CON_LATCHIN1_Pos (15UL)
9280 #define ECAT0_CON_CON_LATCHIN1_Msk (0x8000UL)
9281 #define ECAT0_CON_CON_PHYOFFSET_Pos (16UL)
9282 #define ECAT0_CON_CON_PHYOFFSET_Msk (0x1f0000UL)
9283 #define ECAT0_CON_CON_MDIO_Pos (22UL)
9284 #define ECAT0_CON_CON_MDIO_Msk (0xc00000UL)
9286 /* ------------------------------- ECAT0_CON_CONP0 ------------------------------ */
9287 #define ECAT0_CON_CONP0_RXD0_Pos (0UL)
9288 #define ECAT0_CON_CONP0_RXD0_Msk (0x3UL)
9289 #define ECAT0_CON_CONP0_RXD1_Pos (2UL)
9290 #define ECAT0_CON_CONP0_RXD1_Msk (0xcUL)
9291 #define ECAT0_CON_CONP0_RXD2_Pos (4UL)
9292 #define ECAT0_CON_CONP0_RXD2_Msk (0x30UL)
9293 #define ECAT0_CON_CONP0_RXD3_Pos (6UL)
9294 #define ECAT0_CON_CONP0_RXD3_Msk (0xc0UL)
9295 #define ECAT0_CON_CONP0_RX_ERR_Pos (8UL)
9296 #define ECAT0_CON_CONP0_RX_ERR_Msk (0x300UL)
9297 #define ECAT0_CON_CONP0_RX_DV_Pos (10UL)
9298 #define ECAT0_CON_CONP0_RX_DV_Msk (0xc00UL)
9299 #define ECAT0_CON_CONP0_RX_CLK_Pos (12UL)
9300 #define ECAT0_CON_CONP0_RX_CLK_Msk (0x3000UL)
9301 #define ECAT0_CON_CONP0_LINK_Pos (16UL)
9302 #define ECAT0_CON_CONP0_LINK_Msk (0x30000UL)
9303 #define ECAT0_CON_CONP0_TX_CLK_Pos (28UL)
9304 #define ECAT0_CON_CONP0_TX_CLK_Msk (0x30000000UL)
9305 #define ECAT0_CON_CONP0_TX_SHIFT_Pos (30UL)
9306 #define ECAT0_CON_CONP0_TX_SHIFT_Msk (0xc0000000UL)
9308 /* ------------------------------- ECAT0_CON_CONP1 ------------------------------ */
9309 #define ECAT0_CON_CONP1_RXD0_Pos (0UL)
9310 #define ECAT0_CON_CONP1_RXD0_Msk (0x3UL)
9311 #define ECAT0_CON_CONP1_RXD1_Pos (2UL)
9312 #define ECAT0_CON_CONP1_RXD1_Msk (0xcUL)
9313 #define ECAT0_CON_CONP1_RXD2_Pos (4UL)
9314 #define ECAT0_CON_CONP1_RXD2_Msk (0x30UL)
9315 #define ECAT0_CON_CONP1_RXD3_Pos (6UL)
9316 #define ECAT0_CON_CONP1_RXD3_Msk (0xc0UL)
9317 #define ECAT0_CON_CONP1_RX_ERR_Pos (8UL)
9318 #define ECAT0_CON_CONP1_RX_ERR_Msk (0x300UL)
9319 #define ECAT0_CON_CONP1_RX_DV_Pos (10UL)
9320 #define ECAT0_CON_CONP1_RX_DV_Msk (0xc00UL)
9321 #define ECAT0_CON_CONP1_RX_CLK_Pos (12UL)
9322 #define ECAT0_CON_CONP1_RX_CLK_Msk (0x3000UL)
9323 #define ECAT0_CON_CONP1_LINK_Pos (16UL)
9324 #define ECAT0_CON_CONP1_LINK_Msk (0x30000UL)
9325 #define ECAT0_CON_CONP1_TX_CLK_Pos (28UL)
9326 #define ECAT0_CON_CONP1_TX_CLK_Msk (0x30000000UL)
9327 #define ECAT0_CON_CONP1_TX_SHIFT_Pos (30UL)
9328 #define ECAT0_CON_CONP1_TX_SHIFT_Msk (0xc0000000UL)
9331 /* ================================================================================ */
9332 /* ================ Group 'ECAT' Position & Mask ================ */
9333 /* ================================================================================ */
9334 
9335 
9336 /* ---------------------------------- ECAT_TYPE --------------------------------- */
9337 #define ECAT_TYPE_Type_Pos (0UL)
9338 #define ECAT_TYPE_Type_Msk (0xffUL)
9340 /* -------------------------------- ECAT_REVISION ------------------------------- */
9341 #define ECAT_REVISION_Revision_Pos (0UL)
9342 #define ECAT_REVISION_Revision_Msk (0xffUL)
9344 /* --------------------------------- ECAT_BUILD --------------------------------- */
9345 #define ECAT_BUILD_BUILD_Pos (0UL)
9346 #define ECAT_BUILD_BUILD_Msk (0xffffUL)
9348 /* -------------------------------- ECAT_FMMU_NUM ------------------------------- */
9349 #define ECAT_FMMU_NUM_NUM_FMMU_Pos (0UL)
9350 #define ECAT_FMMU_NUM_NUM_FMMU_Msk (0xffUL)
9352 /* ------------------------------ ECAT_SYNC_MANAGER ----------------------------- */
9353 #define ECAT_SYNC_MANAGER_NUM_SM_Pos (0UL)
9354 #define ECAT_SYNC_MANAGER_NUM_SM_Msk (0xffUL)
9356 /* -------------------------------- ECAT_RAM_SIZE ------------------------------- */
9357 #define ECAT_RAM_SIZE_RAM_Size_Pos (0UL)
9358 #define ECAT_RAM_SIZE_RAM_Size_Msk (0xffUL)
9360 /* ------------------------------- ECAT_PORT_DESC ------------------------------- */
9361 #define ECAT_PORT_DESC_Port0_Pos (0UL)
9362 #define ECAT_PORT_DESC_Port0_Msk (0x3UL)
9363 #define ECAT_PORT_DESC_Port1_Pos (2UL)
9364 #define ECAT_PORT_DESC_Port1_Msk (0xcUL)
9365 #define ECAT_PORT_DESC_Port2_Pos (4UL)
9366 #define ECAT_PORT_DESC_Port2_Msk (0x30UL)
9367 #define ECAT_PORT_DESC_Port3_Pos (6UL)
9368 #define ECAT_PORT_DESC_Port3_Msk (0xc0UL)
9370 /* -------------------------------- ECAT_FEATURE -------------------------------- */
9371 #define ECAT_FEATURE_FMMU_Pos (0UL)
9372 #define ECAT_FEATURE_FMMU_Msk (0x1UL)
9373 #define ECAT_FEATURE_CLKS_Pos (2UL)
9374 #define ECAT_FEATURE_CLKS_Msk (0x4UL)
9375 #define ECAT_FEATURE_CLKS_W_Pos (3UL)
9376 #define ECAT_FEATURE_CLKS_W_Msk (0x8UL)
9377 #define ECAT_FEATURE_LJ_EBUS_Pos (4UL)
9378 #define ECAT_FEATURE_LJ_EBUS_Msk (0x10UL)
9379 #define ECAT_FEATURE_ELD_EBUS_Pos (5UL)
9380 #define ECAT_FEATURE_ELD_EBUS_Msk (0x20UL)
9381 #define ECAT_FEATURE_ELD_MII_Pos (6UL)
9382 #define ECAT_FEATURE_ELD_MII_Msk (0x40UL)
9383 #define ECAT_FEATURE_SH_FCSE_Pos (7UL)
9384 #define ECAT_FEATURE_SH_FCSE_Msk (0x80UL)
9385 #define ECAT_FEATURE_EDC_SYNCA_Pos (8UL)
9386 #define ECAT_FEATURE_EDC_SYNCA_Msk (0x100UL)
9387 #define ECAT_FEATURE_LRW_CS_Pos (9UL)
9388 #define ECAT_FEATURE_LRW_CS_Msk (0x200UL)
9389 #define ECAT_FEATURE_RW_CS_Pos (10UL)
9390 #define ECAT_FEATURE_RW_CS_Msk (0x400UL)
9391 #define ECAT_FEATURE_FX_CONF_Pos (11UL)
9392 #define ECAT_FEATURE_FX_CONF_Msk (0x800UL)
9394 /* ------------------------------ ECAT_STATION_ADR ------------------------------ */
9395 #define ECAT_STATION_ADR_NODE_ADDR_Pos (0UL)
9396 #define ECAT_STATION_ADR_NODE_ADDR_Msk (0xffffUL)
9398 /* ----------------------------- ECAT_STATION_ALIAS ----------------------------- */
9399 #define ECAT_STATION_ALIAS_ALIAS_ADDR_Pos (0UL)
9400 #define ECAT_STATION_ALIAS_ALIAS_ADDR_Msk (0xffffUL)
9402 /* ----------------------------- ECAT_WR_REG_ENABLE ----------------------------- */
9403 #define ECAT_WR_REG_ENABLE_WR_REG_EN_Pos (0UL)
9404 #define ECAT_WR_REG_ENABLE_WR_REG_EN_Msk (0x1UL)
9406 /* ----------------------------- ECAT_WR_REG_PROTECT ---------------------------- */
9407 #define ECAT_WR_REG_PROTECT_WR_REG_P_Pos (0UL)
9408 #define ECAT_WR_REG_PROTECT_WR_REG_P_Msk (0x1UL)
9410 /* ----------------------------- ECAT_ESC_WR_ENABLE ----------------------------- */
9411 #define ECAT_ESC_WR_ENABLE_ESC_WR_PROT_Pos (0UL)
9412 #define ECAT_ESC_WR_ENABLE_ESC_WR_PROT_Msk (0x1UL)
9414 /* ----------------------------- ECAT_ESC_WR_PROTECT ---------------------------- */
9415 #define ECAT_ESC_WR_PROTECT_ESC_WR_PROT_Pos (0UL)
9416 #define ECAT_ESC_WR_PROTECT_ESC_WR_PROT_Msk (0x1UL)
9418 /* ----------------------------- ECAT_ESC_RESET_ECAT ---------------------------- */
9419 #define ECAT_ESC_RESET_ECAT_RESET_CMD_WRITEMode_Pos (0UL)
9420 #define ECAT_ESC_RESET_ECAT_RESET_CMD_WRITEMode_Msk (0xffUL)
9422 /* ----------------------------- ECAT_ESC_RESET_ECAT ---------------------------- */
9423 #define ECAT_ESC_RESET_ECAT_RESET_CMD_STATE_READMode_Pos (0UL)
9424 #define ECAT_ESC_RESET_ECAT_RESET_CMD_STATE_READMode_Msk (0x3UL)
9426 /* ----------------------------- ECAT_ESC_RESET_PDI ----------------------------- */
9427 #define ECAT_ESC_RESET_PDI_RESET_CMD_WRITEMode_Pos (0UL)
9428 #define ECAT_ESC_RESET_PDI_RESET_CMD_WRITEMode_Msk (0xffUL)
9430 /* ----------------------------- ECAT_ESC_RESET_PDI ----------------------------- */
9431 #define ECAT_ESC_RESET_PDI_RESET_CMD_STATE_READMode_Pos (0UL)
9432 #define ECAT_ESC_RESET_PDI_RESET_CMD_STATE_READMode_Msk (0x3UL)
9434 /* ----------------------------- ECAT_ESC_DL_CONTROL ---------------------------- */
9435 #define ECAT_ESC_DL_CONTROL_FR_Pos (0UL)
9436 #define ECAT_ESC_DL_CONTROL_FR_Msk (0x1UL)
9437 #define ECAT_ESC_DL_CONTROL_TEMP_Pos (1UL)
9438 #define ECAT_ESC_DL_CONTROL_TEMP_Msk (0x2UL)
9439 #define ECAT_ESC_DL_CONTROL_LP0_Pos (8UL)
9440 #define ECAT_ESC_DL_CONTROL_LP0_Msk (0x300UL)
9441 #define ECAT_ESC_DL_CONTROL_LP1_Pos (10UL)
9442 #define ECAT_ESC_DL_CONTROL_LP1_Msk (0xc00UL)
9443 #define ECAT_ESC_DL_CONTROL_LP2_Pos (12UL)
9444 #define ECAT_ESC_DL_CONTROL_LP2_Msk (0x3000UL)
9445 #define ECAT_ESC_DL_CONTROL_LP3_Pos (14UL)
9446 #define ECAT_ESC_DL_CONTROL_LP3_Msk (0xc000UL)
9447 #define ECAT_ESC_DL_CONTROL_RX_FIFO_SIZE_Pos (16UL)
9448 #define ECAT_ESC_DL_CONTROL_RX_FIFO_SIZE_Msk (0x70000UL)
9449 #define ECAT_ESC_DL_CONTROL_LJ_Pos (19UL)
9450 #define ECAT_ESC_DL_CONTROL_LJ_Msk (0x80000UL)
9451 #define ECAT_ESC_DL_CONTROL_RLD_ST_Pos (22UL)
9452 #define ECAT_ESC_DL_CONTROL_RLD_ST_Msk (0x400000UL)
9453 #define ECAT_ESC_DL_CONTROL_S_ALIAS_Pos (24UL)
9454 #define ECAT_ESC_DL_CONTROL_S_ALIAS_Msk (0x1000000UL)
9456 /* --------------------------- ECAT_PHYSICAL_RW_OFFSET -------------------------- */
9457 #define ECAT_PHYSICAL_RW_OFFSET_OFFSET_Pos (0UL)
9458 #define ECAT_PHYSICAL_RW_OFFSET_OFFSET_Msk (0xffffUL)
9460 /* ----------------------------- ECAT_ESC_DL_STATUS ----------------------------- */
9461 #define ECAT_ESC_DL_STATUS_PDI_EEPROM_Pos (0UL)
9462 #define ECAT_ESC_DL_STATUS_PDI_EEPROM_Msk (0x1UL)
9463 #define ECAT_ESC_DL_STATUS_PDI_WDT_S_Pos (1UL)
9464 #define ECAT_ESC_DL_STATUS_PDI_WDT_S_Msk (0x2UL)
9465 #define ECAT_ESC_DL_STATUS_ELD_Pos (2UL)
9466 #define ECAT_ESC_DL_STATUS_ELD_Msk (0x4UL)
9467 #define ECAT_ESC_DL_STATUS_LINK_P0_Pos (4UL)
9468 #define ECAT_ESC_DL_STATUS_LINK_P0_Msk (0x10UL)
9469 #define ECAT_ESC_DL_STATUS_LINK_P1_Pos (5UL)
9470 #define ECAT_ESC_DL_STATUS_LINK_P1_Msk (0x20UL)
9471 #define ECAT_ESC_DL_STATUS_LINK_P2_Pos (6UL)
9472 #define ECAT_ESC_DL_STATUS_LINK_P2_Msk (0x40UL)
9473 #define ECAT_ESC_DL_STATUS_LINK_P3_Pos (7UL)
9474 #define ECAT_ESC_DL_STATUS_LINK_P3_Msk (0x80UL)
9475 #define ECAT_ESC_DL_STATUS_LP0_Pos (8UL)
9476 #define ECAT_ESC_DL_STATUS_LP0_Msk (0x100UL)
9477 #define ECAT_ESC_DL_STATUS_COM_P0_Pos (9UL)
9478 #define ECAT_ESC_DL_STATUS_COM_P0_Msk (0x200UL)
9479 #define ECAT_ESC_DL_STATUS_LP1_Pos (10UL)
9480 #define ECAT_ESC_DL_STATUS_LP1_Msk (0x400UL)
9481 #define ECAT_ESC_DL_STATUS_COM_P1_Pos (11UL)
9482 #define ECAT_ESC_DL_STATUS_COM_P1_Msk (0x800UL)
9483 #define ECAT_ESC_DL_STATUS_LP2_Pos (12UL)
9484 #define ECAT_ESC_DL_STATUS_LP2_Msk (0x1000UL)
9485 #define ECAT_ESC_DL_STATUS_COM_P2_Pos (13UL)
9486 #define ECAT_ESC_DL_STATUS_COM_P2_Msk (0x2000UL)
9487 #define ECAT_ESC_DL_STATUS_LP3_Pos (14UL)
9488 #define ECAT_ESC_DL_STATUS_LP3_Msk (0x4000UL)
9489 #define ECAT_ESC_DL_STATUS_COM_P3_Pos (15UL)
9490 #define ECAT_ESC_DL_STATUS_COM_P3_Msk (0x8000UL)
9492 /* ------------------------------- ECAT_AL_CONTROL ------------------------------ */
9493 #define ECAT_AL_CONTROL_IST_Pos (0UL)
9494 #define ECAT_AL_CONTROL_IST_Msk (0xfUL)
9495 #define ECAT_AL_CONTROL_EIA_Pos (4UL)
9496 #define ECAT_AL_CONTROL_EIA_Msk (0x10UL)
9497 #define ECAT_AL_CONTROL_DID_Pos (5UL)
9498 #define ECAT_AL_CONTROL_DID_Msk (0x20UL)
9500 /* ------------------------------- ECAT_AL_STATUS ------------------------------- */
9501 #define ECAT_AL_STATUS_STATE_Pos (0UL)
9502 #define ECAT_AL_STATUS_STATE_Msk (0xfUL)
9503 #define ECAT_AL_STATUS_ERRI_Pos (4UL)
9504 #define ECAT_AL_STATUS_ERRI_Msk (0x10UL)
9505 #define ECAT_AL_STATUS_DID_Pos (5UL)
9506 #define ECAT_AL_STATUS_DID_Msk (0x20UL)
9508 /* ----------------------------- ECAT_AL_STATUS_CODE ---------------------------- */
9509 #define ECAT_AL_STATUS_CODE_AL_S_CODE_Pos (0UL)
9510 #define ECAT_AL_STATUS_CODE_AL_S_CODE_Msk (0xffffUL)
9512 /* -------------------------------- ECAT_RUN_LED -------------------------------- */
9513 #define ECAT_RUN_LED_LED_CODE_Pos (0UL)
9514 #define ECAT_RUN_LED_LED_CODE_Msk (0xfUL)
9515 #define ECAT_RUN_LED_EN_OVERR_Pos (4UL)
9516 #define ECAT_RUN_LED_EN_OVERR_Msk (0x10UL)
9518 /* -------------------------------- ECAT_ERR_LED -------------------------------- */
9519 #define ECAT_ERR_LED_LED_CODE_Pos (0UL)
9520 #define ECAT_ERR_LED_LED_CODE_Msk (0xfUL)
9521 #define ECAT_ERR_LED_EN_OVERR_Pos (4UL)
9522 #define ECAT_ERR_LED_EN_OVERR_Msk (0x10UL)
9524 /* ------------------------------ ECAT_PDI_CONTROL ------------------------------ */
9525 #define ECAT_PDI_CONTROL_PDI_Pos (0UL)
9526 #define ECAT_PDI_CONTROL_PDI_Msk (0xffUL)
9528 /* ------------------------------- ECAT_ESC_CONFIG ------------------------------ */
9529 #define ECAT_ESC_CONFIG_EMUL_Pos (0UL)
9530 #define ECAT_ESC_CONFIG_EMUL_Msk (0x1UL)
9531 #define ECAT_ESC_CONFIG_EHLD_Pos (1UL)
9532 #define ECAT_ESC_CONFIG_EHLD_Msk (0x2UL)
9533 #define ECAT_ESC_CONFIG_CLKS_OUT_Pos (2UL)
9534 #define ECAT_ESC_CONFIG_CLKS_OUT_Msk (0x4UL)
9535 #define ECAT_ESC_CONFIG_CLKS_IN_Pos (3UL)
9536 #define ECAT_ESC_CONFIG_CLKS_IN_Msk (0x8UL)
9537 #define ECAT_ESC_CONFIG_EHLD_P0_Pos (4UL)
9538 #define ECAT_ESC_CONFIG_EHLD_P0_Msk (0x10UL)
9539 #define ECAT_ESC_CONFIG_EHLD_P1_Pos (5UL)
9540 #define ECAT_ESC_CONFIG_EHLD_P1_Msk (0x20UL)
9541 #define ECAT_ESC_CONFIG_EHLD_P2_Pos (6UL)
9542 #define ECAT_ESC_CONFIG_EHLD_P2_Msk (0x40UL)
9543 #define ECAT_ESC_CONFIG_EHLD_P3_Pos (7UL)
9544 #define ECAT_ESC_CONFIG_EHLD_P3_Msk (0x80UL)
9546 /* ------------------------------- ECAT_PDI_CONFIG ------------------------------ */
9547 #define ECAT_PDI_CONFIG_BUS_CLK_Pos (0UL)
9548 #define ECAT_PDI_CONFIG_BUS_CLK_Msk (0x1fUL)
9549 #define ECAT_PDI_CONFIG_OC_BUS_Pos (5UL)
9550 #define ECAT_PDI_CONFIG_OC_BUS_Msk (0xe0UL)
9552 /* --------------------------- ECAT_SYNC_LATCH_CONFIG --------------------------- */
9553 #define ECAT_SYNC_LATCH_CONFIG_SYNC0_POL_Pos (0UL)
9554 #define ECAT_SYNC_LATCH_CONFIG_SYNC0_POL_Msk (0x3UL)
9555 #define ECAT_SYNC_LATCH_CONFIG_SL0_CNF_Pos (2UL)
9556 #define ECAT_SYNC_LATCH_CONFIG_SL0_CNF_Msk (0x4UL)
9557 #define ECAT_SYNC_LATCH_CONFIG_S0_MAP_Pos (3UL)
9558 #define ECAT_SYNC_LATCH_CONFIG_S0_MAP_Msk (0x8UL)
9559 #define ECAT_SYNC_LATCH_CONFIG_SYNC1_POL_Pos (4UL)
9560 #define ECAT_SYNC_LATCH_CONFIG_SYNC1_POL_Msk (0x30UL)
9561 #define ECAT_SYNC_LATCH_CONFIG_SL1_CNF_Pos (6UL)
9562 #define ECAT_SYNC_LATCH_CONFIG_SL1_CNF_Msk (0x40UL)
9563 #define ECAT_SYNC_LATCH_CONFIG_S1_MAP_Pos (7UL)
9564 #define ECAT_SYNC_LATCH_CONFIG_S1_MAP_Msk (0x80UL)
9566 /* ----------------------------- ECAT_PDI_EXT_CONFIG ---------------------------- */
9567 #define ECAT_PDI_EXT_CONFIG_R_Pref_Pos (0UL)
9568 #define ECAT_PDI_EXT_CONFIG_R_Pref_Msk (0x3UL)
9569 #define ECAT_PDI_EXT_CONFIG_SUB_TYPE_Pos (8UL)
9570 #define ECAT_PDI_EXT_CONFIG_SUB_TYPE_Msk (0x700UL)
9572 /* ------------------------------- ECAT_EVENT_MASK ------------------------------ */
9573 #define ECAT_EVENT_MASK_DC_LE_MASK_Pos (0UL)
9574 #define ECAT_EVENT_MASK_DC_LE_MASK_Msk (0x1UL)
9575 #define ECAT_EVENT_MASK_DL_SE_MASK_Pos (2UL)
9576 #define ECAT_EVENT_MASK_DL_SE_MASK_Msk (0x4UL)
9577 #define ECAT_EVENT_MASK_AL_SE_MASK_Pos (3UL)
9578 #define ECAT_EVENT_MASK_AL_SE_MASK_Msk (0x8UL)
9579 #define ECAT_EVENT_MASK_MIR_0_MASK_Pos (4UL)
9580 #define ECAT_EVENT_MASK_MIR_0_MASK_Msk (0x10UL)
9581 #define ECAT_EVENT_MASK_MIR_1_MASK_Pos (5UL)
9582 #define ECAT_EVENT_MASK_MIR_1_MASK_Msk (0x20UL)
9583 #define ECAT_EVENT_MASK_MIR_2_MASK_Pos (6UL)
9584 #define ECAT_EVENT_MASK_MIR_2_MASK_Msk (0x40UL)
9585 #define ECAT_EVENT_MASK_MIR_3_MASK_Pos (7UL)
9586 #define ECAT_EVENT_MASK_MIR_3_MASK_Msk (0x80UL)
9587 #define ECAT_EVENT_MASK_MIR_4_MASK_Pos (8UL)
9588 #define ECAT_EVENT_MASK_MIR_4_MASK_Msk (0x100UL)
9589 #define ECAT_EVENT_MASK_MIR_5_MASK_Pos (9UL)
9590 #define ECAT_EVENT_MASK_MIR_5_MASK_Msk (0x200UL)
9591 #define ECAT_EVENT_MASK_MIR_6_MASK_Pos (10UL)
9592 #define ECAT_EVENT_MASK_MIR_6_MASK_Msk (0x400UL)
9593 #define ECAT_EVENT_MASK_MIR_7_MASK_Pos (11UL)
9594 #define ECAT_EVENT_MASK_MIR_7_MASK_Msk (0x800UL)
9596 /* ----------------------------- ECAT_AL_EVENT_MASK ----------------------------- */
9597 #define ECAT_AL_EVENT_MASK_AL_CE_MASK_Pos (0UL)
9598 #define ECAT_AL_EVENT_MASK_AL_CE_MASK_Msk (0x1UL)
9599 #define ECAT_AL_EVENT_MASK_DC_LE_MASK_Pos (1UL)
9600 #define ECAT_AL_EVENT_MASK_DC_LE_MASK_Msk (0x2UL)
9601 #define ECAT_AL_EVENT_MASK_ST_S0_MASK_Pos (2UL)
9602 #define ECAT_AL_EVENT_MASK_ST_S0_MASK_Msk (0x4UL)
9603 #define ECAT_AL_EVENT_MASK_ST_S1_MASK_Pos (3UL)
9604 #define ECAT_AL_EVENT_MASK_ST_S1_MASK_Msk (0x8UL)
9605 #define ECAT_AL_EVENT_MASK_SM_A_MASK_Pos (4UL)
9606 #define ECAT_AL_EVENT_MASK_SM_A_MASK_Msk (0x10UL)
9607 #define ECAT_AL_EVENT_MASK_EEP_E_MASK_Pos (5UL)
9608 #define ECAT_AL_EVENT_MASK_EEP_E_MASK_Msk (0x20UL)
9609 #define ECAT_AL_EVENT_MASK_WP_D_MASK_Pos (6UL)
9610 #define ECAT_AL_EVENT_MASK_WP_D_MASK_Msk (0x40UL)
9611 #define ECAT_AL_EVENT_MASK_SMI_0_MASK_Pos (8UL)
9612 #define ECAT_AL_EVENT_MASK_SMI_0_MASK_Msk (0x100UL)
9613 #define ECAT_AL_EVENT_MASK_SMI_1_MASK_Pos (9UL)
9614 #define ECAT_AL_EVENT_MASK_SMI_1_MASK_Msk (0x200UL)
9615 #define ECAT_AL_EVENT_MASK_SMI_2_MASK_Pos (10UL)
9616 #define ECAT_AL_EVENT_MASK_SMI_2_MASK_Msk (0x400UL)
9617 #define ECAT_AL_EVENT_MASK_SMI_3_MASK_Pos (11UL)
9618 #define ECAT_AL_EVENT_MASK_SMI_3_MASK_Msk (0x800UL)
9619 #define ECAT_AL_EVENT_MASK_SMI_4_MASK_Pos (12UL)
9620 #define ECAT_AL_EVENT_MASK_SMI_4_MASK_Msk (0x1000UL)
9621 #define ECAT_AL_EVENT_MASK_SMI_5_MASK_Pos (13UL)
9622 #define ECAT_AL_EVENT_MASK_SMI_5_MASK_Msk (0x2000UL)
9623 #define ECAT_AL_EVENT_MASK_SMI_6_MASK_Pos (14UL)
9624 #define ECAT_AL_EVENT_MASK_SMI_6_MASK_Msk (0x4000UL)
9625 #define ECAT_AL_EVENT_MASK_SMI_7_MASK_Pos (15UL)
9626 #define ECAT_AL_EVENT_MASK_SMI_7_MASK_Msk (0x8000UL)
9627 #define ECAT_AL_EVENT_MASK_SMI_8_MASK_Pos (16UL)
9628 #define ECAT_AL_EVENT_MASK_SMI_8_MASK_Msk (0x10000UL)
9629 #define ECAT_AL_EVENT_MASK_SMI_9_MASK_Pos (17UL)
9630 #define ECAT_AL_EVENT_MASK_SMI_9_MASK_Msk (0x20000UL)
9631 #define ECAT_AL_EVENT_MASK_SMI_10_MASK_Pos (18UL)
9632 #define ECAT_AL_EVENT_MASK_SMI_10_MASK_Msk (0x40000UL)
9633 #define ECAT_AL_EVENT_MASK_SMI_11_MASK_Pos (19UL)
9634 #define ECAT_AL_EVENT_MASK_SMI_11_MASK_Msk (0x80000UL)
9635 #define ECAT_AL_EVENT_MASK_SMI_12_MASK_Pos (20UL)
9636 #define ECAT_AL_EVENT_MASK_SMI_12_MASK_Msk (0x100000UL)
9637 #define ECAT_AL_EVENT_MASK_SMI_13_MASK_Pos (21UL)
9638 #define ECAT_AL_EVENT_MASK_SMI_13_MASK_Msk (0x200000UL)
9639 #define ECAT_AL_EVENT_MASK_SMI_14_MASK_Pos (22UL)
9640 #define ECAT_AL_EVENT_MASK_SMI_14_MASK_Msk (0x400000UL)
9641 #define ECAT_AL_EVENT_MASK_SMI_15_MASK_Pos (23UL)
9642 #define ECAT_AL_EVENT_MASK_SMI_15_MASK_Msk (0x800000UL)
9644 /* ------------------------------- ECAT_EVENT_REQ ------------------------------- */
9645 #define ECAT_EVENT_REQ_DC_LE_Pos (0UL)
9646 #define ECAT_EVENT_REQ_DC_LE_Msk (0x1UL)
9647 #define ECAT_EVENT_REQ_DL_SE_Pos (2UL)
9648 #define ECAT_EVENT_REQ_DL_SE_Msk (0x4UL)
9649 #define ECAT_EVENT_REQ_AL_SE_Pos (3UL)
9650 #define ECAT_EVENT_REQ_AL_SE_Msk (0x8UL)
9651 #define ECAT_EVENT_REQ_MIR_0_Pos (4UL)
9652 #define ECAT_EVENT_REQ_MIR_0_Msk (0x10UL)
9653 #define ECAT_EVENT_REQ_MIR_1_Pos (5UL)
9654 #define ECAT_EVENT_REQ_MIR_1_Msk (0x20UL)
9655 #define ECAT_EVENT_REQ_MIR_2_Pos (6UL)
9656 #define ECAT_EVENT_REQ_MIR_2_Msk (0x40UL)
9657 #define ECAT_EVENT_REQ_MIR_3_Pos (7UL)
9658 #define ECAT_EVENT_REQ_MIR_3_Msk (0x80UL)
9659 #define ECAT_EVENT_REQ_MIR_4_Pos (8UL)
9660 #define ECAT_EVENT_REQ_MIR_4_Msk (0x100UL)
9661 #define ECAT_EVENT_REQ_MIR_5_Pos (9UL)
9662 #define ECAT_EVENT_REQ_MIR_5_Msk (0x200UL)
9663 #define ECAT_EVENT_REQ_MIR_6_Pos (10UL)
9664 #define ECAT_EVENT_REQ_MIR_6_Msk (0x400UL)
9665 #define ECAT_EVENT_REQ_MIR_7_Pos (11UL)
9666 #define ECAT_EVENT_REQ_MIR_7_Msk (0x800UL)
9668 /* ------------------------------ ECAT_AL_EVENT_REQ ----------------------------- */
9669 #define ECAT_AL_EVENT_REQ_AL_CE_Pos (0UL)
9670 #define ECAT_AL_EVENT_REQ_AL_CE_Msk (0x1UL)
9671 #define ECAT_AL_EVENT_REQ_DC_LE_Pos (1UL)
9672 #define ECAT_AL_EVENT_REQ_DC_LE_Msk (0x2UL)
9673 #define ECAT_AL_EVENT_REQ_ST_S0_Pos (2UL)
9674 #define ECAT_AL_EVENT_REQ_ST_S0_Msk (0x4UL)
9675 #define ECAT_AL_EVENT_REQ_ST_S1_Pos (3UL)
9676 #define ECAT_AL_EVENT_REQ_ST_S1_Msk (0x8UL)
9677 #define ECAT_AL_EVENT_REQ_SM_A_Pos (4UL)
9678 #define ECAT_AL_EVENT_REQ_SM_A_Msk (0x10UL)
9679 #define ECAT_AL_EVENT_REQ_EEP_E_Pos (5UL)
9680 #define ECAT_AL_EVENT_REQ_EEP_E_Msk (0x20UL)
9681 #define ECAT_AL_EVENT_REQ_WP_D_Pos (6UL)
9682 #define ECAT_AL_EVENT_REQ_WP_D_Msk (0x40UL)
9683 #define ECAT_AL_EVENT_REQ_SMI_0_Pos (8UL)
9684 #define ECAT_AL_EVENT_REQ_SMI_0_Msk (0x100UL)
9685 #define ECAT_AL_EVENT_REQ_SMI_1_Pos (9UL)
9686 #define ECAT_AL_EVENT_REQ_SMI_1_Msk (0x200UL)
9687 #define ECAT_AL_EVENT_REQ_SMI_2_Pos (10UL)
9688 #define ECAT_AL_EVENT_REQ_SMI_2_Msk (0x400UL)
9689 #define ECAT_AL_EVENT_REQ_SMI_3_Pos (11UL)
9690 #define ECAT_AL_EVENT_REQ_SMI_3_Msk (0x800UL)
9691 #define ECAT_AL_EVENT_REQ_SMI_4_Pos (12UL)
9692 #define ECAT_AL_EVENT_REQ_SMI_4_Msk (0x1000UL)
9693 #define ECAT_AL_EVENT_REQ_SMI_5_Pos (13UL)
9694 #define ECAT_AL_EVENT_REQ_SMI_5_Msk (0x2000UL)
9695 #define ECAT_AL_EVENT_REQ_SMI_6_Pos (14UL)
9696 #define ECAT_AL_EVENT_REQ_SMI_6_Msk (0x4000UL)
9697 #define ECAT_AL_EVENT_REQ_SMI_7_Pos (15UL)
9698 #define ECAT_AL_EVENT_REQ_SMI_7_Msk (0x8000UL)
9699 #define ECAT_AL_EVENT_REQ_SMI_8_Pos (16UL)
9700 #define ECAT_AL_EVENT_REQ_SMI_8_Msk (0x10000UL)
9701 #define ECAT_AL_EVENT_REQ_SMI_9_Pos (17UL)
9702 #define ECAT_AL_EVENT_REQ_SMI_9_Msk (0x20000UL)
9703 #define ECAT_AL_EVENT_REQ_SMI_10_Pos (18UL)
9704 #define ECAT_AL_EVENT_REQ_SMI_10_Msk (0x40000UL)
9705 #define ECAT_AL_EVENT_REQ_SMI_11_Pos (19UL)
9706 #define ECAT_AL_EVENT_REQ_SMI_11_Msk (0x80000UL)
9707 #define ECAT_AL_EVENT_REQ_SMI_12_Pos (20UL)
9708 #define ECAT_AL_EVENT_REQ_SMI_12_Msk (0x100000UL)
9709 #define ECAT_AL_EVENT_REQ_SMI_13_Pos (21UL)
9710 #define ECAT_AL_EVENT_REQ_SMI_13_Msk (0x200000UL)
9711 #define ECAT_AL_EVENT_REQ_SMI_14_Pos (22UL)
9712 #define ECAT_AL_EVENT_REQ_SMI_14_Msk (0x400000UL)
9713 #define ECAT_AL_EVENT_REQ_SMI_15_Pos (23UL)
9714 #define ECAT_AL_EVENT_REQ_SMI_15_Msk (0x800000UL)
9716 /* ----------------------------- ECAT_RX_ERR_COUNT0 ----------------------------- */
9717 #define ECAT_RX_ERR_COUNT0_INVALID_FRAME_Pos (0UL)
9718 #define ECAT_RX_ERR_COUNT0_INVALID_FRAME_Msk (0xffUL)
9719 #define ECAT_RX_ERR_COUNT0_RX_ERROR_Pos (8UL)
9720 #define ECAT_RX_ERR_COUNT0_RX_ERROR_Msk (0xff00UL)
9722 /* ----------------------------- ECAT_RX_ERR_COUNT1 ----------------------------- */
9723 #define ECAT_RX_ERR_COUNT1_INVALID_FRAME_Pos (0UL)
9724 #define ECAT_RX_ERR_COUNT1_INVALID_FRAME_Msk (0xffUL)
9725 #define ECAT_RX_ERR_COUNT1_RX_ERROR_Pos (8UL)
9726 #define ECAT_RX_ERR_COUNT1_RX_ERROR_Msk (0xff00UL)
9728 /* --------------------------- ECAT_FWD_RX_ERR_COUNT0 --------------------------- */
9729 #define ECAT_FWD_RX_ERR_COUNT0_FORW_ERROR_Pos (0UL)
9730 #define ECAT_FWD_RX_ERR_COUNT0_FORW_ERROR_Msk (0xffUL)
9732 /* --------------------------- ECAT_FWD_RX_ERR_COUNT1 --------------------------- */
9733 #define ECAT_FWD_RX_ERR_COUNT1_FORW_ERROR_Pos (0UL)
9734 #define ECAT_FWD_RX_ERR_COUNT1_FORW_ERROR_Msk (0xffUL)
9736 /* ----------------------------- ECAT_PROC_ERR_COUNT ---------------------------- */
9737 #define ECAT_PROC_ERR_COUNT_UNIT_ERROR_Pos (0UL)
9738 #define ECAT_PROC_ERR_COUNT_UNIT_ERROR_Msk (0xffUL)
9740 /* ----------------------------- ECAT_PDI_ERR_COUNT ----------------------------- */
9741 #define ECAT_PDI_ERR_COUNT_PDI_ERROR_COUNTER_Pos (0UL)
9742 #define ECAT_PDI_ERR_COUNT_PDI_ERROR_COUNTER_Msk (0xffUL)
9744 /* ---------------------------- ECAT_LOST_LINK_COUNT0 --------------------------- */
9745 #define ECAT_LOST_LINK_COUNT0_LL_COUNTER_Pos (0UL)
9746 #define ECAT_LOST_LINK_COUNT0_LL_COUNTER_Msk (0xffUL)
9748 /* ---------------------------- ECAT_LOST_LINK_COUNT1 --------------------------- */
9749 #define ECAT_LOST_LINK_COUNT1_LL_COUNTER_Pos (0UL)
9750 #define ECAT_LOST_LINK_COUNT1_LL_COUNTER_Msk (0xffUL)
9752 /* ------------------------------- ECAT_WD_DIVIDE ------------------------------- */
9753 #define ECAT_WD_DIVIDE_WD_DIV_Pos (0UL)
9754 #define ECAT_WD_DIVIDE_WD_DIV_Msk (0xffffUL)
9756 /* ------------------------------ ECAT_WD_TIME_PDI ------------------------------ */
9757 #define ECAT_WD_TIME_PDI_WD_TIME_PDI_Pos (0UL)
9758 #define ECAT_WD_TIME_PDI_WD_TIME_PDI_Msk (0xffffUL)
9760 /* ----------------------------- ECAT_WD_TIME_PDATA ----------------------------- */
9761 #define ECAT_WD_TIME_PDATA_WD_TIME_PD_Pos (0UL)
9762 #define ECAT_WD_TIME_PDATA_WD_TIME_PD_Msk (0xffffUL)
9764 /* ----------------------------- ECAT_WD_STAT_PDATA ----------------------------- */
9765 #define ECAT_WD_STAT_PDATA_WD_STAT_PD_Pos (0UL)
9766 #define ECAT_WD_STAT_PDATA_WD_STAT_PD_Msk (0x1UL)
9768 /* ----------------------------- ECAT_WD_COUNT_PDATA ---------------------------- */
9769 #define ECAT_WD_COUNT_PDATA_WD_COUNTER_PD_Pos (0UL)
9770 #define ECAT_WD_COUNT_PDATA_WD_COUNTER_PD_Msk (0xffUL)
9772 /* ------------------------------ ECAT_WD_COUNT_PDI ----------------------------- */
9773 #define ECAT_WD_COUNT_PDI_WD_COUNTER_PDI_Pos (0UL)
9774 #define ECAT_WD_COUNT_PDI_WD_COUNTER_PDI_Msk (0xffUL)
9776 /* -------------------------------- ECAT_EEP_CONF ------------------------------- */
9777 #define ECAT_EEP_CONF_TO_PDI_Pos (0UL)
9778 #define ECAT_EEP_CONF_TO_PDI_Msk (0x1UL)
9779 #define ECAT_EEP_CONF_FORCE_Pos (1UL)
9780 #define ECAT_EEP_CONF_FORCE_Msk (0x2UL)
9782 /* ------------------------------- ECAT_EEP_STATE ------------------------------- */
9783 #define ECAT_EEP_STATE_ACCESS_Pos (0UL)
9784 #define ECAT_EEP_STATE_ACCESS_Msk (0x1UL)
9786 /* ----------------------------- ECAT_EEP_CONT_STAT ----------------------------- */
9787 #define ECAT_EEP_CONT_STAT_W_EN_Pos (0UL)
9788 #define ECAT_EEP_CONT_STAT_W_EN_Msk (0x1UL)
9789 #define ECAT_EEP_CONT_STAT_EMUL_Pos (5UL)
9790 #define ECAT_EEP_CONT_STAT_EMUL_Msk (0x20UL)
9791 #define ECAT_EEP_CONT_STAT_BYTES_Pos (6UL)
9792 #define ECAT_EEP_CONT_STAT_BYTES_Msk (0x40UL)
9793 #define ECAT_EEP_CONT_STAT_ALG_Pos (7UL)
9794 #define ECAT_EEP_CONT_STAT_ALG_Msk (0x80UL)
9795 #define ECAT_EEP_CONT_STAT_CMD_REG_Pos (8UL)
9796 #define ECAT_EEP_CONT_STAT_CMD_REG_Msk (0x700UL)
9797 #define ECAT_EEP_CONT_STAT_ERROR_Pos (11UL)
9798 #define ECAT_EEP_CONT_STAT_ERROR_Msk (0x800UL)
9799 #define ECAT_EEP_CONT_STAT_L_STAT_Pos (12UL)
9800 #define ECAT_EEP_CONT_STAT_L_STAT_Msk (0x1000UL)
9801 #define ECAT_EEP_CONT_STAT_ERROR_AC_Pos (13UL)
9802 #define ECAT_EEP_CONT_STAT_ERROR_AC_Msk (0x2000UL)
9803 #define ECAT_EEP_CONT_STAT_ERROR_WE_Pos (14UL)
9804 #define ECAT_EEP_CONT_STAT_ERROR_WE_Msk (0x4000UL)
9805 #define ECAT_EEP_CONT_STAT_BUSY_Pos (15UL)
9806 #define ECAT_EEP_CONT_STAT_BUSY_Msk (0x8000UL)
9808 /* -------------------------------- ECAT_EEP_ADR -------------------------------- */
9809 #define ECAT_EEP_ADR_EEPROM_ADDR_Pos (0UL)
9810 #define ECAT_EEP_ADR_EEPROM_ADDR_Msk (0xffffffffUL)
9812 /* -------------------------------- ECAT_EEP_DATA ------------------------------- */
9813 #define ECAT_EEP_DATA_EEP_DATA_Pos (0UL)
9814 #define ECAT_EEP_DATA_EEP_DATA_Msk (0xffffffffUL)
9816 /* ----------------------------- ECAT_MII_CONT_STAT ----------------------------- */
9817 #define ECAT_MII_CONT_STAT_W_EN_Pos (0UL)
9818 #define ECAT_MII_CONT_STAT_W_EN_Msk (0x1UL)
9819 #define ECAT_MII_CONT_STAT_MIC_PDI_Pos (1UL)
9820 #define ECAT_MII_CONT_STAT_MIC_PDI_Msk (0x2UL)
9821 #define ECAT_MII_CONT_STAT_MI_LD_Pos (2UL)
9822 #define ECAT_MII_CONT_STAT_MI_LD_Msk (0x4UL)
9823 #define ECAT_MII_CONT_STAT_PHY_ADDR_Pos (3UL)
9824 #define ECAT_MII_CONT_STAT_PHY_ADDR_Msk (0xf8UL)
9825 #define ECAT_MII_CONT_STAT_CMD_REG_Pos (8UL)
9826 #define ECAT_MII_CONT_STAT_CMD_REG_Msk (0x300UL)
9827 #define ECAT_MII_CONT_STAT_ERROR_Pos (14UL)
9828 #define ECAT_MII_CONT_STAT_ERROR_Msk (0x4000UL)
9829 #define ECAT_MII_CONT_STAT_BUSY_Pos (15UL)
9830 #define ECAT_MII_CONT_STAT_BUSY_Msk (0x8000UL)
9832 /* ------------------------------ ECAT_MII_PHY_ADR ------------------------------ */
9833 #define ECAT_MII_PHY_ADR_PHY_ADDR_Pos (0UL)
9834 #define ECAT_MII_PHY_ADR_PHY_ADDR_Msk (0x1fUL)
9835 #define ECAT_MII_PHY_ADR_PHY_CADDR_Pos (7UL)
9836 #define ECAT_MII_PHY_ADR_PHY_CADDR_Msk (0x80UL)
9838 /* ---------------------------- ECAT_MII_PHY_REG_ADR ---------------------------- */
9839 #define ECAT_MII_PHY_REG_ADR_PHY_REG_ADDR_Pos (0UL)
9840 #define ECAT_MII_PHY_REG_ADR_PHY_REG_ADDR_Msk (0x1fUL)
9842 /* ------------------------------ ECAT_MII_PHY_DATA ----------------------------- */
9843 #define ECAT_MII_PHY_DATA_PHY_RW_DATA_Pos (0UL)
9844 #define ECAT_MII_PHY_DATA_PHY_RW_DATA_Msk (0xffffUL)
9846 /* --------------------------- ECAT_MII_ECAT_ACS_STATE -------------------------- */
9847 #define ECAT_MII_ECAT_ACS_STATE_EN_ACS_MII_BY_PDI_Pos (0UL)
9848 #define ECAT_MII_ECAT_ACS_STATE_EN_ACS_MII_BY_PDI_Msk (0x1UL)
9850 /* --------------------------- ECAT_MII_PDI_ACS_STATE --------------------------- */
9851 #define ECAT_MII_PDI_ACS_STATE_ACS_MII_BY_PDI_Pos (0UL)
9852 #define ECAT_MII_PDI_ACS_STATE_ACS_MII_BY_PDI_Msk (0x1UL)
9853 #define ECAT_MII_PDI_ACS_STATE_FORCE_PDI_ACS_S_Pos (1UL)
9854 #define ECAT_MII_PDI_ACS_STATE_FORCE_PDI_ACS_S_Msk (0x2UL)
9856 /* --------------------------- ECAT_DC_RCV_TIME_PORT0 --------------------------- */
9857 #define ECAT_DC_RCV_TIME_PORT0_LOCAL_TIME_P0_Pos (0UL)
9858 #define ECAT_DC_RCV_TIME_PORT0_LOCAL_TIME_P0_Msk (0xffffffffUL)
9860 /* --------------------------- ECAT_DC_RCV_TIME_PORT1 --------------------------- */
9861 #define ECAT_DC_RCV_TIME_PORT1_LOCAL_TIME_P1_Pos (0UL)
9862 #define ECAT_DC_RCV_TIME_PORT1_LOCAL_TIME_P1_Msk (0xffffffffUL)
9864 /* ------------------------------ ECAT_DC_SYS_TIME ------------------------------ */
9865 #define ECAT_DC_SYS_TIME_WRITE_ACCESS_WRITEMode_Pos (0UL)
9866 #define ECAT_DC_SYS_TIME_WRITE_ACCESS_WRITEMode_Msk (0xffffffffUL)
9868 /* ------------------------------ ECAT_DC_SYS_TIME ------------------------------ */
9869 #define ECAT_DC_SYS_TIME_READ_ACCESS_READMode_Pos (0UL)
9870 #define ECAT_DC_SYS_TIME_READ_ACCESS_READMode_Msk (0xffffffffUL)
9872 /* ---------------------------- ECAT_RECEIVE_TIME_PU ---------------------------- */
9873 #define ECAT_RECEIVE_TIME_PU_RECEIVE_TIME_PU_Pos (0UL)
9874 #define ECAT_RECEIVE_TIME_PU_RECEIVE_TIME_PU_Msk (0xffffffffUL)
9876 /* --------------------------- ECAT_DC_SYS_TIME_OFFSET -------------------------- */
9877 #define ECAT_DC_SYS_TIME_OFFSET_DC_SYS_TIME_OFFSET_Pos (0UL)
9878 #define ECAT_DC_SYS_TIME_OFFSET_DC_SYS_TIME_OFFSET_Msk (0xffffffffUL)
9880 /* --------------------------- ECAT_DC_SYS_TIME_DELAY --------------------------- */
9881 #define ECAT_DC_SYS_TIME_DELAY_CLK_DELAY_Pos (0UL)
9882 #define ECAT_DC_SYS_TIME_DELAY_CLK_DELAY_Msk (0xffffffffUL)
9884 /* ---------------------------- ECAT_DC_SYS_TIME_DIFF --------------------------- */
9885 #define ECAT_DC_SYS_TIME_DIFF_TIME_DIF_Pos (0UL)
9886 #define ECAT_DC_SYS_TIME_DIFF_TIME_DIF_Msk (0x7fffffffUL)
9887 #define ECAT_DC_SYS_TIME_DIFF_CPY_Pos (31UL)
9888 #define ECAT_DC_SYS_TIME_DIFF_CPY_Msk (0x80000000UL)
9890 /* -------------------------- ECAT_DC_SPEED_COUNT_START ------------------------- */
9891 #define ECAT_DC_SPEED_COUNT_START_COUNT_START_Pos (0UL)
9892 #define ECAT_DC_SPEED_COUNT_START_COUNT_START_Msk (0x7fffUL)
9894 /* -------------------------- ECAT_DC_SPEED_COUNT_DIFF -------------------------- */
9895 #define ECAT_DC_SPEED_COUNT_DIFF_DEVIATION_Pos (0UL)
9896 #define ECAT_DC_SPEED_COUNT_DIFF_DEVIATION_Msk (0xffffUL)
9898 /* ------------------------- ECAT_DC_SYS_TIME_FIL_DEPTH ------------------------- */
9899 #define ECAT_DC_SYS_TIME_FIL_DEPTH_FILTER_DEPTH_Pos (0UL)
9900 #define ECAT_DC_SYS_TIME_FIL_DEPTH_FILTER_DEPTH_Msk (0xfUL)
9902 /* ------------------------ ECAT_DC_SPEED_COUNT_FIL_DEPTH ----------------------- */
9903 #define ECAT_DC_SPEED_COUNT_FIL_DEPTH_FILTER_DEPTH_Pos (0UL)
9904 #define ECAT_DC_SPEED_COUNT_FIL_DEPTH_FILTER_DEPTH_Msk (0xfUL)
9906 /* ------------------------------ ECAT_DC_CYC_CONT ------------------------------ */
9907 #define ECAT_DC_CYC_CONT_SYNC_Pos (0UL)
9908 #define ECAT_DC_CYC_CONT_SYNC_Msk (0x1UL)
9909 #define ECAT_DC_CYC_CONT_LATCH_U0_Pos (4UL)
9910 #define ECAT_DC_CYC_CONT_LATCH_U0_Msk (0x10UL)
9911 #define ECAT_DC_CYC_CONT_LATCH_U1_Pos (5UL)
9912 #define ECAT_DC_CYC_CONT_LATCH_U1_Msk (0x20UL)
9914 /* --------------------------------- ECAT_DC_ACT -------------------------------- */
9915 #define ECAT_DC_ACT_SYNC_OUT_Pos (0UL)
9916 #define ECAT_DC_ACT_SYNC_OUT_Msk (0x1UL)
9917 #define ECAT_DC_ACT_SYNC_0_Pos (1UL)
9918 #define ECAT_DC_ACT_SYNC_0_Msk (0x2UL)
9919 #define ECAT_DC_ACT_SYNC_1_Pos (2UL)
9920 #define ECAT_DC_ACT_SYNC_1_Msk (0x4UL)
9922 /* ------------------------------ ECAT_DC_PULSE_LEN ----------------------------- */
9923 #define ECAT_DC_PULSE_LEN_PULS_LENGTH_Pos (0UL)
9924 #define ECAT_DC_PULSE_LEN_PULS_LENGTH_Msk (0xffffUL)
9926 /* ------------------------------ ECAT_DC_ACT_STAT ------------------------------ */
9927 #define ECAT_DC_ACT_STAT_S0_ACK_STATE_Pos (0UL)
9928 #define ECAT_DC_ACT_STAT_S0_ACK_STATE_Msk (0x1UL)
9929 #define ECAT_DC_ACT_STAT_S1_ACK_STATE_Pos (1UL)
9930 #define ECAT_DC_ACT_STAT_S1_ACK_STATE_Msk (0x2UL)
9931 #define ECAT_DC_ACT_STAT_S_TIME_Pos (2UL)
9932 #define ECAT_DC_ACT_STAT_S_TIME_Msk (0x4UL)
9934 /* ----------------------------- ECAT_DC_SYNC0_STAT ----------------------------- */
9935 #define ECAT_DC_SYNC0_STAT_S0_STATE_Pos (0UL)
9936 #define ECAT_DC_SYNC0_STAT_S0_STATE_Msk (0x1UL)
9938 /* ----------------------------- ECAT_DC_SYNC1_STAT ----------------------------- */
9939 #define ECAT_DC_SYNC1_STAT_S1_STATE_Pos (0UL)
9940 #define ECAT_DC_SYNC1_STAT_S1_STATE_Msk (0x1UL)
9942 /* --------------------------- ECAT_DC_CYC_START_TIME --------------------------- */
9943 #define ECAT_DC_CYC_START_TIME_DC_CYC_START_TIME_Pos (0UL)
9944 #define ECAT_DC_CYC_START_TIME_DC_CYC_START_TIME_Msk (0xffffffffUL)
9946 /* -------------------------- ECAT_DC_NEXT_SYNC1_PULSE -------------------------- */
9947 #define ECAT_DC_NEXT_SYNC1_PULSE_DC_NEXT_SYNC1_PULSE_Pos (0UL)
9948 #define ECAT_DC_NEXT_SYNC1_PULSE_DC_NEXT_SYNC1_PULSE_Msk (0xffffffffUL)
9950 /* --------------------------- ECAT_DC_SYNC0_CYC_TIME --------------------------- */
9951 #define ECAT_DC_SYNC0_CYC_TIME_TIME_BETWEEN_SYNC0_Pos (0UL)
9952 #define ECAT_DC_SYNC0_CYC_TIME_TIME_BETWEEN_SYNC0_Msk (0xffffffffUL)
9954 /* --------------------------- ECAT_DC_SYNC1_CYC_TIME --------------------------- */
9955 #define ECAT_DC_SYNC1_CYC_TIME_TIME_SYNC1_SYNC0_Pos (0UL)
9956 #define ECAT_DC_SYNC1_CYC_TIME_TIME_SYNC1_SYNC0_Msk (0xffffffffUL)
9958 /* ----------------------------- ECAT_DC_LATCH0_CONT ---------------------------- */
9959 #define ECAT_DC_LATCH0_CONT_L0_POS_Pos (0UL)
9960 #define ECAT_DC_LATCH0_CONT_L0_POS_Msk (0x1UL)
9961 #define ECAT_DC_LATCH0_CONT_L0_NEG_Pos (1UL)
9962 #define ECAT_DC_LATCH0_CONT_L0_NEG_Msk (0x2UL)
9964 /* ----------------------------- ECAT_DC_LATCH1_CONT ---------------------------- */
9965 #define ECAT_DC_LATCH1_CONT_L1_POS_Pos (0UL)
9966 #define ECAT_DC_LATCH1_CONT_L1_POS_Msk (0x1UL)
9967 #define ECAT_DC_LATCH1_CONT_L1_NEG_Pos (1UL)
9968 #define ECAT_DC_LATCH1_CONT_L1_NEG_Msk (0x2UL)
9970 /* ----------------------------- ECAT_DC_LATCH0_STAT ---------------------------- */
9971 #define ECAT_DC_LATCH0_STAT_EV_L0_POS_Pos (0UL)
9972 #define ECAT_DC_LATCH0_STAT_EV_L0_POS_Msk (0x1UL)
9973 #define ECAT_DC_LATCH0_STAT_EV_L0_NEG_Pos (1UL)
9974 #define ECAT_DC_LATCH0_STAT_EV_L0_NEG_Msk (0x2UL)
9975 #define ECAT_DC_LATCH0_STAT_L0_PIN_Pos (2UL)
9976 #define ECAT_DC_LATCH0_STAT_L0_PIN_Msk (0x4UL)
9978 /* ----------------------------- ECAT_DC_LATCH1_STAT ---------------------------- */
9979 #define ECAT_DC_LATCH1_STAT_EV_L1_POS_Pos (0UL)
9980 #define ECAT_DC_LATCH1_STAT_EV_L1_POS_Msk (0x1UL)
9981 #define ECAT_DC_LATCH1_STAT_EV_L1_NEG_Pos (1UL)
9982 #define ECAT_DC_LATCH1_STAT_EV_L1_NEG_Msk (0x2UL)
9983 #define ECAT_DC_LATCH1_STAT_L1_PIN_Pos (2UL)
9984 #define ECAT_DC_LATCH1_STAT_L1_PIN_Msk (0x4UL)
9986 /* --------------------------- ECAT_DC_LATCH0_TIME_POS -------------------------- */
9987 #define ECAT_DC_LATCH0_TIME_POS_DC_LATCH0_TIME_POS_Pos (0UL)
9988 #define ECAT_DC_LATCH0_TIME_POS_DC_LATCH0_TIME_POS_Msk (0xffffffffUL)
9990 /* --------------------------- ECAT_DC_LATCH0_TIME_NEG -------------------------- */
9991 #define ECAT_DC_LATCH0_TIME_NEG_DC_LATCH0_TIME_NEG_Pos (0UL)
9992 #define ECAT_DC_LATCH0_TIME_NEG_DC_LATCH0_TIME_NEG_Msk (0xffffffffUL)
9994 /* --------------------------- ECAT_DC_LATCH1_TIME_POS -------------------------- */
9995 #define ECAT_DC_LATCH1_TIME_POS_DC_LATCH1_TIME_POS_Pos (0UL)
9996 #define ECAT_DC_LATCH1_TIME_POS_DC_LATCH1_TIME_POS_Msk (0xffffffffUL)
9998 /* --------------------------- ECAT_DC_LATCH1_TIME_NEG -------------------------- */
9999 #define ECAT_DC_LATCH1_TIME_NEG_DC_LATCH1_TIME_NEG_Pos (0UL)
10000 #define ECAT_DC_LATCH1_TIME_NEG_DC_LATCH1_TIME_NEG_Msk (0xffffffffUL)
10002 /* -------------------------- ECAT_DC_ECAT_CNG_EV_TIME -------------------------- */
10003 #define ECAT_DC_ECAT_CNG_EV_TIME_ECAT_CNG_EV_TIME_Pos (0UL)
10004 #define ECAT_DC_ECAT_CNG_EV_TIME_ECAT_CNG_EV_TIME_Msk (0xffffffffUL)
10006 /* -------------------------- ECAT_DC_PDI_START_EV_TIME ------------------------- */
10007 #define ECAT_DC_PDI_START_EV_TIME_PDI_START_EV_TIME_Pos (0UL)
10008 #define ECAT_DC_PDI_START_EV_TIME_PDI_START_EV_TIME_Msk (0xffffffffUL)
10010 /* --------------------------- ECAT_DC_PDI_CNG_EV_TIME -------------------------- */
10011 #define ECAT_DC_PDI_CNG_EV_TIME_PDI_CNG_EV_TIME_Pos (0UL)
10012 #define ECAT_DC_PDI_CNG_EV_TIME_PDI_CNG_EV_TIME_Msk (0xffffffffUL)
10014 /* ----------------------------------- ECAT_ID ---------------------------------- */
10015 #define ECAT_ID_MOD_REV_Pos (0UL)
10016 #define ECAT_ID_MOD_REV_Msk (0xffUL)
10017 #define ECAT_ID_MOD_TYPE_Pos (8UL)
10018 #define ECAT_ID_MOD_TYPE_Msk (0xff00UL)
10019 #define ECAT_ID_MOD_NUMBER_Pos (16UL)
10020 #define ECAT_ID_MOD_NUMBER_Msk (0xffff0000UL)
10022 /* --------------------------------- ECAT_STATUS -------------------------------- */
10023 #define ECAT_STATUS_PARERR_Pos (0UL)
10024 #define ECAT_STATUS_PARERR_Msk (0x1UL)
10027 /* ================================================================================ */
10028 /* ================ Group 'USB' Position & Mask ================ */
10029 /* ================================================================================ */
10030 
10031 
10032 /* --------------------------------- USB_GOTGCTL -------------------------------- */
10033 #define USB_GOTGCTL_SesReqScs_Pos (0UL)
10034 #define USB_GOTGCTL_SesReqScs_Msk (0x1UL)
10035 #define USB_GOTGCTL_SesReq_Pos (1UL)
10036 #define USB_GOTGCTL_SesReq_Msk (0x2UL)
10037 #define USB_GOTGCTL_VbvalidOvEn_Pos (2UL)
10038 #define USB_GOTGCTL_VbvalidOvEn_Msk (0x4UL)
10039 #define USB_GOTGCTL_VbvalidOvVal_Pos (3UL)
10040 #define USB_GOTGCTL_VbvalidOvVal_Msk (0x8UL)
10041 #define USB_GOTGCTL_AvalidOvEn_Pos (4UL)
10042 #define USB_GOTGCTL_AvalidOvEn_Msk (0x10UL)
10043 #define USB_GOTGCTL_AvalidOvVal_Pos (5UL)
10044 #define USB_GOTGCTL_AvalidOvVal_Msk (0x20UL)
10045 #define USB_GOTGCTL_BvalidOvEn_Pos (6UL)
10046 #define USB_GOTGCTL_BvalidOvEn_Msk (0x40UL)
10047 #define USB_GOTGCTL_BvalidOvVal_Pos (7UL)
10048 #define USB_GOTGCTL_BvalidOvVal_Msk (0x80UL)
10049 #define USB_GOTGCTL_HstNegScs_Pos (8UL)
10050 #define USB_GOTGCTL_HstNegScs_Msk (0x100UL)
10051 #define USB_GOTGCTL_HNPReq_Pos (9UL)
10052 #define USB_GOTGCTL_HNPReq_Msk (0x200UL)
10053 #define USB_GOTGCTL_HstSetHNPEn_Pos (10UL)
10054 #define USB_GOTGCTL_HstSetHNPEn_Msk (0x400UL)
10055 #define USB_GOTGCTL_DevHNPEn_Pos (11UL)
10056 #define USB_GOTGCTL_DevHNPEn_Msk (0x800UL)
10057 #define USB_GOTGCTL_ConlDSts_Pos (16UL)
10058 #define USB_GOTGCTL_ConlDSts_Msk (0x10000UL)
10059 #define USB_GOTGCTL_DbncTime_Pos (17UL)
10060 #define USB_GOTGCTL_DbncTime_Msk (0x20000UL)
10061 #define USB_GOTGCTL_ASesVId_Pos (18UL)
10062 #define USB_GOTGCTL_ASesVId_Msk (0x40000UL)
10063 #define USB_GOTGCTL_BSesVld_Pos (19UL)
10064 #define USB_GOTGCTL_BSesVld_Msk (0x80000UL)
10065 #define USB_GOTGCTL_OTGVer_Pos (20UL)
10066 #define USB_GOTGCTL_OTGVer_Msk (0x100000UL)
10068 /* --------------------------------- USB_GOTGINT -------------------------------- */
10069 #define USB_GOTGINT_SesEndDet_Pos (2UL)
10070 #define USB_GOTGINT_SesEndDet_Msk (0x4UL)
10071 #define USB_GOTGINT_SesReqSucStsChng_Pos (8UL)
10072 #define USB_GOTGINT_SesReqSucStsChng_Msk (0x100UL)
10073 #define USB_GOTGINT_HstNegSucStsChng_Pos (9UL)
10074 #define USB_GOTGINT_HstNegSucStsChng_Msk (0x200UL)
10075 #define USB_GOTGINT_HstNegDet_Pos (17UL)
10076 #define USB_GOTGINT_HstNegDet_Msk (0x20000UL)
10077 #define USB_GOTGINT_ADevTOUTChg_Pos (18UL)
10078 #define USB_GOTGINT_ADevTOUTChg_Msk (0x40000UL)
10079 #define USB_GOTGINT_DbnceDone_Pos (19UL)
10080 #define USB_GOTGINT_DbnceDone_Msk (0x80000UL)
10082 /* --------------------------------- USB_GAHBCFG -------------------------------- */
10083 #define USB_GAHBCFG_GlblIntrMsk_Pos (0UL)
10084 #define USB_GAHBCFG_GlblIntrMsk_Msk (0x1UL)
10085 #define USB_GAHBCFG_HBstLen_Pos (1UL)
10086 #define USB_GAHBCFG_HBstLen_Msk (0x1eUL)
10087 #define USB_GAHBCFG_DMAEn_Pos (5UL)
10088 #define USB_GAHBCFG_DMAEn_Msk (0x20UL)
10089 #define USB_GAHBCFG_NPTxFEmpLvl_Pos (7UL)
10090 #define USB_GAHBCFG_NPTxFEmpLvl_Msk (0x80UL)
10091 #define USB_GAHBCFG_PTxFEmpLvl_Pos (8UL)
10092 #define USB_GAHBCFG_PTxFEmpLvl_Msk (0x100UL)
10093 #define USB_GAHBCFG_AHBSingle_Pos (23UL)
10094 #define USB_GAHBCFG_AHBSingle_Msk (0x800000UL)
10096 /* --------------------------------- USB_GUSBCFG -------------------------------- */
10097 #define USB_GUSBCFG_TOutCal_Pos (0UL)
10098 #define USB_GUSBCFG_TOutCal_Msk (0x7UL)
10099 #define USB_GUSBCFG_PHYSel_Pos (6UL)
10100 #define USB_GUSBCFG_PHYSel_Msk (0x40UL)
10101 #define USB_GUSBCFG_SRPCap_Pos (8UL)
10102 #define USB_GUSBCFG_SRPCap_Msk (0x100UL)
10103 #define USB_GUSBCFG_HNPCap_Pos (9UL)
10104 #define USB_GUSBCFG_HNPCap_Msk (0x200UL)
10105 #define USB_GUSBCFG_USBTrdTim_Pos (10UL)
10106 #define USB_GUSBCFG_USBTrdTim_Msk (0x3c00UL)
10107 #define USB_GUSBCFG_OtgI2CSel_Pos (16UL)
10108 #define USB_GUSBCFG_OtgI2CSel_Msk (0x10000UL)
10109 #define USB_GUSBCFG_TxEndDelay_Pos (28UL)
10110 #define USB_GUSBCFG_TxEndDelay_Msk (0x10000000UL)
10111 #define USB_GUSBCFG_ForceHstMode_Pos (29UL)
10112 #define USB_GUSBCFG_ForceHstMode_Msk (0x20000000UL)
10113 #define USB_GUSBCFG_ForceDevMode_Pos (30UL)
10114 #define USB_GUSBCFG_ForceDevMode_Msk (0x40000000UL)
10115 #define USB_GUSBCFG_CTP_Pos (31UL)
10116 #define USB_GUSBCFG_CTP_Msk (0x80000000UL)
10118 /* --------------------------------- USB_GRSTCTL -------------------------------- */
10119 #define USB_GRSTCTL_CSftRst_Pos (0UL)
10120 #define USB_GRSTCTL_CSftRst_Msk (0x1UL)
10121 #define USB_GRSTCTL_FrmCntrRst_Pos (2UL)
10122 #define USB_GRSTCTL_FrmCntrRst_Msk (0x4UL)
10123 #define USB_GRSTCTL_RxFFlsh_Pos (4UL)
10124 #define USB_GRSTCTL_RxFFlsh_Msk (0x10UL)
10125 #define USB_GRSTCTL_TxFFlsh_Pos (5UL)
10126 #define USB_GRSTCTL_TxFFlsh_Msk (0x20UL)
10127 #define USB_GRSTCTL_TxFNum_Pos (6UL)
10128 #define USB_GRSTCTL_TxFNum_Msk (0x7c0UL)
10129 #define USB_GRSTCTL_DMAReq_Pos (30UL)
10130 #define USB_GRSTCTL_DMAReq_Msk (0x40000000UL)
10131 #define USB_GRSTCTL_AHBIdle_Pos (31UL)
10132 #define USB_GRSTCTL_AHBIdle_Msk (0x80000000UL)
10134 /* ---------------------------- USB_GINTSTS_HOSTMODE ---------------------------- */
10135 #define USB_GINTSTS_HOSTMODE_CurMod_Pos (0UL)
10136 #define USB_GINTSTS_HOSTMODE_CurMod_Msk (0x1UL)
10137 #define USB_GINTSTS_HOSTMODE_ModeMis_Pos (1UL)
10138 #define USB_GINTSTS_HOSTMODE_ModeMis_Msk (0x2UL)
10139 #define USB_GINTSTS_HOSTMODE_OTGInt_Pos (2UL)
10140 #define USB_GINTSTS_HOSTMODE_OTGInt_Msk (0x4UL)
10141 #define USB_GINTSTS_HOSTMODE_Sof_Pos (3UL)
10142 #define USB_GINTSTS_HOSTMODE_Sof_Msk (0x8UL)
10143 #define USB_GINTSTS_HOSTMODE_RxFLvl_Pos (4UL)
10144 #define USB_GINTSTS_HOSTMODE_RxFLvl_Msk (0x10UL)
10145 #define USB_GINTSTS_HOSTMODE_incomplP_Pos (21UL)
10146 #define USB_GINTSTS_HOSTMODE_incomplP_Msk (0x200000UL)
10147 #define USB_GINTSTS_HOSTMODE_PrtInt_Pos (24UL)
10148 #define USB_GINTSTS_HOSTMODE_PrtInt_Msk (0x1000000UL)
10149 #define USB_GINTSTS_HOSTMODE_HChInt_Pos (25UL)
10150 #define USB_GINTSTS_HOSTMODE_HChInt_Msk (0x2000000UL)
10151 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Pos (26UL)
10152 #define USB_GINTSTS_HOSTMODE_PTxFEmp_Msk (0x4000000UL)
10153 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Pos (28UL)
10154 #define USB_GINTSTS_HOSTMODE_ConIDStsChng_Msk (0x10000000UL)
10155 #define USB_GINTSTS_HOSTMODE_DisconnInt_Pos (29UL)
10156 #define USB_GINTSTS_HOSTMODE_DisconnInt_Msk (0x20000000UL)
10157 #define USB_GINTSTS_HOSTMODE_SessReqInt_Pos (30UL)
10158 #define USB_GINTSTS_HOSTMODE_SessReqInt_Msk (0x40000000UL)
10159 #define USB_GINTSTS_HOSTMODE_WkUpInt_Pos (31UL)
10160 #define USB_GINTSTS_HOSTMODE_WkUpInt_Msk (0x80000000UL)
10162 /* --------------------------- USB_GINTSTS_DEVICEMODE --------------------------- */
10163 #define USB_GINTSTS_DEVICEMODE_CurMod_Pos (0UL)
10164 #define USB_GINTSTS_DEVICEMODE_CurMod_Msk (0x1UL)
10165 #define USB_GINTSTS_DEVICEMODE_ModeMis_Pos (1UL)
10166 #define USB_GINTSTS_DEVICEMODE_ModeMis_Msk (0x2UL)
10167 #define USB_GINTSTS_DEVICEMODE_OTGInt_Pos (2UL)
10168 #define USB_GINTSTS_DEVICEMODE_OTGInt_Msk (0x4UL)
10169 #define USB_GINTSTS_DEVICEMODE_Sof_Pos (3UL)
10170 #define USB_GINTSTS_DEVICEMODE_Sof_Msk (0x8UL)
10171 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Pos (4UL)
10172 #define USB_GINTSTS_DEVICEMODE_RxFLvl_Msk (0x10UL)
10173 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Pos (6UL)
10174 #define USB_GINTSTS_DEVICEMODE_GINNakEff_Msk (0x40UL)
10175 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Pos (7UL)
10176 #define USB_GINTSTS_DEVICEMODE_GOUTNakEff_Msk (0x80UL)
10177 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Pos (10UL)
10178 #define USB_GINTSTS_DEVICEMODE_ErlySusp_Msk (0x400UL)
10179 #define USB_GINTSTS_DEVICEMODE_USBSusp_Pos (11UL)
10180 #define USB_GINTSTS_DEVICEMODE_USBSusp_Msk (0x800UL)
10181 #define USB_GINTSTS_DEVICEMODE_USBRst_Pos (12UL)
10182 #define USB_GINTSTS_DEVICEMODE_USBRst_Msk (0x1000UL)
10183 #define USB_GINTSTS_DEVICEMODE_EnumDone_Pos (13UL)
10184 #define USB_GINTSTS_DEVICEMODE_EnumDone_Msk (0x2000UL)
10185 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Pos (14UL)
10186 #define USB_GINTSTS_DEVICEMODE_ISOOutDrop_Msk (0x4000UL)
10187 #define USB_GINTSTS_DEVICEMODE_EOPF_Pos (15UL)
10188 #define USB_GINTSTS_DEVICEMODE_EOPF_Msk (0x8000UL)
10189 #define USB_GINTSTS_DEVICEMODE_IEPInt_Pos (18UL)
10190 #define USB_GINTSTS_DEVICEMODE_IEPInt_Msk (0x40000UL)
10191 #define USB_GINTSTS_DEVICEMODE_OEPInt_Pos (19UL)
10192 #define USB_GINTSTS_DEVICEMODE_OEPInt_Msk (0x80000UL)
10193 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Pos (20UL)
10194 #define USB_GINTSTS_DEVICEMODE_incompISOIN_Msk (0x100000UL)
10195 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Pos (21UL)
10196 #define USB_GINTSTS_DEVICEMODE_incomplSOOUT_Msk (0x200000UL)
10197 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Pos (28UL)
10198 #define USB_GINTSTS_DEVICEMODE_ConIDStsChng_Msk (0x10000000UL)
10199 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Pos (30UL)
10200 #define USB_GINTSTS_DEVICEMODE_SessReqInt_Msk (0x40000000UL)
10201 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Pos (31UL)
10202 #define USB_GINTSTS_DEVICEMODE_WkUpInt_Msk (0x80000000UL)
10204 /* ---------------------------- USB_GINTMSK_HOSTMODE ---------------------------- */
10205 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Pos (1UL)
10206 #define USB_GINTMSK_HOSTMODE_ModeMisMsk_Msk (0x2UL)
10207 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Pos (2UL)
10208 #define USB_GINTMSK_HOSTMODE_OTGIntMsk_Msk (0x4UL)
10209 #define USB_GINTMSK_HOSTMODE_SofMsk_Pos (3UL)
10210 #define USB_GINTMSK_HOSTMODE_SofMsk_Msk (0x8UL)
10211 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Pos (4UL)
10212 #define USB_GINTMSK_HOSTMODE_RxFLvlMsk_Msk (0x10UL)
10213 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Pos (21UL)
10214 #define USB_GINTMSK_HOSTMODE_incomplPMsk_Msk (0x200000UL)
10215 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Pos (24UL)
10216 #define USB_GINTMSK_HOSTMODE_PrtIntMsk_Msk (0x1000000UL)
10217 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Pos (25UL)
10218 #define USB_GINTMSK_HOSTMODE_HChIntMsk_Msk (0x2000000UL)
10219 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Pos (26UL)
10220 #define USB_GINTMSK_HOSTMODE_PTxFEmpMsk_Msk (0x4000000UL)
10221 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Pos (28UL)
10222 #define USB_GINTMSK_HOSTMODE_ConIDStsChngMsk_Msk (0x10000000UL)
10223 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Pos (29UL)
10224 #define USB_GINTMSK_HOSTMODE_DisconnIntMsk_Msk (0x20000000UL)
10225 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Pos (30UL)
10226 #define USB_GINTMSK_HOSTMODE_SessReqIntMsk_Msk (0x40000000UL)
10227 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Pos (31UL)
10228 #define USB_GINTMSK_HOSTMODE_WkUpIntMsk_Msk (0x80000000UL)
10230 /* --------------------------- USB_GINTMSK_DEVICEMODE --------------------------- */
10231 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Pos (1UL)
10232 #define USB_GINTMSK_DEVICEMODE_ModeMisMsk_Msk (0x2UL)
10233 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Pos (2UL)
10234 #define USB_GINTMSK_DEVICEMODE_OTGIntMsk_Msk (0x4UL)
10235 #define USB_GINTMSK_DEVICEMODE_SofMsk_Pos (3UL)
10236 #define USB_GINTMSK_DEVICEMODE_SofMsk_Msk (0x8UL)
10237 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Pos (4UL)
10238 #define USB_GINTMSK_DEVICEMODE_RxFLvlMsk_Msk (0x10UL)
10239 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Pos (6UL)
10240 #define USB_GINTMSK_DEVICEMODE_GINNakEffMsk_Msk (0x40UL)
10241 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Pos (7UL)
10242 #define USB_GINTMSK_DEVICEMODE_GOUTNakEffMsk_Msk (0x80UL)
10243 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Pos (10UL)
10244 #define USB_GINTMSK_DEVICEMODE_ErlySuspMsk_Msk (0x400UL)
10245 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Pos (11UL)
10246 #define USB_GINTMSK_DEVICEMODE_USBSuspMsk_Msk (0x800UL)
10247 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Pos (12UL)
10248 #define USB_GINTMSK_DEVICEMODE_USBRstMsk_Msk (0x1000UL)
10249 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Pos (13UL)
10250 #define USB_GINTMSK_DEVICEMODE_EnumDoneMsk_Msk (0x2000UL)
10251 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Pos (14UL)
10252 #define USB_GINTMSK_DEVICEMODE_ISOOutDropMsk_Msk (0x4000UL)
10253 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Pos (15UL)
10254 #define USB_GINTMSK_DEVICEMODE_EOPFMsk_Msk (0x8000UL)
10255 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Pos (18UL)
10256 #define USB_GINTMSK_DEVICEMODE_IEPIntMsk_Msk (0x40000UL)
10257 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Pos (19UL)
10258 #define USB_GINTMSK_DEVICEMODE_OEPIntMsk_Msk (0x80000UL)
10259 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Pos (20UL)
10260 #define USB_GINTMSK_DEVICEMODE_incompISOINMsk_Msk (0x100000UL)
10261 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Pos (21UL)
10262 #define USB_GINTMSK_DEVICEMODE_incomplSOOUTMsk_Msk (0x200000UL)
10263 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Pos (28UL)
10264 #define USB_GINTMSK_DEVICEMODE_ConIDStsChngMsk_Msk (0x10000000UL)
10265 #define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Pos (29UL)
10266 #define USB_GINTMSK_DEVICEMODE_DisconnIntMsk_Msk (0x20000000UL)
10267 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Pos (30UL)
10268 #define USB_GINTMSK_DEVICEMODE_SessReqIntMsk_Msk (0x40000000UL)
10269 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Pos (31UL)
10270 #define USB_GINTMSK_DEVICEMODE_WkUpIntMsk_Msk (0x80000000UL)
10272 /* ---------------------------- USB_GRXSTSR_HOSTMODE ---------------------------- */
10273 #define USB_GRXSTSR_HOSTMODE_ChNum_Pos (0UL)
10274 #define USB_GRXSTSR_HOSTMODE_ChNum_Msk (0xfUL)
10275 #define USB_GRXSTSR_HOSTMODE_BCnt_Pos (4UL)
10276 #define USB_GRXSTSR_HOSTMODE_BCnt_Msk (0x7ff0UL)
10277 #define USB_GRXSTSR_HOSTMODE_DPID_Pos (15UL)
10278 #define USB_GRXSTSR_HOSTMODE_DPID_Msk (0x18000UL)
10279 #define USB_GRXSTSR_HOSTMODE_PktSts_Pos (17UL)
10280 #define USB_GRXSTSR_HOSTMODE_PktSts_Msk (0x1e0000UL)
10282 /* --------------------------- USB_GRXSTSR_DEVICEMODE --------------------------- */
10283 #define USB_GRXSTSR_DEVICEMODE_EPNum_Pos (0UL)
10284 #define USB_GRXSTSR_DEVICEMODE_EPNum_Msk (0xfUL)
10285 #define USB_GRXSTSR_DEVICEMODE_BCnt_Pos (4UL)
10286 #define USB_GRXSTSR_DEVICEMODE_BCnt_Msk (0x7ff0UL)
10287 #define USB_GRXSTSR_DEVICEMODE_DPID_Pos (15UL)
10288 #define USB_GRXSTSR_DEVICEMODE_DPID_Msk (0x18000UL)
10289 #define USB_GRXSTSR_DEVICEMODE_PktSts_Pos (17UL)
10290 #define USB_GRXSTSR_DEVICEMODE_PktSts_Msk (0x1e0000UL)
10291 #define USB_GRXSTSR_DEVICEMODE_FN_Pos (21UL)
10292 #define USB_GRXSTSR_DEVICEMODE_FN_Msk (0x1e00000UL)
10294 /* --------------------------- USB_GRXSTSP_DEVICEMODE --------------------------- */
10295 #define USB_GRXSTSP_DEVICEMODE_EPNum_Pos (0UL)
10296 #define USB_GRXSTSP_DEVICEMODE_EPNum_Msk (0xfUL)
10297 #define USB_GRXSTSP_DEVICEMODE_BCnt_Pos (4UL)
10298 #define USB_GRXSTSP_DEVICEMODE_BCnt_Msk (0x7ff0UL)
10299 #define USB_GRXSTSP_DEVICEMODE_DPID_Pos (15UL)
10300 #define USB_GRXSTSP_DEVICEMODE_DPID_Msk (0x18000UL)
10301 #define USB_GRXSTSP_DEVICEMODE_PktSts_Pos (17UL)
10302 #define USB_GRXSTSP_DEVICEMODE_PktSts_Msk (0x1e0000UL)
10303 #define USB_GRXSTSP_DEVICEMODE_FN_Pos (21UL)
10304 #define USB_GRXSTSP_DEVICEMODE_FN_Msk (0x1e00000UL)
10306 /* ---------------------------- USB_GRXSTSP_HOSTMODE ---------------------------- */
10307 #define USB_GRXSTSP_HOSTMODE_ChNum_Pos (0UL)
10308 #define USB_GRXSTSP_HOSTMODE_ChNum_Msk (0xfUL)
10309 #define USB_GRXSTSP_HOSTMODE_BCnt_Pos (4UL)
10310 #define USB_GRXSTSP_HOSTMODE_BCnt_Msk (0x7ff0UL)
10311 #define USB_GRXSTSP_HOSTMODE_DPID_Pos (15UL)
10312 #define USB_GRXSTSP_HOSTMODE_DPID_Msk (0x18000UL)
10313 #define USB_GRXSTSP_HOSTMODE_PktSts_Pos (17UL)
10314 #define USB_GRXSTSP_HOSTMODE_PktSts_Msk (0x1e0000UL)
10316 /* --------------------------------- USB_GRXFSIZ -------------------------------- */
10317 #define USB_GRXFSIZ_RxFDep_Pos (0UL)
10318 #define USB_GRXFSIZ_RxFDep_Msk (0xffffUL)
10320 /* --------------------------- USB_GNPTXFSIZ_HOSTMODE --------------------------- */
10321 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Pos (0UL)
10322 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFStAddr_Msk (0xffffUL)
10323 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Pos (16UL)
10324 #define USB_GNPTXFSIZ_HOSTMODE_NPTxFDep_Msk (0xffff0000UL)
10326 /* -------------------------- USB_GNPTXFSIZ_DEVICEMODE -------------------------- */
10327 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Pos (0UL)
10328 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0StAddr_Msk (0xffffUL)
10329 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Pos (16UL)
10330 #define USB_GNPTXFSIZ_DEVICEMODE_INEPTxF0Dep_Msk (0xffff0000UL)
10332 /* -------------------------------- USB_GNPTXSTS -------------------------------- */
10333 #define USB_GNPTXSTS_NPTxFSpcAvail_Pos (0UL)
10334 #define USB_GNPTXSTS_NPTxFSpcAvail_Msk (0xffffUL)
10335 #define USB_GNPTXSTS_NPTxQSpcAvail_Pos (16UL)
10336 #define USB_GNPTXSTS_NPTxQSpcAvail_Msk (0xff0000UL)
10337 #define USB_GNPTXSTS_NPTxQTop_Pos (24UL)
10338 #define USB_GNPTXSTS_NPTxQTop_Msk (0x7f000000UL)
10340 /* ---------------------------------- USB_GUID ---------------------------------- */
10341 #define USB_GUID_MOD_REV_Pos (0UL)
10342 #define USB_GUID_MOD_REV_Msk (0xffUL)
10343 #define USB_GUID_MOD_TYPE_Pos (8UL)
10344 #define USB_GUID_MOD_TYPE_Msk (0xff00UL)
10345 #define USB_GUID_MOD_NUMBER_Pos (16UL)
10346 #define USB_GUID_MOD_NUMBER_Msk (0xffff0000UL)
10348 /* -------------------------------- USB_GDFIFOCFG ------------------------------- */
10349 #define USB_GDFIFOCFG_GDFIFOCfg_Pos (0UL)
10350 #define USB_GDFIFOCFG_GDFIFOCfg_Msk (0xffffUL)
10351 #define USB_GDFIFOCFG_EPInfoBaseAddr_Pos (16UL)
10352 #define USB_GDFIFOCFG_EPInfoBaseAddr_Msk (0xffff0000UL)
10354 /* -------------------------------- USB_HPTXFSIZ -------------------------------- */
10355 #define USB_HPTXFSIZ_PTxFStAddr_Pos (0UL)
10356 #define USB_HPTXFSIZ_PTxFStAddr_Msk (0xffffUL)
10357 #define USB_HPTXFSIZ_PTxFSize_Pos (16UL)
10358 #define USB_HPTXFSIZ_PTxFSize_Msk (0xffff0000UL)
10360 /* -------------------------------- USB_DIEPTXF1 -------------------------------- */
10361 #define USB_DIEPTXF1_INEPnTxFStAddr_Pos (0UL)
10362 #define USB_DIEPTXF1_INEPnTxFStAddr_Msk (0xffffUL)
10363 #define USB_DIEPTXF1_INEPnTxFDep_Pos (16UL)
10364 #define USB_DIEPTXF1_INEPnTxFDep_Msk (0xffff0000UL)
10366 /* -------------------------------- USB_DIEPTXF2 -------------------------------- */
10367 #define USB_DIEPTXF2_INEPnTxFStAddr_Pos (0UL)
10368 #define USB_DIEPTXF2_INEPnTxFStAddr_Msk (0xffffUL)
10369 #define USB_DIEPTXF2_INEPnTxFDep_Pos (16UL)
10370 #define USB_DIEPTXF2_INEPnTxFDep_Msk (0xffff0000UL)
10372 /* -------------------------------- USB_DIEPTXF3 -------------------------------- */
10373 #define USB_DIEPTXF3_INEPnTxFStAddr_Pos (0UL)
10374 #define USB_DIEPTXF3_INEPnTxFStAddr_Msk (0xffffUL)
10375 #define USB_DIEPTXF3_INEPnTxFDep_Pos (16UL)
10376 #define USB_DIEPTXF3_INEPnTxFDep_Msk (0xffff0000UL)
10378 /* -------------------------------- USB_DIEPTXF4 -------------------------------- */
10379 #define USB_DIEPTXF4_INEPnTxFStAddr_Pos (0UL)
10380 #define USB_DIEPTXF4_INEPnTxFStAddr_Msk (0xffffUL)
10381 #define USB_DIEPTXF4_INEPnTxFDep_Pos (16UL)
10382 #define USB_DIEPTXF4_INEPnTxFDep_Msk (0xffff0000UL)
10384 /* -------------------------------- USB_DIEPTXF5 -------------------------------- */
10385 #define USB_DIEPTXF5_INEPnTxFStAddr_Pos (0UL)
10386 #define USB_DIEPTXF5_INEPnTxFStAddr_Msk (0xffffUL)
10387 #define USB_DIEPTXF5_INEPnTxFDep_Pos (16UL)
10388 #define USB_DIEPTXF5_INEPnTxFDep_Msk (0xffff0000UL)
10390 /* -------------------------------- USB_DIEPTXF6 -------------------------------- */
10391 #define USB_DIEPTXF6_INEPnTxFStAddr_Pos (0UL)
10392 #define USB_DIEPTXF6_INEPnTxFStAddr_Msk (0xffffUL)
10393 #define USB_DIEPTXF6_INEPnTxFDep_Pos (16UL)
10394 #define USB_DIEPTXF6_INEPnTxFDep_Msk (0xffff0000UL)
10396 /* ---------------------------------- USB_HCFG ---------------------------------- */
10397 #define USB_HCFG_FSLSPclkSel_Pos (0UL)
10398 #define USB_HCFG_FSLSPclkSel_Msk (0x3UL)
10399 #define USB_HCFG_FSLSSupp_Pos (2UL)
10400 #define USB_HCFG_FSLSSupp_Msk (0x4UL)
10401 #define USB_HCFG_DescDMA_Pos (23UL)
10402 #define USB_HCFG_DescDMA_Msk (0x800000UL)
10403 #define USB_HCFG_FrListEn_Pos (24UL)
10404 #define USB_HCFG_FrListEn_Msk (0x3000000UL)
10405 #define USB_HCFG_PerSchedEna_Pos (26UL)
10406 #define USB_HCFG_PerSchedEna_Msk (0x4000000UL)
10408 /* ---------------------------------- USB_HFIR ---------------------------------- */
10409 #define USB_HFIR_FrInt_Pos (0UL)
10410 #define USB_HFIR_FrInt_Msk (0xffffUL)
10411 #define USB_HFIR_HFIRRldCtrl_Pos (16UL)
10412 #define USB_HFIR_HFIRRldCtrl_Msk (0x10000UL)
10414 /* ---------------------------------- USB_HFNUM --------------------------------- */
10415 #define USB_HFNUM_FrNum_Pos (0UL)
10416 #define USB_HFNUM_FrNum_Msk (0xffffUL)
10417 #define USB_HFNUM_FrRem_Pos (16UL)
10418 #define USB_HFNUM_FrRem_Msk (0xffff0000UL)
10420 /* --------------------------------- USB_HPTXSTS -------------------------------- */
10421 #define USB_HPTXSTS_PTxFSpcAvail_Pos (0UL)
10422 #define USB_HPTXSTS_PTxFSpcAvail_Msk (0xffffUL)
10423 #define USB_HPTXSTS_PTxQSpcAvail_Pos (16UL)
10424 #define USB_HPTXSTS_PTxQSpcAvail_Msk (0xff0000UL)
10425 #define USB_HPTXSTS_PTxQTop_Pos (24UL)
10426 #define USB_HPTXSTS_PTxQTop_Msk (0xff000000UL)
10428 /* ---------------------------------- USB_HAINT --------------------------------- */
10429 #define USB_HAINT_HAINT_Pos (0UL)
10430 #define USB_HAINT_HAINT_Msk (0x3fffUL)
10432 /* -------------------------------- USB_HAINTMSK -------------------------------- */
10433 #define USB_HAINTMSK_HAINTMsk_Pos (0UL)
10434 #define USB_HAINTMSK_HAINTMsk_Msk (0x3fffUL)
10436 /* -------------------------------- USB_HFLBADDR -------------------------------- */
10437 #define USB_HFLBADDR_Starting_Address_Pos (0UL)
10438 #define USB_HFLBADDR_Starting_Address_Msk (0xffffffffUL)
10440 /* ---------------------------------- USB_HPRT ---------------------------------- */
10441 #define USB_HPRT_PrtConnSts_Pos (0UL)
10442 #define USB_HPRT_PrtConnSts_Msk (0x1UL)
10443 #define USB_HPRT_PrtConnDet_Pos (1UL)
10444 #define USB_HPRT_PrtConnDet_Msk (0x2UL)
10445 #define USB_HPRT_PrtEna_Pos (2UL)
10446 #define USB_HPRT_PrtEna_Msk (0x4UL)
10447 #define USB_HPRT_PrtEnChng_Pos (3UL)
10448 #define USB_HPRT_PrtEnChng_Msk (0x8UL)
10449 #define USB_HPRT_PrtOvrCurrAct_Pos (4UL)
10450 #define USB_HPRT_PrtOvrCurrAct_Msk (0x10UL)
10451 #define USB_HPRT_PrtOvrCurrChng_Pos (5UL)
10452 #define USB_HPRT_PrtOvrCurrChng_Msk (0x20UL)
10453 #define USB_HPRT_PrtRes_Pos (6UL)
10454 #define USB_HPRT_PrtRes_Msk (0x40UL)
10455 #define USB_HPRT_PrtSusp_Pos (7UL)
10456 #define USB_HPRT_PrtSusp_Msk (0x80UL)
10457 #define USB_HPRT_PrtRst_Pos (8UL)
10458 #define USB_HPRT_PrtRst_Msk (0x100UL)
10459 #define USB_HPRT_PrtLnSts_Pos (10UL)
10460 #define USB_HPRT_PrtLnSts_Msk (0xc00UL)
10461 #define USB_HPRT_PrtPwr_Pos (12UL)
10462 #define USB_HPRT_PrtPwr_Msk (0x1000UL)
10463 #define USB_HPRT_PrtSpd_Pos (17UL)
10464 #define USB_HPRT_PrtSpd_Msk (0x60000UL)
10466 /* ---------------------------------- USB_DCFG ---------------------------------- */
10467 #define USB_DCFG_DevSpd_Pos (0UL)
10468 #define USB_DCFG_DevSpd_Msk (0x3UL)
10469 #define USB_DCFG_NZStsOUTHShk_Pos (2UL)
10470 #define USB_DCFG_NZStsOUTHShk_Msk (0x4UL)
10471 #define USB_DCFG_DevAddr_Pos (4UL)
10472 #define USB_DCFG_DevAddr_Msk (0x7f0UL)
10473 #define USB_DCFG_PerFrInt_Pos (11UL)
10474 #define USB_DCFG_PerFrInt_Msk (0x1800UL)
10475 #define USB_DCFG_DescDMA_Pos (23UL)
10476 #define USB_DCFG_DescDMA_Msk (0x800000UL)
10477 #define USB_DCFG_PerSchIntvl_Pos (24UL)
10478 #define USB_DCFG_PerSchIntvl_Msk (0x3000000UL)
10480 /* ---------------------------------- USB_DCTL ---------------------------------- */
10481 #define USB_DCTL_RmtWkUpSig_Pos (0UL)
10482 #define USB_DCTL_RmtWkUpSig_Msk (0x1UL)
10483 #define USB_DCTL_SftDiscon_Pos (1UL)
10484 #define USB_DCTL_SftDiscon_Msk (0x2UL)
10485 #define USB_DCTL_GNPINNakSts_Pos (2UL)
10486 #define USB_DCTL_GNPINNakSts_Msk (0x4UL)
10487 #define USB_DCTL_GOUTNakSts_Pos (3UL)
10488 #define USB_DCTL_GOUTNakSts_Msk (0x8UL)
10489 #define USB_DCTL_SGNPInNak_Pos (7UL)
10490 #define USB_DCTL_SGNPInNak_Msk (0x80UL)
10491 #define USB_DCTL_CGNPInNak_Pos (8UL)
10492 #define USB_DCTL_CGNPInNak_Msk (0x100UL)
10493 #define USB_DCTL_SGOUTNak_Pos (9UL)
10494 #define USB_DCTL_SGOUTNak_Msk (0x200UL)
10495 #define USB_DCTL_CGOUTNak_Pos (10UL)
10496 #define USB_DCTL_CGOUTNak_Msk (0x400UL)
10497 #define USB_DCTL_GMC_Pos (13UL)
10498 #define USB_DCTL_GMC_Msk (0x6000UL)
10499 #define USB_DCTL_IgnrFrmNum_Pos (15UL)
10500 #define USB_DCTL_IgnrFrmNum_Msk (0x8000UL)
10501 #define USB_DCTL_NakOnBble_Pos (16UL)
10502 #define USB_DCTL_NakOnBble_Msk (0x10000UL)
10503 #define USB_DCTL_EnContOnBNA_Pos (17UL)
10504 #define USB_DCTL_EnContOnBNA_Msk (0x20000UL)
10506 /* ---------------------------------- USB_DSTS ---------------------------------- */
10507 #define USB_DSTS_SuspSts_Pos (0UL)
10508 #define USB_DSTS_SuspSts_Msk (0x1UL)
10509 #define USB_DSTS_EnumSpd_Pos (1UL)
10510 #define USB_DSTS_EnumSpd_Msk (0x6UL)
10511 #define USB_DSTS_ErrticErr_Pos (3UL)
10512 #define USB_DSTS_ErrticErr_Msk (0x8UL)
10513 #define USB_DSTS_SOFFN_Pos (8UL)
10514 #define USB_DSTS_SOFFN_Msk (0x3fff00UL)
10516 /* --------------------------------- USB_DIEPMSK -------------------------------- */
10517 #define USB_DIEPMSK_XferComplMsk_Pos (0UL)
10518 #define USB_DIEPMSK_XferComplMsk_Msk (0x1UL)
10519 #define USB_DIEPMSK_EPDisbldMsk_Pos (1UL)
10520 #define USB_DIEPMSK_EPDisbldMsk_Msk (0x2UL)
10521 #define USB_DIEPMSK_AHBErrMsk_Pos (2UL)
10522 #define USB_DIEPMSK_AHBErrMsk_Msk (0x4UL)
10523 #define USB_DIEPMSK_TimeOUTMsk_Pos (3UL)
10524 #define USB_DIEPMSK_TimeOUTMsk_Msk (0x8UL)
10525 #define USB_DIEPMSK_INTknTXFEmpMsk_Pos (4UL)
10526 #define USB_DIEPMSK_INTknTXFEmpMsk_Msk (0x10UL)
10527 #define USB_DIEPMSK_INEPNakEffMsk_Pos (6UL)
10528 #define USB_DIEPMSK_INEPNakEffMsk_Msk (0x40UL)
10529 #define USB_DIEPMSK_TxfifoUndrnMsk_Pos (8UL)
10530 #define USB_DIEPMSK_TxfifoUndrnMsk_Msk (0x100UL)
10531 #define USB_DIEPMSK_BNAInIntrMsk_Pos (9UL)
10532 #define USB_DIEPMSK_BNAInIntrMsk_Msk (0x200UL)
10533 #define USB_DIEPMSK_NAKMsk_Pos (13UL)
10534 #define USB_DIEPMSK_NAKMsk_Msk (0x2000UL)
10536 /* --------------------------------- USB_DOEPMSK -------------------------------- */
10537 #define USB_DOEPMSK_XferComplMsk_Pos (0UL)
10538 #define USB_DOEPMSK_XferComplMsk_Msk (0x1UL)
10539 #define USB_DOEPMSK_EPDisbldMsk_Pos (1UL)
10540 #define USB_DOEPMSK_EPDisbldMsk_Msk (0x2UL)
10541 #define USB_DOEPMSK_AHBErrMsk_Pos (2UL)
10542 #define USB_DOEPMSK_AHBErrMsk_Msk (0x4UL)
10543 #define USB_DOEPMSK_SetUPMsk_Pos (3UL)
10544 #define USB_DOEPMSK_SetUPMsk_Msk (0x8UL)
10545 #define USB_DOEPMSK_OUTTknEPdisMsk_Pos (4UL)
10546 #define USB_DOEPMSK_OUTTknEPdisMsk_Msk (0x10UL)
10547 #define USB_DOEPMSK_Back2BackSETup_Pos (6UL)
10548 #define USB_DOEPMSK_Back2BackSETup_Msk (0x40UL)
10549 #define USB_DOEPMSK_OutPktErrMsk_Pos (8UL)
10550 #define USB_DOEPMSK_OutPktErrMsk_Msk (0x100UL)
10551 #define USB_DOEPMSK_BnaOutIntrMsk_Pos (9UL)
10552 #define USB_DOEPMSK_BnaOutIntrMsk_Msk (0x200UL)
10553 #define USB_DOEPMSK_BbleErrMsk_Pos (12UL)
10554 #define USB_DOEPMSK_BbleErrMsk_Msk (0x1000UL)
10555 #define USB_DOEPMSK_NAKMsk_Pos (13UL)
10556 #define USB_DOEPMSK_NAKMsk_Msk (0x2000UL)
10557 #define USB_DOEPMSK_NYETMsk_Pos (14UL)
10558 #define USB_DOEPMSK_NYETMsk_Msk (0x4000UL)
10560 /* ---------------------------------- USB_DAINT --------------------------------- */
10561 #define USB_DAINT_InEpInt_Pos (0UL)
10562 #define USB_DAINT_InEpInt_Msk (0xffffUL)
10563 #define USB_DAINT_OutEPInt_Pos (16UL)
10564 #define USB_DAINT_OutEPInt_Msk (0xffff0000UL)
10566 /* -------------------------------- USB_DAINTMSK -------------------------------- */
10567 #define USB_DAINTMSK_InEpMsk_Pos (0UL)
10568 #define USB_DAINTMSK_InEpMsk_Msk (0xffffUL)
10569 #define USB_DAINTMSK_OutEpMsk_Pos (16UL)
10570 #define USB_DAINTMSK_OutEpMsk_Msk (0xffff0000UL)
10572 /* -------------------------------- USB_DVBUSDIS -------------------------------- */
10573 #define USB_DVBUSDIS_DVBUSDis_Pos (0UL)
10574 #define USB_DVBUSDIS_DVBUSDis_Msk (0xffffUL)
10576 /* ------------------------------- USB_DVBUSPULSE ------------------------------- */
10577 #define USB_DVBUSPULSE_DVBUSPulse_Pos (0UL)
10578 #define USB_DVBUSPULSE_DVBUSPulse_Msk (0xfffUL)
10580 /* ------------------------------- USB_DIEPEMPMSK ------------------------------- */
10581 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Pos (0UL)
10582 #define USB_DIEPEMPMSK_InEpTxfEmpMsk_Msk (0xffffUL)
10584 /* --------------------------------- USB_PCGCCTL -------------------------------- */
10585 #define USB_PCGCCTL_StopPclk_Pos (0UL)
10586 #define USB_PCGCCTL_StopPclk_Msk (0x1UL)
10587 #define USB_PCGCCTL_GateHclk_Pos (1UL)
10588 #define USB_PCGCCTL_GateHclk_Msk (0x2UL)
10591 /* ================================================================================ */
10592 /* ================ struct 'USB0_EP0' Position & Mask ================ */
10593 /* ================================================================================ */
10594 
10595 
10596 /* ------------------------------ USB_EP_DIEPCTL0 ----------------------------- */
10597 #define USB_EP_DIEPCTL0_MPS_Pos (0UL)
10598 #define USB_EP_DIEPCTL0_MPS_Msk (0x3UL)
10599 #define USB_EP_DIEPCTL0_USBActEP_Pos (15UL)
10600 #define USB_EP_DIEPCTL0_USBActEP_Msk (0x8000UL)
10601 #define USB_EP_DIEPCTL0_NAKSts_Pos (17UL)
10602 #define USB_EP_DIEPCTL0_NAKSts_Msk (0x20000UL)
10603 #define USB_EP_DIEPCTL0_EPType_Pos (18UL)
10604 #define USB_EP_DIEPCTL0_EPType_Msk (0xc0000UL)
10605 #define USB_EP_DIEPCTL0_Stall_Pos (21UL)
10606 #define USB_EP_DIEPCTL0_Stall_Msk (0x200000UL)
10607 #define USB_EP_DIEPCTL0_TxFNum_Pos (22UL)
10608 #define USB_EP_DIEPCTL0_TxFNum_Msk (0x3c00000UL)
10609 #define USB_EP_DIEPCTL0_CNAK_Pos (26UL)
10610 #define USB_EP_DIEPCTL0_CNAK_Msk (0x4000000UL)
10611 #define USB_EP_DIEPCTL0_SNAK_Pos (27UL)
10612 #define USB_EP_DIEPCTL0_SNAK_Msk (0x8000000UL)
10613 #define USB_EP_DIEPCTL0_EPDis_Pos (30UL)
10614 #define USB_EP_DIEPCTL0_EPDis_Msk (0x40000000UL)
10615 #define USB_EP_DIEPCTL0_EPEna_Pos (31UL)
10616 #define USB_EP_DIEPCTL0_EPEna_Msk (0x80000000UL)
10618 /* ------------------------------ USB_EP_DIEPINT0 ----------------------------- */
10619 #define USB_EP_DIEPINT0_XferCompl_Pos (0UL)
10620 #define USB_EP_DIEPINT0_XferCompl_Msk (0x1UL)
10621 #define USB_EP_DIEPINT0_EPDisbld_Pos (1UL)
10622 #define USB_EP_DIEPINT0_EPDisbld_Msk (0x2UL)
10623 #define USB_EP_DIEPINT0_AHBErr_Pos (2UL)
10624 #define USB_EP_DIEPINT0_AHBErr_Msk (0x4UL)
10625 #define USB_EP_DIEPINT0_TimeOUT_Pos (3UL)
10626 #define USB_EP_DIEPINT0_TimeOUT_Msk (0x8UL)
10627 #define USB_EP_DIEPINT0_INTknTXFEmp_Pos (4UL)
10628 #define USB_EP_DIEPINT0_INTknTXFEmp_Msk (0x10UL)
10629 #define USB_EP_DIEPINT0_INEPNakEff_Pos (6UL)
10630 #define USB_EP_DIEPINT0_INEPNakEff_Msk (0x40UL)
10631 #define USB_EP_DIEPINT0_TxFEmp_Pos (7UL)
10632 #define USB_EP_DIEPINT0_TxFEmp_Msk (0x80UL)
10633 #define USB_EP_DIEPINT0_BNAIntr_Pos (9UL)
10634 #define USB_EP_DIEPINT0_BNAIntr_Msk (0x200UL)
10636 /* ----------------------------- USB_EP_DIEPTSIZ0 ----------------------------- */
10637 #define USB_EP_DIEPTSIZ0_XferSize_Pos (0UL)
10638 #define USB_EP_DIEPTSIZ0_XferSize_Msk (0x7fUL)
10639 #define USB_EP_DIEPTSIZ0_PktCnt_Pos (19UL)
10640 #define USB_EP_DIEPTSIZ0_PktCnt_Msk (0x180000UL)
10642 /* ------------------------------ USB_EP_DIEPDMA0 ----------------------------- */
10643 #define USB_EP_DIEPDMA0_DMAAddr_Pos (0UL)
10644 #define USB_EP_DIEPDMA0_DMAAddr_Msk (0xffffffffUL)
10646 /* ------------------------------ USB_EP_DTXFSTS0 ----------------------------- */
10647 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Pos (0UL)
10648 #define USB_EP_DTXFSTS0_INEPTxFSpcAvail_Msk (0xffffUL)
10650 /* ----------------------------- USB_EP_DIEPDMAB0 ----------------------------- */
10651 #define USB_EP_DIEPDMAB0_DMABufferAddr_Pos (0UL)
10652 #define USB_EP_DIEPDMAB0_DMABufferAddr_Msk (0xffffffffUL)
10654 /* ------------------------------ USB_EP_DOEPCTL0 ----------------------------- */
10655 #define USB_EP_DOEPCTL0_MPS_Pos (0UL)
10656 #define USB_EP_DOEPCTL0_MPS_Msk (0x3UL)
10657 #define USB_EP_DOEPCTL0_USBActEP_Pos (15UL)
10658 #define USB_EP_DOEPCTL0_USBActEP_Msk (0x8000UL)
10659 #define USB_EP_DOEPCTL0_NAKSts_Pos (17UL)
10660 #define USB_EP_DOEPCTL0_NAKSts_Msk (0x20000UL)
10661 #define USB_EP_DOEPCTL0_EPType_Pos (18UL)
10662 #define USB_EP_DOEPCTL0_EPType_Msk (0xc0000UL)
10663 #define USB_EP_DOEPCTL0_Snp_Pos (20UL)
10664 #define USB_EP_DOEPCTL0_Snp_Msk (0x100000UL)
10665 #define USB_EP_DOEPCTL0_Stall_Pos (21UL)
10666 #define USB_EP_DOEPCTL0_Stall_Msk (0x200000UL)
10667 #define USB_EP_DOEPCTL0_CNAK_Pos (26UL)
10668 #define USB_EP_DOEPCTL0_CNAK_Msk (0x4000000UL)
10669 #define USB_EP_DOEPCTL0_SNAK_Pos (27UL)
10670 #define USB_EP_DOEPCTL0_SNAK_Msk (0x8000000UL)
10671 #define USB_EP_DOEPCTL0_EPDis_Pos (30UL)
10672 #define USB_EP_DOEPCTL0_EPDis_Msk (0x40000000UL)
10673 #define USB_EP_DOEPCTL0_EPEna_Pos (31UL)
10674 #define USB_EP_DOEPCTL0_EPEna_Msk (0x80000000UL)
10676 /* ------------------------------ USB_EP_DOEPINT0 ----------------------------- */
10677 #define USB_EP_DOEPINT0_XferCompl_Pos (0UL)
10678 #define USB_EP_DOEPINT0_XferCompl_Msk (0x1UL)
10679 #define USB_EP_DOEPINT0_EPDisbld_Pos (1UL)
10680 #define USB_EP_DOEPINT0_EPDisbld_Msk (0x2UL)
10681 #define USB_EP_DOEPINT0_AHBErr_Pos (2UL)
10682 #define USB_EP_DOEPINT0_AHBErr_Msk (0x4UL)
10683 #define USB_EP_DOEPINT0_SetUp_Pos (3UL)
10684 #define USB_EP_DOEPINT0_SetUp_Msk (0x8UL)
10685 #define USB_EP_DOEPINT0_OUTTknEPdis_Pos (4UL)
10686 #define USB_EP_DOEPINT0_OUTTknEPdis_Msk (0x10UL)
10687 #define USB_EP_DOEPINT0_StsPhseRcvd_Pos (5UL)
10688 #define USB_EP_DOEPINT0_StsPhseRcvd_Msk (0x20UL)
10689 #define USB_EP_DOEPINT0_Back2BackSETup_Pos (6UL)
10690 #define USB_EP_DOEPINT0_Back2BackSETup_Msk (0x40UL)
10691 #define USB_EP_DOEPINT0_BNAIntr_Pos (9UL)
10692 #define USB_EP_DOEPINT0_BNAIntr_Msk (0x200UL)
10693 #define USB_EP_DOEPINT0_PktDrpSts_Pos (11UL)
10694 #define USB_EP_DOEPINT0_PktDrpSts_Msk (0x800UL)
10695 #define USB_EP_DOEPINT0_BbleErrIntrpt_Pos (12UL)
10696 #define USB_EP_DOEPINT0_BbleErrIntrpt_Msk (0x1000UL)
10697 #define USB_EP_DOEPINT0_NAKIntrpt_Pos (13UL)
10698 #define USB_EP_DOEPINT0_NAKIntrpt_Msk (0x2000UL)
10699 #define USB_EP_DOEPINT0_NYETIntrpt_Pos (14UL)
10700 #define USB_EP_DOEPINT0_NYETIntrpt_Msk (0x4000UL)
10702 /* ----------------------------- USB_EP_DOEPTSIZ0 ----------------------------- */
10703 #define USB_EP_DOEPTSIZ0_XferSize_Pos (0UL)
10704 #define USB_EP_DOEPTSIZ0_XferSize_Msk (0x7fUL)
10705 #define USB_EP_DOEPTSIZ0_PktCnt_Pos (19UL)
10706 #define USB_EP_DOEPTSIZ0_PktCnt_Msk (0x180000UL)
10707 #define USB_EP_DOEPTSIZ0_SUPCnt_Pos (29UL)
10708 #define USB_EP_DOEPTSIZ0_SUPCnt_Msk (0x60000000UL)
10710 /* ------------------------------ USB_EP_DOEPDMA0 ----------------------------- */
10711 #define USB_EP_DOEPDMA0_DMAAddr_Pos (0UL)
10712 #define USB_EP_DOEPDMA0_DMAAddr_Msk (0xffffffffUL)
10714 /* ----------------------------- USB_EP_DOEPDMAB0 ----------------------------- */
10715 #define USB_EP_DOEPDMAB0_DMABufferAddr_Pos (0UL)
10716 #define USB_EP_DOEPDMAB0_DMABufferAddr_Msk (0xffffffffUL)
10719 /* ================================================================================ */
10720 /* ================ Group 'USB_EP' Position & Mask ================ */
10721 /* ================================================================================ */
10722 
10723 
10724 /* --------------------------- USB_EP_DIEPCTL_ISOCONT --------------------------- */
10725 #define USB_EP_DIEPCTL_ISOCONT_MPS_Pos (0UL)
10726 #define USB_EP_DIEPCTL_ISOCONT_MPS_Msk (0x7ffUL)
10727 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Pos (15UL)
10728 #define USB_EP_DIEPCTL_ISOCONT_USBActEP_Msk (0x8000UL)
10729 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Pos (16UL)
10730 #define USB_EP_DIEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL)
10731 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Pos (17UL)
10732 #define USB_EP_DIEPCTL_ISOCONT_NAKSts_Msk (0x20000UL)
10733 #define USB_EP_DIEPCTL_ISOCONT_EPType_Pos (18UL)
10734 #define USB_EP_DIEPCTL_ISOCONT_EPType_Msk (0xc0000UL)
10735 #define USB_EP_DIEPCTL_ISOCONT_Snp_Pos (20UL)
10736 #define USB_EP_DIEPCTL_ISOCONT_Snp_Msk (0x100000UL)
10737 #define USB_EP_DIEPCTL_ISOCONT_Stall_Pos (21UL)
10738 #define USB_EP_DIEPCTL_ISOCONT_Stall_Msk (0x200000UL)
10739 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Pos (22UL)
10740 #define USB_EP_DIEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL)
10741 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Pos (26UL)
10742 #define USB_EP_DIEPCTL_ISOCONT_CNAK_Msk (0x4000000UL)
10743 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Pos (27UL)
10744 #define USB_EP_DIEPCTL_ISOCONT_SNAK_Msk (0x8000000UL)
10745 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Pos (28UL)
10746 #define USB_EP_DIEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL)
10747 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Pos (29UL)
10748 #define USB_EP_DIEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL)
10749 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Pos (30UL)
10750 #define USB_EP_DIEPCTL_ISOCONT_EPDis_Msk (0x40000000UL)
10751 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Pos (31UL)
10752 #define USB_EP_DIEPCTL_ISOCONT_EPEna_Msk (0x80000000UL)
10754 /* --------------------------- USB_EP_DIEPCTL_INTBULK --------------------------- */
10755 #define USB_EP_DIEPCTL_INTBULK_MPS_Pos (0UL)
10756 #define USB_EP_DIEPCTL_INTBULK_MPS_Msk (0x7ffUL)
10757 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Pos (15UL)
10758 #define USB_EP_DIEPCTL_INTBULK_USBActEP_Msk (0x8000UL)
10759 #define USB_EP_DIEPCTL_INTBULK_DPID_Pos (16UL)
10760 #define USB_EP_DIEPCTL_INTBULK_DPID_Msk (0x10000UL)
10761 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Pos (17UL)
10762 #define USB_EP_DIEPCTL_INTBULK_NAKSts_Msk (0x20000UL)
10763 #define USB_EP_DIEPCTL_INTBULK_EPType_Pos (18UL)
10764 #define USB_EP_DIEPCTL_INTBULK_EPType_Msk (0xc0000UL)
10765 #define USB_EP_DIEPCTL_INTBULK_Snp_Pos (20UL)
10766 #define USB_EP_DIEPCTL_INTBULK_Snp_Msk (0x100000UL)
10767 #define USB_EP_DIEPCTL_INTBULK_Stall_Pos (21UL)
10768 #define USB_EP_DIEPCTL_INTBULK_Stall_Msk (0x200000UL)
10769 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Pos (22UL)
10770 #define USB_EP_DIEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL)
10771 #define USB_EP_DIEPCTL_INTBULK_CNAK_Pos (26UL)
10772 #define USB_EP_DIEPCTL_INTBULK_CNAK_Msk (0x4000000UL)
10773 #define USB_EP_DIEPCTL_INTBULK_SNAK_Pos (27UL)
10774 #define USB_EP_DIEPCTL_INTBULK_SNAK_Msk (0x8000000UL)
10775 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Pos (28UL)
10776 #define USB_EP_DIEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL)
10777 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Pos (29UL)
10778 #define USB_EP_DIEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL)
10779 #define USB_EP_DIEPCTL_INTBULK_EPDis_Pos (30UL)
10780 #define USB_EP_DIEPCTL_INTBULK_EPDis_Msk (0x40000000UL)
10781 #define USB_EP_DIEPCTL_INTBULK_EPEna_Pos (31UL)
10782 #define USB_EP_DIEPCTL_INTBULK_EPEna_Msk (0x80000000UL)
10784 /* ------------------------------- USB_EP_DIEPINT ------------------------------- */
10785 #define USB_EP_DIEPINT_XferCompl_Pos (0UL)
10786 #define USB_EP_DIEPINT_XferCompl_Msk (0x1UL)
10787 #define USB_EP_DIEPINT_EPDisbld_Pos (1UL)
10788 #define USB_EP_DIEPINT_EPDisbld_Msk (0x2UL)
10789 #define USB_EP_DIEPINT_AHBErr_Pos (2UL)
10790 #define USB_EP_DIEPINT_AHBErr_Msk (0x4UL)
10791 #define USB_EP_DIEPINT_TimeOUT_Pos (3UL)
10792 #define USB_EP_DIEPINT_TimeOUT_Msk (0x8UL)
10793 #define USB_EP_DIEPINT_INTknTXFEmp_Pos (4UL)
10794 #define USB_EP_DIEPINT_INTknTXFEmp_Msk (0x10UL)
10795 #define USB_EP_DIEPINT_INEPNakEff_Pos (6UL)
10796 #define USB_EP_DIEPINT_INEPNakEff_Msk (0x40UL)
10797 #define USB_EP_DIEPINT_TxFEmp_Pos (7UL)
10798 #define USB_EP_DIEPINT_TxFEmp_Msk (0x80UL)
10799 #define USB_EP_DIEPINT_BNAIntr_Pos (9UL)
10800 #define USB_EP_DIEPINT_BNAIntr_Msk (0x200UL)
10802 /* ------------------------------- USB_EP_DIEPTSIZ ------------------------------ */
10803 #define USB_EP_DIEPTSIZ_XferSize_Pos (0UL)
10804 #define USB_EP_DIEPTSIZ_XferSize_Msk (0x7ffffUL)
10805 #define USB_EP_DIEPTSIZ_PktCnt_Pos (19UL)
10806 #define USB_EP_DIEPTSIZ_PktCnt_Msk (0x1ff80000UL)
10808 /* ------------------------------- USB_EP_DIEPDMA ------------------------------- */
10809 #define USB_EP_DIEPDMA_DMAAddr_Pos (0UL)
10810 #define USB_EP_DIEPDMA_DMAAddr_Msk (0xffffffffUL)
10812 /* ------------------------------- USB_EP_DTXFSTS ------------------------------- */
10813 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Pos (0UL)
10814 #define USB_EP_DTXFSTS_INEPTxFSpcAvail_Msk (0xffffUL)
10816 /* ------------------------------- USB_EP_DIEPDMAB ------------------------------ */
10817 #define USB_EP_DIEPDMAB_DMABufferAddr_Pos (0UL)
10818 #define USB_EP_DIEPDMAB_DMABufferAddr_Msk (0xffffffffUL)
10820 /* --------------------------- USB_EP_DOEPCTL_ISOCONT --------------------------- */
10821 #define USB_EP_DOEPCTL_ISOCONT_MPS_Pos (0UL)
10822 #define USB_EP_DOEPCTL_ISOCONT_MPS_Msk (0x7ffUL)
10823 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Pos (15UL)
10824 #define USB_EP_DOEPCTL_ISOCONT_USBActEP_Msk (0x8000UL)
10825 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Pos (16UL)
10826 #define USB_EP_DOEPCTL_ISOCONT_EO_FrNum_Msk (0x10000UL)
10827 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Pos (17UL)
10828 #define USB_EP_DOEPCTL_ISOCONT_NAKSts_Msk (0x20000UL)
10829 #define USB_EP_DOEPCTL_ISOCONT_EPType_Pos (18UL)
10830 #define USB_EP_DOEPCTL_ISOCONT_EPType_Msk (0xc0000UL)
10831 #define USB_EP_DOEPCTL_ISOCONT_Snp_Pos (20UL)
10832 #define USB_EP_DOEPCTL_ISOCONT_Snp_Msk (0x100000UL)
10833 #define USB_EP_DOEPCTL_ISOCONT_Stall_Pos (21UL)
10834 #define USB_EP_DOEPCTL_ISOCONT_Stall_Msk (0x200000UL)
10835 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Pos (22UL)
10836 #define USB_EP_DOEPCTL_ISOCONT_TxFNum_Msk (0x3c00000UL)
10837 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Pos (26UL)
10838 #define USB_EP_DOEPCTL_ISOCONT_CNAK_Msk (0x4000000UL)
10839 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Pos (27UL)
10840 #define USB_EP_DOEPCTL_ISOCONT_SNAK_Msk (0x8000000UL)
10841 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Pos (28UL)
10842 #define USB_EP_DOEPCTL_ISOCONT_SetEvenFr_Msk (0x10000000UL)
10843 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Pos (29UL)
10844 #define USB_EP_DOEPCTL_ISOCONT_SetOddFr_Msk (0x20000000UL)
10845 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Pos (30UL)
10846 #define USB_EP_DOEPCTL_ISOCONT_EPDis_Msk (0x40000000UL)
10847 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Pos (31UL)
10848 #define USB_EP_DOEPCTL_ISOCONT_EPEna_Msk (0x80000000UL)
10850 /* --------------------------- USB_EP_DOEPCTL_INTBULK --------------------------- */
10851 #define USB_EP_DOEPCTL_INTBULK_MPS_Pos (0UL)
10852 #define USB_EP_DOEPCTL_INTBULK_MPS_Msk (0x7ffUL)
10853 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Pos (15UL)
10854 #define USB_EP_DOEPCTL_INTBULK_USBActEP_Msk (0x8000UL)
10855 #define USB_EP_DOEPCTL_INTBULK_DPID_Pos (16UL)
10856 #define USB_EP_DOEPCTL_INTBULK_DPID_Msk (0x10000UL)
10857 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Pos (17UL)
10858 #define USB_EP_DOEPCTL_INTBULK_NAKSts_Msk (0x20000UL)
10859 #define USB_EP_DOEPCTL_INTBULK_EPType_Pos (18UL)
10860 #define USB_EP_DOEPCTL_INTBULK_EPType_Msk (0xc0000UL)
10861 #define USB_EP_DOEPCTL_INTBULK_Snp_Pos (20UL)
10862 #define USB_EP_DOEPCTL_INTBULK_Snp_Msk (0x100000UL)
10863 #define USB_EP_DOEPCTL_INTBULK_Stall_Pos (21UL)
10864 #define USB_EP_DOEPCTL_INTBULK_Stall_Msk (0x200000UL)
10865 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Pos (22UL)
10866 #define USB_EP_DOEPCTL_INTBULK_TxFNum_Msk (0x3c00000UL)
10867 #define USB_EP_DOEPCTL_INTBULK_CNAK_Pos (26UL)
10868 #define USB_EP_DOEPCTL_INTBULK_CNAK_Msk (0x4000000UL)
10869 #define USB_EP_DOEPCTL_INTBULK_SNAK_Pos (27UL)
10870 #define USB_EP_DOEPCTL_INTBULK_SNAK_Msk (0x8000000UL)
10871 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Pos (28UL)
10872 #define USB_EP_DOEPCTL_INTBULK_SetD0PID_Msk (0x10000000UL)
10873 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Pos (29UL)
10874 #define USB_EP_DOEPCTL_INTBULK_SetD1PID_Msk (0x20000000UL)
10875 #define USB_EP_DOEPCTL_INTBULK_EPDis_Pos (30UL)
10876 #define USB_EP_DOEPCTL_INTBULK_EPDis_Msk (0x40000000UL)
10877 #define USB_EP_DOEPCTL_INTBULK_EPEna_Pos (31UL)
10878 #define USB_EP_DOEPCTL_INTBULK_EPEna_Msk (0x80000000UL)
10880 /* ------------------------------- USB_EP_DOEPINT ------------------------------- */
10881 #define USB_EP_DOEPINT_XferCompl_Pos (0UL)
10882 #define USB_EP_DOEPINT_XferCompl_Msk (0x1UL)
10883 #define USB_EP_DOEPINT_EPDisbld_Pos (1UL)
10884 #define USB_EP_DOEPINT_EPDisbld_Msk (0x2UL)
10885 #define USB_EP_DOEPINT_AHBErr_Pos (2UL)
10886 #define USB_EP_DOEPINT_AHBErr_Msk (0x4UL)
10887 #define USB_EP_DOEPINT_SetUp_Pos (3UL)
10888 #define USB_EP_DOEPINT_SetUp_Msk (0x8UL)
10889 #define USB_EP_DOEPINT_OUTTknEPdis_Pos (4UL)
10890 #define USB_EP_DOEPINT_OUTTknEPdis_Msk (0x10UL)
10891 #define USB_EP_DOEPINT_StsPhseRcvd_Pos (5UL)
10892 #define USB_EP_DOEPINT_StsPhseRcvd_Msk (0x20UL)
10893 #define USB_EP_DOEPINT_Back2BackSETup_Pos (6UL)
10894 #define USB_EP_DOEPINT_Back2BackSETup_Msk (0x40UL)
10895 #define USB_EP_DOEPINT_BNAIntr_Pos (9UL)
10896 #define USB_EP_DOEPINT_BNAIntr_Msk (0x200UL)
10897 #define USB_EP_DOEPINT_PktDrpSts_Pos (11UL)
10898 #define USB_EP_DOEPINT_PktDrpSts_Msk (0x800UL)
10899 #define USB_EP_DOEPINT_BbleErrIntrpt_Pos (12UL)
10900 #define USB_EP_DOEPINT_BbleErrIntrpt_Msk (0x1000UL)
10901 #define USB_EP_DOEPINT_NAKIntrpt_Pos (13UL)
10902 #define USB_EP_DOEPINT_NAKIntrpt_Msk (0x2000UL)
10903 #define USB_EP_DOEPINT_NYETIntrpt_Pos (14UL)
10904 #define USB_EP_DOEPINT_NYETIntrpt_Msk (0x4000UL)
10906 /* ----------------------------- USB_EP_DOEPTSIZ_ISO ---------------------------- */
10907 #define USB_EP_DOEPTSIZ_ISO_XferSize_Pos (0UL)
10908 #define USB_EP_DOEPTSIZ_ISO_XferSize_Msk (0x7ffffUL)
10909 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Pos (19UL)
10910 #define USB_EP_DOEPTSIZ_ISO_PktCnt_Msk (0x1ff80000UL)
10911 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Pos (29UL)
10912 #define USB_EP_DOEPTSIZ_ISO_RxDPID_Msk (0x60000000UL)
10914 /* --------------------------- USB_EP_DOEPTSIZ_CONTROL -------------------------- */
10915 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Pos (0UL)
10916 #define USB_EP_DOEPTSIZ_CONTROL_XferSize_Msk (0x7ffffUL)
10917 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Pos (19UL)
10918 #define USB_EP_DOEPTSIZ_CONTROL_PktCnt_Msk (0x1ff80000UL)
10919 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Pos (29UL)
10920 #define USB_EP_DOEPTSIZ_CONTROL_SUPCnt_Msk (0x60000000UL)
10922 /* ------------------------------- USB_EP_DOEPDMA ------------------------------- */
10923 #define USB_EP_DOEPDMA_DMAAddr_Pos (0UL)
10924 #define USB_EP_DOEPDMA_DMAAddr_Msk (0xffffffffUL)
10926 /* ------------------------------- USB_EP_DOEPDMAB ------------------------------ */
10927 #define USB_EP_DOEPDMAB_DMABufferAddr_Pos (0UL)
10928 #define USB_EP_DOEPDMAB_DMABufferAddr_Msk (0xffffffffUL)
10931 /* ================================================================================ */
10932 /* ================ Group 'USB_CH' Position & Mask ================ */
10933 /* ================================================================================ */
10934 
10935 
10936 /* -------------------------------- USB_CH_HCCHAR ------------------------------- */
10937 #define USB_CH_HCCHAR_MPS_Pos (0UL)
10938 #define USB_CH_HCCHAR_MPS_Msk (0x7ffUL)
10939 #define USB_CH_HCCHAR_EPNum_Pos (11UL)
10940 #define USB_CH_HCCHAR_EPNum_Msk (0x7800UL)
10941 #define USB_CH_HCCHAR_EPDir_Pos (15UL)
10942 #define USB_CH_HCCHAR_EPDir_Msk (0x8000UL)
10943 #define USB_CH_HCCHAR_EPType_Pos (18UL)
10944 #define USB_CH_HCCHAR_EPType_Msk (0xc0000UL)
10945 #define USB_CH_HCCHAR_MC_EC_Pos (20UL)
10946 #define USB_CH_HCCHAR_MC_EC_Msk (0x300000UL)
10947 #define USB_CH_HCCHAR_DevAddr_Pos (22UL)
10948 #define USB_CH_HCCHAR_DevAddr_Msk (0x1fc00000UL)
10949 #define USB_CH_HCCHAR_OddFrm_Pos (29UL)
10950 #define USB_CH_HCCHAR_OddFrm_Msk (0x20000000UL)
10951 #define USB_CH_HCCHAR_ChDis_Pos (30UL)
10952 #define USB_CH_HCCHAR_ChDis_Msk (0x40000000UL)
10953 #define USB_CH_HCCHAR_ChEna_Pos (31UL)
10954 #define USB_CH_HCCHAR_ChEna_Msk (0x80000000UL)
10956 /* -------------------------------- USB_CH_HCINT -------------------------------- */
10957 #define USB_CH_HCINT_XferCompl_Pos (0UL)
10958 #define USB_CH_HCINT_XferCompl_Msk (0x1UL)
10959 #define USB_CH_HCINT_ChHltd_Pos (1UL)
10960 #define USB_CH_HCINT_ChHltd_Msk (0x2UL)
10961 #define USB_CH_HCINT_AHBErr_Pos (2UL)
10962 #define USB_CH_HCINT_AHBErr_Msk (0x4UL)
10963 #define USB_CH_HCINT_STALL_Pos (3UL)
10964 #define USB_CH_HCINT_STALL_Msk (0x8UL)
10965 #define USB_CH_HCINT_NAK_Pos (4UL)
10966 #define USB_CH_HCINT_NAK_Msk (0x10UL)
10967 #define USB_CH_HCINT_ACK_Pos (5UL)
10968 #define USB_CH_HCINT_ACK_Msk (0x20UL)
10969 #define USB_CH_HCINT_NYET_Pos (6UL)
10970 #define USB_CH_HCINT_NYET_Msk (0x40UL)
10971 #define USB_CH_HCINT_XactErr_Pos (7UL)
10972 #define USB_CH_HCINT_XactErr_Msk (0x80UL)
10973 #define USB_CH_HCINT_BblErr_Pos (8UL)
10974 #define USB_CH_HCINT_BblErr_Msk (0x100UL)
10975 #define USB_CH_HCINT_FrmOvrun_Pos (9UL)
10976 #define USB_CH_HCINT_FrmOvrun_Msk (0x200UL)
10977 #define USB_CH_HCINT_DataTglErr_Pos (10UL)
10978 #define USB_CH_HCINT_DataTglErr_Msk (0x400UL)
10979 #define USB_CH_HCINT_BNAIntr_Pos (11UL)
10980 #define USB_CH_HCINT_BNAIntr_Msk (0x800UL)
10981 #define USB_CH_HCINT_XCS_XACT_ERR_Pos (12UL)
10982 #define USB_CH_HCINT_XCS_XACT_ERR_Msk (0x1000UL)
10983 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Pos (13UL)
10984 #define USB_CH_HCINT_DESC_LST_ROLLIntr_Msk (0x2000UL)
10986 /* ------------------------------- USB_CH_HCINTMSK ------------------------------ */
10987 #define USB_CH_HCINTMSK_XferComplMsk_Pos (0UL)
10988 #define USB_CH_HCINTMSK_XferComplMsk_Msk (0x1UL)
10989 #define USB_CH_HCINTMSK_ChHltdMsk_Pos (1UL)
10990 #define USB_CH_HCINTMSK_ChHltdMsk_Msk (0x2UL)
10991 #define USB_CH_HCINTMSK_AHBErrMsk_Pos (2UL)
10992 #define USB_CH_HCINTMSK_AHBErrMsk_Msk (0x4UL)
10993 #define USB_CH_HCINTMSK_StallMsk_Pos (3UL)
10994 #define USB_CH_HCINTMSK_StallMsk_Msk (0x8UL)
10995 #define USB_CH_HCINTMSK_NakMsk_Pos (4UL)
10996 #define USB_CH_HCINTMSK_NakMsk_Msk (0x10UL)
10997 #define USB_CH_HCINTMSK_AckMsk_Pos (5UL)
10998 #define USB_CH_HCINTMSK_AckMsk_Msk (0x20UL)
10999 #define USB_CH_HCINTMSK_NyetMsk_Pos (6UL)
11000 #define USB_CH_HCINTMSK_NyetMsk_Msk (0x40UL)
11001 #define USB_CH_HCINTMSK_XactErrMsk_Pos (7UL)
11002 #define USB_CH_HCINTMSK_XactErrMsk_Msk (0x80UL)
11003 #define USB_CH_HCINTMSK_BblErrMsk_Pos (8UL)
11004 #define USB_CH_HCINTMSK_BblErrMsk_Msk (0x100UL)
11005 #define USB_CH_HCINTMSK_FrmOvrunMsk_Pos (9UL)
11006 #define USB_CH_HCINTMSK_FrmOvrunMsk_Msk (0x200UL)
11007 #define USB_CH_HCINTMSK_DataTglErrMsk_Pos (10UL)
11008 #define USB_CH_HCINTMSK_DataTglErrMsk_Msk (0x400UL)
11009 #define USB_CH_HCINTMSK_BNAIntrMsk_Pos (11UL)
11010 #define USB_CH_HCINTMSK_BNAIntrMsk_Msk (0x800UL)
11011 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Pos (13UL)
11012 #define USB_CH_HCINTMSK_DESC_LST_ROLLIntrMsk_Msk (0x2000UL)
11014 /* -------------------------- USB_CH_HCTSIZ_BUFFERMODE -------------------------- */
11015 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Pos (0UL)
11016 #define USB_CH_HCTSIZ_BUFFERMODE_XferSize_Msk (0x7ffffUL)
11017 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Pos (19UL)
11018 #define USB_CH_HCTSIZ_BUFFERMODE_PktCnt_Msk (0x1ff80000UL)
11019 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Pos (29UL)
11020 #define USB_CH_HCTSIZ_BUFFERMODE_Pid_Msk (0x60000000UL)
11022 /* -------------------------- USB_CH_HCTSIZ_SCATGATHER -------------------------- */
11023 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Pos (0UL)
11024 #define USB_CH_HCTSIZ_SCATGATHER_SCHED_INFO_Msk (0xffUL)
11025 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Pos (8UL)
11026 #define USB_CH_HCTSIZ_SCATGATHER_NTD_Msk (0xff00UL)
11027 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Pos (29UL)
11028 #define USB_CH_HCTSIZ_SCATGATHER_Pid_Msk (0x60000000UL)
11030 /* --------------------------- USB_CH_HCDMA_BUFFERMODE -------------------------- */
11031 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Pos (0UL)
11032 #define USB_CH_HCDMA_BUFFERMODE_DMAAddr_Msk (0xffffffffUL)
11034 /* --------------------------- USB_CH_HCDMA_SCATGATHER -------------------------- */
11035 #define USB_CH_HCDMA_SCATGATHER_CTD_Pos (3UL)
11036 #define USB_CH_HCDMA_SCATGATHER_CTD_Msk (0x1f8UL)
11037 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Pos (9UL)
11038 #define USB_CH_HCDMA_SCATGATHER_DMAAddr_Msk (0xfffffe00UL)
11040 /* -------------------------------- USB_CH_HCDMAB ------------------------------- */
11041 #define USB_CH_HCDMAB_Buffer_Address_Pos (0UL)
11042 #define USB_CH_HCDMAB_Buffer_Address_Msk (0xffffffffUL)
11045 /* ================================================================================ */
11046 /* ================ Group 'USIC' Position & Mask ================ */
11047 /* ================================================================================ */
11048 
11049 
11050 /* ----------------------------------- USIC_ID ---------------------------------- */
11051 #define USIC_ID_MOD_REV_Pos (0UL)
11052 #define USIC_ID_MOD_REV_Msk (0xffUL)
11053 #define USIC_ID_MOD_TYPE_Pos (8UL)
11054 #define USIC_ID_MOD_TYPE_Msk (0xff00UL)
11055 #define USIC_ID_MOD_NUMBER_Pos (16UL)
11056 #define USIC_ID_MOD_NUMBER_Msk (0xffff0000UL)
11059 /* ================================================================================ */
11060 /* ================ Group 'USIC_CH' Position & Mask ================ */
11061 /* ================================================================================ */
11062 
11063 
11064 /* -------------------------------- USIC_CH_CCFG -------------------------------- */
11065 #define USIC_CH_CCFG_SSC_Pos (0UL)
11066 #define USIC_CH_CCFG_SSC_Msk (0x1UL)
11067 #define USIC_CH_CCFG_ASC_Pos (1UL)
11068 #define USIC_CH_CCFG_ASC_Msk (0x2UL)
11069 #define USIC_CH_CCFG_IIC_Pos (2UL)
11070 #define USIC_CH_CCFG_IIC_Msk (0x4UL)
11071 #define USIC_CH_CCFG_IIS_Pos (3UL)
11072 #define USIC_CH_CCFG_IIS_Msk (0x8UL)
11073 #define USIC_CH_CCFG_RB_Pos (6UL)
11074 #define USIC_CH_CCFG_RB_Msk (0x40UL)
11075 #define USIC_CH_CCFG_TB_Pos (7UL)
11076 #define USIC_CH_CCFG_TB_Msk (0x80UL)
11078 /* -------------------------------- USIC_CH_KSCFG ------------------------------- */
11079 #define USIC_CH_KSCFG_MODEN_Pos (0UL)
11080 #define USIC_CH_KSCFG_MODEN_Msk (0x1UL)
11081 #define USIC_CH_KSCFG_BPMODEN_Pos (1UL)
11082 #define USIC_CH_KSCFG_BPMODEN_Msk (0x2UL)
11083 #define USIC_CH_KSCFG_NOMCFG_Pos (4UL)
11084 #define USIC_CH_KSCFG_NOMCFG_Msk (0x30UL)
11085 #define USIC_CH_KSCFG_BPNOM_Pos (7UL)
11086 #define USIC_CH_KSCFG_BPNOM_Msk (0x80UL)
11087 #define USIC_CH_KSCFG_SUMCFG_Pos (8UL)
11088 #define USIC_CH_KSCFG_SUMCFG_Msk (0x300UL)
11089 #define USIC_CH_KSCFG_BPSUM_Pos (11UL)
11090 #define USIC_CH_KSCFG_BPSUM_Msk (0x800UL)
11092 /* --------------------------------- USIC_CH_FDR -------------------------------- */
11093 #define USIC_CH_FDR_STEP_Pos (0UL)
11094 #define USIC_CH_FDR_STEP_Msk (0x3ffUL)
11095 #define USIC_CH_FDR_DM_Pos (14UL)
11096 #define USIC_CH_FDR_DM_Msk (0xc000UL)
11097 #define USIC_CH_FDR_RESULT_Pos (16UL)
11098 #define USIC_CH_FDR_RESULT_Msk (0x3ff0000UL)
11100 /* --------------------------------- USIC_CH_BRG -------------------------------- */
11101 #define USIC_CH_BRG_CLKSEL_Pos (0UL)
11102 #define USIC_CH_BRG_CLKSEL_Msk (0x3UL)
11103 #define USIC_CH_BRG_TMEN_Pos (3UL)
11104 #define USIC_CH_BRG_TMEN_Msk (0x8UL)
11105 #define USIC_CH_BRG_PPPEN_Pos (4UL)
11106 #define USIC_CH_BRG_PPPEN_Msk (0x10UL)
11107 #define USIC_CH_BRG_CTQSEL_Pos (6UL)
11108 #define USIC_CH_BRG_CTQSEL_Msk (0xc0UL)
11109 #define USIC_CH_BRG_PCTQ_Pos (8UL)
11110 #define USIC_CH_BRG_PCTQ_Msk (0x300UL)
11111 #define USIC_CH_BRG_DCTQ_Pos (10UL)
11112 #define USIC_CH_BRG_DCTQ_Msk (0x7c00UL)
11113 #define USIC_CH_BRG_PDIV_Pos (16UL)
11114 #define USIC_CH_BRG_PDIV_Msk (0x3ff0000UL)
11115 #define USIC_CH_BRG_SCLKOSEL_Pos (28UL)
11116 #define USIC_CH_BRG_SCLKOSEL_Msk (0x10000000UL)
11117 #define USIC_CH_BRG_MCLKCFG_Pos (29UL)
11118 #define USIC_CH_BRG_MCLKCFG_Msk (0x20000000UL)
11119 #define USIC_CH_BRG_SCLKCFG_Pos (30UL)
11120 #define USIC_CH_BRG_SCLKCFG_Msk (0xc0000000UL)
11122 /* -------------------------------- USIC_CH_INPR -------------------------------- */
11123 #define USIC_CH_INPR_TSINP_Pos (0UL)
11124 #define USIC_CH_INPR_TSINP_Msk (0x7UL)
11125 #define USIC_CH_INPR_TBINP_Pos (4UL)
11126 #define USIC_CH_INPR_TBINP_Msk (0x70UL)
11127 #define USIC_CH_INPR_RINP_Pos (8UL)
11128 #define USIC_CH_INPR_RINP_Msk (0x700UL)
11129 #define USIC_CH_INPR_AINP_Pos (12UL)
11130 #define USIC_CH_INPR_AINP_Msk (0x7000UL)
11131 #define USIC_CH_INPR_PINP_Pos (16UL)
11132 #define USIC_CH_INPR_PINP_Msk (0x70000UL)
11134 /* -------------------------------- USIC_CH_DX0CR ------------------------------- */
11135 #define USIC_CH_DX0CR_DSEL_Pos (0UL)
11136 #define USIC_CH_DX0CR_DSEL_Msk (0x7UL)
11137 #define USIC_CH_DX0CR_INSW_Pos (4UL)
11138 #define USIC_CH_DX0CR_INSW_Msk (0x10UL)
11139 #define USIC_CH_DX0CR_DFEN_Pos (5UL)
11140 #define USIC_CH_DX0CR_DFEN_Msk (0x20UL)
11141 #define USIC_CH_DX0CR_DSEN_Pos (6UL)
11142 #define USIC_CH_DX0CR_DSEN_Msk (0x40UL)
11143 #define USIC_CH_DX0CR_DPOL_Pos (8UL)
11144 #define USIC_CH_DX0CR_DPOL_Msk (0x100UL)
11145 #define USIC_CH_DX0CR_SFSEL_Pos (9UL)
11146 #define USIC_CH_DX0CR_SFSEL_Msk (0x200UL)
11147 #define USIC_CH_DX0CR_CM_Pos (10UL)
11148 #define USIC_CH_DX0CR_CM_Msk (0xc00UL)
11149 #define USIC_CH_DX0CR_DXS_Pos (15UL)
11150 #define USIC_CH_DX0CR_DXS_Msk (0x8000UL)
11152 /* -------------------------------- USIC_CH_DX1CR ------------------------------- */
11153 #define USIC_CH_DX1CR_DSEL_Pos (0UL)
11154 #define USIC_CH_DX1CR_DSEL_Msk (0x7UL)
11155 #define USIC_CH_DX1CR_DCEN_Pos (3UL)
11156 #define USIC_CH_DX1CR_DCEN_Msk (0x8UL)
11157 #define USIC_CH_DX1CR_INSW_Pos (4UL)
11158 #define USIC_CH_DX1CR_INSW_Msk (0x10UL)
11159 #define USIC_CH_DX1CR_DFEN_Pos (5UL)
11160 #define USIC_CH_DX1CR_DFEN_Msk (0x20UL)
11161 #define USIC_CH_DX1CR_DSEN_Pos (6UL)
11162 #define USIC_CH_DX1CR_DSEN_Msk (0x40UL)
11163 #define USIC_CH_DX1CR_DPOL_Pos (8UL)
11164 #define USIC_CH_DX1CR_DPOL_Msk (0x100UL)
11165 #define USIC_CH_DX1CR_SFSEL_Pos (9UL)
11166 #define USIC_CH_DX1CR_SFSEL_Msk (0x200UL)
11167 #define USIC_CH_DX1CR_CM_Pos (10UL)
11168 #define USIC_CH_DX1CR_CM_Msk (0xc00UL)
11169 #define USIC_CH_DX1CR_DXS_Pos (15UL)
11170 #define USIC_CH_DX1CR_DXS_Msk (0x8000UL)
11172 /* -------------------------------- USIC_CH_DX2CR ------------------------------- */
11173 #define USIC_CH_DX2CR_DSEL_Pos (0UL)
11174 #define USIC_CH_DX2CR_DSEL_Msk (0x7UL)
11175 #define USIC_CH_DX2CR_INSW_Pos (4UL)
11176 #define USIC_CH_DX2CR_INSW_Msk (0x10UL)
11177 #define USIC_CH_DX2CR_DFEN_Pos (5UL)
11178 #define USIC_CH_DX2CR_DFEN_Msk (0x20UL)
11179 #define USIC_CH_DX2CR_DSEN_Pos (6UL)
11180 #define USIC_CH_DX2CR_DSEN_Msk (0x40UL)
11181 #define USIC_CH_DX2CR_DPOL_Pos (8UL)
11182 #define USIC_CH_DX2CR_DPOL_Msk (0x100UL)
11183 #define USIC_CH_DX2CR_SFSEL_Pos (9UL)
11184 #define USIC_CH_DX2CR_SFSEL_Msk (0x200UL)
11185 #define USIC_CH_DX2CR_CM_Pos (10UL)
11186 #define USIC_CH_DX2CR_CM_Msk (0xc00UL)
11187 #define USIC_CH_DX2CR_DXS_Pos (15UL)
11188 #define USIC_CH_DX2CR_DXS_Msk (0x8000UL)
11190 /* -------------------------------- USIC_CH_DX3CR ------------------------------- */
11191 #define USIC_CH_DX3CR_DSEL_Pos (0UL)
11192 #define USIC_CH_DX3CR_DSEL_Msk (0x7UL)
11193 #define USIC_CH_DX3CR_INSW_Pos (4UL)
11194 #define USIC_CH_DX3CR_INSW_Msk (0x10UL)
11195 #define USIC_CH_DX3CR_DFEN_Pos (5UL)
11196 #define USIC_CH_DX3CR_DFEN_Msk (0x20UL)
11197 #define USIC_CH_DX3CR_DSEN_Pos (6UL)
11198 #define USIC_CH_DX3CR_DSEN_Msk (0x40UL)
11199 #define USIC_CH_DX3CR_DPOL_Pos (8UL)
11200 #define USIC_CH_DX3CR_DPOL_Msk (0x100UL)
11201 #define USIC_CH_DX3CR_SFSEL_Pos (9UL)
11202 #define USIC_CH_DX3CR_SFSEL_Msk (0x200UL)
11203 #define USIC_CH_DX3CR_CM_Pos (10UL)
11204 #define USIC_CH_DX3CR_CM_Msk (0xc00UL)
11205 #define USIC_CH_DX3CR_DXS_Pos (15UL)
11206 #define USIC_CH_DX3CR_DXS_Msk (0x8000UL)
11208 /* -------------------------------- USIC_CH_DX4CR ------------------------------- */
11209 #define USIC_CH_DX4CR_DSEL_Pos (0UL)
11210 #define USIC_CH_DX4CR_DSEL_Msk (0x7UL)
11211 #define USIC_CH_DX4CR_INSW_Pos (4UL)
11212 #define USIC_CH_DX4CR_INSW_Msk (0x10UL)
11213 #define USIC_CH_DX4CR_DFEN_Pos (5UL)
11214 #define USIC_CH_DX4CR_DFEN_Msk (0x20UL)
11215 #define USIC_CH_DX4CR_DSEN_Pos (6UL)
11216 #define USIC_CH_DX4CR_DSEN_Msk (0x40UL)
11217 #define USIC_CH_DX4CR_DPOL_Pos (8UL)
11218 #define USIC_CH_DX4CR_DPOL_Msk (0x100UL)
11219 #define USIC_CH_DX4CR_SFSEL_Pos (9UL)
11220 #define USIC_CH_DX4CR_SFSEL_Msk (0x200UL)
11221 #define USIC_CH_DX4CR_CM_Pos (10UL)
11222 #define USIC_CH_DX4CR_CM_Msk (0xc00UL)
11223 #define USIC_CH_DX4CR_DXS_Pos (15UL)
11224 #define USIC_CH_DX4CR_DXS_Msk (0x8000UL)
11226 /* -------------------------------- USIC_CH_DX5CR ------------------------------- */
11227 #define USIC_CH_DX5CR_DSEL_Pos (0UL)
11228 #define USIC_CH_DX5CR_DSEL_Msk (0x7UL)
11229 #define USIC_CH_DX5CR_INSW_Pos (4UL)
11230 #define USIC_CH_DX5CR_INSW_Msk (0x10UL)
11231 #define USIC_CH_DX5CR_DFEN_Pos (5UL)
11232 #define USIC_CH_DX5CR_DFEN_Msk (0x20UL)
11233 #define USIC_CH_DX5CR_DSEN_Pos (6UL)
11234 #define USIC_CH_DX5CR_DSEN_Msk (0x40UL)
11235 #define USIC_CH_DX5CR_DPOL_Pos (8UL)
11236 #define USIC_CH_DX5CR_DPOL_Msk (0x100UL)
11237 #define USIC_CH_DX5CR_SFSEL_Pos (9UL)
11238 #define USIC_CH_DX5CR_SFSEL_Msk (0x200UL)
11239 #define USIC_CH_DX5CR_CM_Pos (10UL)
11240 #define USIC_CH_DX5CR_CM_Msk (0xc00UL)
11241 #define USIC_CH_DX5CR_DXS_Pos (15UL)
11242 #define USIC_CH_DX5CR_DXS_Msk (0x8000UL)
11244 /* -------------------------------- USIC_CH_SCTR -------------------------------- */
11245 #define USIC_CH_SCTR_SDIR_Pos (0UL)
11246 #define USIC_CH_SCTR_SDIR_Msk (0x1UL)
11247 #define USIC_CH_SCTR_PDL_Pos (1UL)
11248 #define USIC_CH_SCTR_PDL_Msk (0x2UL)
11249 #define USIC_CH_SCTR_DSM_Pos (2UL)
11250 #define USIC_CH_SCTR_DSM_Msk (0xcUL)
11251 #define USIC_CH_SCTR_HPCDIR_Pos (4UL)
11252 #define USIC_CH_SCTR_HPCDIR_Msk (0x10UL)
11253 #define USIC_CH_SCTR_DOCFG_Pos (6UL)
11254 #define USIC_CH_SCTR_DOCFG_Msk (0xc0UL)
11255 #define USIC_CH_SCTR_TRM_Pos (8UL)
11256 #define USIC_CH_SCTR_TRM_Msk (0x300UL)
11257 #define USIC_CH_SCTR_FLE_Pos (16UL)
11258 #define USIC_CH_SCTR_FLE_Msk (0x3f0000UL)
11259 #define USIC_CH_SCTR_WLE_Pos (24UL)
11260 #define USIC_CH_SCTR_WLE_Msk (0xf000000UL)
11262 /* -------------------------------- USIC_CH_TCSR -------------------------------- */
11263 #define USIC_CH_TCSR_WLEMD_Pos (0UL)
11264 #define USIC_CH_TCSR_WLEMD_Msk (0x1UL)
11265 #define USIC_CH_TCSR_SELMD_Pos (1UL)
11266 #define USIC_CH_TCSR_SELMD_Msk (0x2UL)
11267 #define USIC_CH_TCSR_FLEMD_Pos (2UL)
11268 #define USIC_CH_TCSR_FLEMD_Msk (0x4UL)
11269 #define USIC_CH_TCSR_WAMD_Pos (3UL)
11270 #define USIC_CH_TCSR_WAMD_Msk (0x8UL)
11271 #define USIC_CH_TCSR_HPCMD_Pos (4UL)
11272 #define USIC_CH_TCSR_HPCMD_Msk (0x10UL)
11273 #define USIC_CH_TCSR_SOF_Pos (5UL)
11274 #define USIC_CH_TCSR_SOF_Msk (0x20UL)
11275 #define USIC_CH_TCSR_EOF_Pos (6UL)
11276 #define USIC_CH_TCSR_EOF_Msk (0x40UL)
11277 #define USIC_CH_TCSR_TDV_Pos (7UL)
11278 #define USIC_CH_TCSR_TDV_Msk (0x80UL)
11279 #define USIC_CH_TCSR_TDSSM_Pos (8UL)
11280 #define USIC_CH_TCSR_TDSSM_Msk (0x100UL)
11281 #define USIC_CH_TCSR_TDEN_Pos (10UL)
11282 #define USIC_CH_TCSR_TDEN_Msk (0xc00UL)
11283 #define USIC_CH_TCSR_TDVTR_Pos (12UL)
11284 #define USIC_CH_TCSR_TDVTR_Msk (0x1000UL)
11285 #define USIC_CH_TCSR_WA_Pos (13UL)
11286 #define USIC_CH_TCSR_WA_Msk (0x2000UL)
11287 #define USIC_CH_TCSR_TSOF_Pos (24UL)
11288 #define USIC_CH_TCSR_TSOF_Msk (0x1000000UL)
11289 #define USIC_CH_TCSR_TV_Pos (26UL)
11290 #define USIC_CH_TCSR_TV_Msk (0x4000000UL)
11291 #define USIC_CH_TCSR_TVC_Pos (27UL)
11292 #define USIC_CH_TCSR_TVC_Msk (0x8000000UL)
11293 #define USIC_CH_TCSR_TE_Pos (28UL)
11294 #define USIC_CH_TCSR_TE_Msk (0x10000000UL)
11296 /* --------------------------------- USIC_CH_PCR -------------------------------- */
11297 #define USIC_CH_PCR_CTR0_Pos (0UL)
11298 #define USIC_CH_PCR_CTR0_Msk (0x1UL)
11299 #define USIC_CH_PCR_CTR1_Pos (1UL)
11300 #define USIC_CH_PCR_CTR1_Msk (0x2UL)
11301 #define USIC_CH_PCR_CTR2_Pos (2UL)
11302 #define USIC_CH_PCR_CTR2_Msk (0x4UL)
11303 #define USIC_CH_PCR_CTR3_Pos (3UL)
11304 #define USIC_CH_PCR_CTR3_Msk (0x8UL)
11305 #define USIC_CH_PCR_CTR4_Pos (4UL)
11306 #define USIC_CH_PCR_CTR4_Msk (0x10UL)
11307 #define USIC_CH_PCR_CTR5_Pos (5UL)
11308 #define USIC_CH_PCR_CTR5_Msk (0x20UL)
11309 #define USIC_CH_PCR_CTR6_Pos (6UL)
11310 #define USIC_CH_PCR_CTR6_Msk (0x40UL)
11311 #define USIC_CH_PCR_CTR7_Pos (7UL)
11312 #define USIC_CH_PCR_CTR7_Msk (0x80UL)
11313 #define USIC_CH_PCR_CTR8_Pos (8UL)
11314 #define USIC_CH_PCR_CTR8_Msk (0x100UL)
11315 #define USIC_CH_PCR_CTR9_Pos (9UL)
11316 #define USIC_CH_PCR_CTR9_Msk (0x200UL)
11317 #define USIC_CH_PCR_CTR10_Pos (10UL)
11318 #define USIC_CH_PCR_CTR10_Msk (0x400UL)
11319 #define USIC_CH_PCR_CTR11_Pos (11UL)
11320 #define USIC_CH_PCR_CTR11_Msk (0x800UL)
11321 #define USIC_CH_PCR_CTR12_Pos (12UL)
11322 #define USIC_CH_PCR_CTR12_Msk (0x1000UL)
11323 #define USIC_CH_PCR_CTR13_Pos (13UL)
11324 #define USIC_CH_PCR_CTR13_Msk (0x2000UL)
11325 #define USIC_CH_PCR_CTR14_Pos (14UL)
11326 #define USIC_CH_PCR_CTR14_Msk (0x4000UL)
11327 #define USIC_CH_PCR_CTR15_Pos (15UL)
11328 #define USIC_CH_PCR_CTR15_Msk (0x8000UL)
11329 #define USIC_CH_PCR_CTR16_Pos (16UL)
11330 #define USIC_CH_PCR_CTR16_Msk (0x10000UL)
11331 #define USIC_CH_PCR_CTR17_Pos (17UL)
11332 #define USIC_CH_PCR_CTR17_Msk (0x20000UL)
11333 #define USIC_CH_PCR_CTR18_Pos (18UL)
11334 #define USIC_CH_PCR_CTR18_Msk (0x40000UL)
11335 #define USIC_CH_PCR_CTR19_Pos (19UL)
11336 #define USIC_CH_PCR_CTR19_Msk (0x80000UL)
11337 #define USIC_CH_PCR_CTR20_Pos (20UL)
11338 #define USIC_CH_PCR_CTR20_Msk (0x100000UL)
11339 #define USIC_CH_PCR_CTR21_Pos (21UL)
11340 #define USIC_CH_PCR_CTR21_Msk (0x200000UL)
11341 #define USIC_CH_PCR_CTR22_Pos (22UL)
11342 #define USIC_CH_PCR_CTR22_Msk (0x400000UL)
11343 #define USIC_CH_PCR_CTR23_Pos (23UL)
11344 #define USIC_CH_PCR_CTR23_Msk (0x800000UL)
11345 #define USIC_CH_PCR_CTR24_Pos (24UL)
11346 #define USIC_CH_PCR_CTR24_Msk (0x1000000UL)
11347 #define USIC_CH_PCR_CTR25_Pos (25UL)
11348 #define USIC_CH_PCR_CTR25_Msk (0x2000000UL)
11349 #define USIC_CH_PCR_CTR26_Pos (26UL)
11350 #define USIC_CH_PCR_CTR26_Msk (0x4000000UL)
11351 #define USIC_CH_PCR_CTR27_Pos (27UL)
11352 #define USIC_CH_PCR_CTR27_Msk (0x8000000UL)
11353 #define USIC_CH_PCR_CTR28_Pos (28UL)
11354 #define USIC_CH_PCR_CTR28_Msk (0x10000000UL)
11355 #define USIC_CH_PCR_CTR29_Pos (29UL)
11356 #define USIC_CH_PCR_CTR29_Msk (0x20000000UL)
11357 #define USIC_CH_PCR_CTR30_Pos (30UL)
11358 #define USIC_CH_PCR_CTR30_Msk (0x40000000UL)
11359 #define USIC_CH_PCR_CTR31_Pos (31UL)
11360 #define USIC_CH_PCR_CTR31_Msk (0x80000000UL)
11362 /* ----------------------------- USIC_CH_PCR_ASCMode ---------------------------- */
11363 #define USIC_CH_PCR_ASCMode_SMD_Pos (0UL)
11364 #define USIC_CH_PCR_ASCMode_SMD_Msk (0x1UL)
11365 #define USIC_CH_PCR_ASCMode_STPB_Pos (1UL)
11366 #define USIC_CH_PCR_ASCMode_STPB_Msk (0x2UL)
11367 #define USIC_CH_PCR_ASCMode_IDM_Pos (2UL)
11368 #define USIC_CH_PCR_ASCMode_IDM_Msk (0x4UL)
11369 #define USIC_CH_PCR_ASCMode_SBIEN_Pos (3UL)
11370 #define USIC_CH_PCR_ASCMode_SBIEN_Msk (0x8UL)
11371 #define USIC_CH_PCR_ASCMode_CDEN_Pos (4UL)
11372 #define USIC_CH_PCR_ASCMode_CDEN_Msk (0x10UL)
11373 #define USIC_CH_PCR_ASCMode_RNIEN_Pos (5UL)
11374 #define USIC_CH_PCR_ASCMode_RNIEN_Msk (0x20UL)
11375 #define USIC_CH_PCR_ASCMode_FEIEN_Pos (6UL)
11376 #define USIC_CH_PCR_ASCMode_FEIEN_Msk (0x40UL)
11377 #define USIC_CH_PCR_ASCMode_FFIEN_Pos (7UL)
11378 #define USIC_CH_PCR_ASCMode_FFIEN_Msk (0x80UL)
11379 #define USIC_CH_PCR_ASCMode_SP_Pos (8UL)
11380 #define USIC_CH_PCR_ASCMode_SP_Msk (0x1f00UL)
11381 #define USIC_CH_PCR_ASCMode_PL_Pos (13UL)
11382 #define USIC_CH_PCR_ASCMode_PL_Msk (0xe000UL)
11383 #define USIC_CH_PCR_ASCMode_RSTEN_Pos (16UL)
11384 #define USIC_CH_PCR_ASCMode_RSTEN_Msk (0x10000UL)
11385 #define USIC_CH_PCR_ASCMode_TSTEN_Pos (17UL)
11386 #define USIC_CH_PCR_ASCMode_TSTEN_Msk (0x20000UL)
11387 #define USIC_CH_PCR_ASCMode_MCLK_Pos (31UL)
11388 #define USIC_CH_PCR_ASCMode_MCLK_Msk (0x80000000UL)
11390 /* ----------------------------- USIC_CH_PCR_SSCMode ---------------------------- */
11391 #define USIC_CH_PCR_SSCMode_MSLSEN_Pos (0UL)
11392 #define USIC_CH_PCR_SSCMode_MSLSEN_Msk (0x1UL)
11393 #define USIC_CH_PCR_SSCMode_SELCTR_Pos (1UL)
11394 #define USIC_CH_PCR_SSCMode_SELCTR_Msk (0x2UL)
11395 #define USIC_CH_PCR_SSCMode_SELINV_Pos (2UL)
11396 #define USIC_CH_PCR_SSCMode_SELINV_Msk (0x4UL)
11397 #define USIC_CH_PCR_SSCMode_FEM_Pos (3UL)
11398 #define USIC_CH_PCR_SSCMode_FEM_Msk (0x8UL)
11399 #define USIC_CH_PCR_SSCMode_CTQSEL1_Pos (4UL)
11400 #define USIC_CH_PCR_SSCMode_CTQSEL1_Msk (0x30UL)
11401 #define USIC_CH_PCR_SSCMode_PCTQ1_Pos (6UL)
11402 #define USIC_CH_PCR_SSCMode_PCTQ1_Msk (0xc0UL)
11403 #define USIC_CH_PCR_SSCMode_DCTQ1_Pos (8UL)
11404 #define USIC_CH_PCR_SSCMode_DCTQ1_Msk (0x1f00UL)
11405 #define USIC_CH_PCR_SSCMode_PARIEN_Pos (13UL)
11406 #define USIC_CH_PCR_SSCMode_PARIEN_Msk (0x2000UL)
11407 #define USIC_CH_PCR_SSCMode_MSLSIEN_Pos (14UL)
11408 #define USIC_CH_PCR_SSCMode_MSLSIEN_Msk (0x4000UL)
11409 #define USIC_CH_PCR_SSCMode_DX2TIEN_Pos (15UL)
11410 #define USIC_CH_PCR_SSCMode_DX2TIEN_Msk (0x8000UL)
11411 #define USIC_CH_PCR_SSCMode_SELO_Pos (16UL)
11412 #define USIC_CH_PCR_SSCMode_SELO_Msk (0xff0000UL)
11413 #define USIC_CH_PCR_SSCMode_TIWEN_Pos (24UL)
11414 #define USIC_CH_PCR_SSCMode_TIWEN_Msk (0x1000000UL)
11415 #define USIC_CH_PCR_SSCMode_SLPHSEL_Pos (25UL)
11416 #define USIC_CH_PCR_SSCMode_SLPHSEL_Msk (0x2000000UL)
11417 #define USIC_CH_PCR_SSCMode_MCLK_Pos (31UL)
11418 #define USIC_CH_PCR_SSCMode_MCLK_Msk (0x80000000UL)
11420 /* ----------------------------- USIC_CH_PCR_IICMode ---------------------------- */
11421 #define USIC_CH_PCR_IICMode_SLAD_Pos (0UL)
11422 #define USIC_CH_PCR_IICMode_SLAD_Msk (0xffffUL)
11423 #define USIC_CH_PCR_IICMode_ACK00_Pos (16UL)
11424 #define USIC_CH_PCR_IICMode_ACK00_Msk (0x10000UL)
11425 #define USIC_CH_PCR_IICMode_STIM_Pos (17UL)
11426 #define USIC_CH_PCR_IICMode_STIM_Msk (0x20000UL)
11427 #define USIC_CH_PCR_IICMode_SCRIEN_Pos (18UL)
11428 #define USIC_CH_PCR_IICMode_SCRIEN_Msk (0x40000UL)
11429 #define USIC_CH_PCR_IICMode_RSCRIEN_Pos (19UL)
11430 #define USIC_CH_PCR_IICMode_RSCRIEN_Msk (0x80000UL)
11431 #define USIC_CH_PCR_IICMode_PCRIEN_Pos (20UL)
11432 #define USIC_CH_PCR_IICMode_PCRIEN_Msk (0x100000UL)
11433 #define USIC_CH_PCR_IICMode_NACKIEN_Pos (21UL)
11434 #define USIC_CH_PCR_IICMode_NACKIEN_Msk (0x200000UL)
11435 #define USIC_CH_PCR_IICMode_ARLIEN_Pos (22UL)
11436 #define USIC_CH_PCR_IICMode_ARLIEN_Msk (0x400000UL)
11437 #define USIC_CH_PCR_IICMode_SRRIEN_Pos (23UL)
11438 #define USIC_CH_PCR_IICMode_SRRIEN_Msk (0x800000UL)
11439 #define USIC_CH_PCR_IICMode_ERRIEN_Pos (24UL)
11440 #define USIC_CH_PCR_IICMode_ERRIEN_Msk (0x1000000UL)
11441 #define USIC_CH_PCR_IICMode_SACKDIS_Pos (25UL)
11442 #define USIC_CH_PCR_IICMode_SACKDIS_Msk (0x2000000UL)
11443 #define USIC_CH_PCR_IICMode_HDEL_Pos (26UL)
11444 #define USIC_CH_PCR_IICMode_HDEL_Msk (0x3c000000UL)
11445 #define USIC_CH_PCR_IICMode_ACKIEN_Pos (30UL)
11446 #define USIC_CH_PCR_IICMode_ACKIEN_Msk (0x40000000UL)
11447 #define USIC_CH_PCR_IICMode_MCLK_Pos (31UL)
11448 #define USIC_CH_PCR_IICMode_MCLK_Msk (0x80000000UL)
11450 /* ----------------------------- USIC_CH_PCR_IISMode ---------------------------- */
11451 #define USIC_CH_PCR_IISMode_WAGEN_Pos (0UL)
11452 #define USIC_CH_PCR_IISMode_WAGEN_Msk (0x1UL)
11453 #define USIC_CH_PCR_IISMode_DTEN_Pos (1UL)
11454 #define USIC_CH_PCR_IISMode_DTEN_Msk (0x2UL)
11455 #define USIC_CH_PCR_IISMode_SELINV_Pos (2UL)
11456 #define USIC_CH_PCR_IISMode_SELINV_Msk (0x4UL)
11457 #define USIC_CH_PCR_IISMode_WAFEIEN_Pos (4UL)
11458 #define USIC_CH_PCR_IISMode_WAFEIEN_Msk (0x10UL)
11459 #define USIC_CH_PCR_IISMode_WAREIEN_Pos (5UL)
11460 #define USIC_CH_PCR_IISMode_WAREIEN_Msk (0x20UL)
11461 #define USIC_CH_PCR_IISMode_ENDIEN_Pos (6UL)
11462 #define USIC_CH_PCR_IISMode_ENDIEN_Msk (0x40UL)
11463 #define USIC_CH_PCR_IISMode_DX2TIEN_Pos (15UL)
11464 #define USIC_CH_PCR_IISMode_DX2TIEN_Msk (0x8000UL)
11465 #define USIC_CH_PCR_IISMode_TDEL_Pos (16UL)
11466 #define USIC_CH_PCR_IISMode_TDEL_Msk (0x3f0000UL)
11467 #define USIC_CH_PCR_IISMode_MCLK_Pos (31UL)
11468 #define USIC_CH_PCR_IISMode_MCLK_Msk (0x80000000UL)
11470 /* --------------------------------- USIC_CH_CCR -------------------------------- */
11471 #define USIC_CH_CCR_MODE_Pos (0UL)
11472 #define USIC_CH_CCR_MODE_Msk (0xfUL)
11473 #define USIC_CH_CCR_HPCEN_Pos (6UL)
11474 #define USIC_CH_CCR_HPCEN_Msk (0xc0UL)
11475 #define USIC_CH_CCR_PM_Pos (8UL)
11476 #define USIC_CH_CCR_PM_Msk (0x300UL)
11477 #define USIC_CH_CCR_RSIEN_Pos (10UL)
11478 #define USIC_CH_CCR_RSIEN_Msk (0x400UL)
11479 #define USIC_CH_CCR_DLIEN_Pos (11UL)
11480 #define USIC_CH_CCR_DLIEN_Msk (0x800UL)
11481 #define USIC_CH_CCR_TSIEN_Pos (12UL)
11482 #define USIC_CH_CCR_TSIEN_Msk (0x1000UL)
11483 #define USIC_CH_CCR_TBIEN_Pos (13UL)
11484 #define USIC_CH_CCR_TBIEN_Msk (0x2000UL)
11485 #define USIC_CH_CCR_RIEN_Pos (14UL)
11486 #define USIC_CH_CCR_RIEN_Msk (0x4000UL)
11487 #define USIC_CH_CCR_AIEN_Pos (15UL)
11488 #define USIC_CH_CCR_AIEN_Msk (0x8000UL)
11489 #define USIC_CH_CCR_BRGIEN_Pos (16UL)
11490 #define USIC_CH_CCR_BRGIEN_Msk (0x10000UL)
11492 /* -------------------------------- USIC_CH_CMTR -------------------------------- */
11493 #define USIC_CH_CMTR_CTV_Pos (0UL)
11494 #define USIC_CH_CMTR_CTV_Msk (0x3ffUL)
11496 /* --------------------------------- USIC_CH_PSR -------------------------------- */
11497 #define USIC_CH_PSR_ST0_Pos (0UL)
11498 #define USIC_CH_PSR_ST0_Msk (0x1UL)
11499 #define USIC_CH_PSR_ST1_Pos (1UL)
11500 #define USIC_CH_PSR_ST1_Msk (0x2UL)
11501 #define USIC_CH_PSR_ST2_Pos (2UL)
11502 #define USIC_CH_PSR_ST2_Msk (0x4UL)
11503 #define USIC_CH_PSR_ST3_Pos (3UL)
11504 #define USIC_CH_PSR_ST3_Msk (0x8UL)
11505 #define USIC_CH_PSR_ST4_Pos (4UL)
11506 #define USIC_CH_PSR_ST4_Msk (0x10UL)
11507 #define USIC_CH_PSR_ST5_Pos (5UL)
11508 #define USIC_CH_PSR_ST5_Msk (0x20UL)
11509 #define USIC_CH_PSR_ST6_Pos (6UL)
11510 #define USIC_CH_PSR_ST6_Msk (0x40UL)
11511 #define USIC_CH_PSR_ST7_Pos (7UL)
11512 #define USIC_CH_PSR_ST7_Msk (0x80UL)
11513 #define USIC_CH_PSR_ST8_Pos (8UL)
11514 #define USIC_CH_PSR_ST8_Msk (0x100UL)
11515 #define USIC_CH_PSR_ST9_Pos (9UL)
11516 #define USIC_CH_PSR_ST9_Msk (0x200UL)
11517 #define USIC_CH_PSR_RSIF_Pos (10UL)
11518 #define USIC_CH_PSR_RSIF_Msk (0x400UL)
11519 #define USIC_CH_PSR_DLIF_Pos (11UL)
11520 #define USIC_CH_PSR_DLIF_Msk (0x800UL)
11521 #define USIC_CH_PSR_TSIF_Pos (12UL)
11522 #define USIC_CH_PSR_TSIF_Msk (0x1000UL)
11523 #define USIC_CH_PSR_TBIF_Pos (13UL)
11524 #define USIC_CH_PSR_TBIF_Msk (0x2000UL)
11525 #define USIC_CH_PSR_RIF_Pos (14UL)
11526 #define USIC_CH_PSR_RIF_Msk (0x4000UL)
11527 #define USIC_CH_PSR_AIF_Pos (15UL)
11528 #define USIC_CH_PSR_AIF_Msk (0x8000UL)
11529 #define USIC_CH_PSR_BRGIF_Pos (16UL)
11530 #define USIC_CH_PSR_BRGIF_Msk (0x10000UL)
11532 /* ----------------------------- USIC_CH_PSR_ASCMode ---------------------------- */
11533 #define USIC_CH_PSR_ASCMode_TXIDLE_Pos (0UL)
11534 #define USIC_CH_PSR_ASCMode_TXIDLE_Msk (0x1UL)
11535 #define USIC_CH_PSR_ASCMode_RXIDLE_Pos (1UL)
11536 #define USIC_CH_PSR_ASCMode_RXIDLE_Msk (0x2UL)
11537 #define USIC_CH_PSR_ASCMode_SBD_Pos (2UL)
11538 #define USIC_CH_PSR_ASCMode_SBD_Msk (0x4UL)
11539 #define USIC_CH_PSR_ASCMode_COL_Pos (3UL)
11540 #define USIC_CH_PSR_ASCMode_COL_Msk (0x8UL)
11541 #define USIC_CH_PSR_ASCMode_RNS_Pos (4UL)
11542 #define USIC_CH_PSR_ASCMode_RNS_Msk (0x10UL)
11543 #define USIC_CH_PSR_ASCMode_FER0_Pos (5UL)
11544 #define USIC_CH_PSR_ASCMode_FER0_Msk (0x20UL)
11545 #define USIC_CH_PSR_ASCMode_FER1_Pos (6UL)
11546 #define USIC_CH_PSR_ASCMode_FER1_Msk (0x40UL)
11547 #define USIC_CH_PSR_ASCMode_RFF_Pos (7UL)
11548 #define USIC_CH_PSR_ASCMode_RFF_Msk (0x80UL)
11549 #define USIC_CH_PSR_ASCMode_TFF_Pos (8UL)
11550 #define USIC_CH_PSR_ASCMode_TFF_Msk (0x100UL)
11551 #define USIC_CH_PSR_ASCMode_BUSY_Pos (9UL)
11552 #define USIC_CH_PSR_ASCMode_BUSY_Msk (0x200UL)
11553 #define USIC_CH_PSR_ASCMode_RSIF_Pos (10UL)
11554 #define USIC_CH_PSR_ASCMode_RSIF_Msk (0x400UL)
11555 #define USIC_CH_PSR_ASCMode_DLIF_Pos (11UL)
11556 #define USIC_CH_PSR_ASCMode_DLIF_Msk (0x800UL)
11557 #define USIC_CH_PSR_ASCMode_TSIF_Pos (12UL)
11558 #define USIC_CH_PSR_ASCMode_TSIF_Msk (0x1000UL)
11559 #define USIC_CH_PSR_ASCMode_TBIF_Pos (13UL)
11560 #define USIC_CH_PSR_ASCMode_TBIF_Msk (0x2000UL)
11561 #define USIC_CH_PSR_ASCMode_RIF_Pos (14UL)
11562 #define USIC_CH_PSR_ASCMode_RIF_Msk (0x4000UL)
11563 #define USIC_CH_PSR_ASCMode_AIF_Pos (15UL)
11564 #define USIC_CH_PSR_ASCMode_AIF_Msk (0x8000UL)
11565 #define USIC_CH_PSR_ASCMode_BRGIF_Pos (16UL)
11566 #define USIC_CH_PSR_ASCMode_BRGIF_Msk (0x10000UL)
11568 /* ----------------------------- USIC_CH_PSR_SSCMode ---------------------------- */
11569 #define USIC_CH_PSR_SSCMode_MSLS_Pos (0UL)
11570 #define USIC_CH_PSR_SSCMode_MSLS_Msk (0x1UL)
11571 #define USIC_CH_PSR_SSCMode_DX2S_Pos (1UL)
11572 #define USIC_CH_PSR_SSCMode_DX2S_Msk (0x2UL)
11573 #define USIC_CH_PSR_SSCMode_MSLSEV_Pos (2UL)
11574 #define USIC_CH_PSR_SSCMode_MSLSEV_Msk (0x4UL)
11575 #define USIC_CH_PSR_SSCMode_DX2TEV_Pos (3UL)
11576 #define USIC_CH_PSR_SSCMode_DX2TEV_Msk (0x8UL)
11577 #define USIC_CH_PSR_SSCMode_PARERR_Pos (4UL)
11578 #define USIC_CH_PSR_SSCMode_PARERR_Msk (0x10UL)
11579 #define USIC_CH_PSR_SSCMode_RSIF_Pos (10UL)
11580 #define USIC_CH_PSR_SSCMode_RSIF_Msk (0x400UL)
11581 #define USIC_CH_PSR_SSCMode_DLIF_Pos (11UL)
11582 #define USIC_CH_PSR_SSCMode_DLIF_Msk (0x800UL)
11583 #define USIC_CH_PSR_SSCMode_TSIF_Pos (12UL)
11584 #define USIC_CH_PSR_SSCMode_TSIF_Msk (0x1000UL)
11585 #define USIC_CH_PSR_SSCMode_TBIF_Pos (13UL)
11586 #define USIC_CH_PSR_SSCMode_TBIF_Msk (0x2000UL)
11587 #define USIC_CH_PSR_SSCMode_RIF_Pos (14UL)
11588 #define USIC_CH_PSR_SSCMode_RIF_Msk (0x4000UL)
11589 #define USIC_CH_PSR_SSCMode_AIF_Pos (15UL)
11590 #define USIC_CH_PSR_SSCMode_AIF_Msk (0x8000UL)
11591 #define USIC_CH_PSR_SSCMode_BRGIF_Pos (16UL)
11592 #define USIC_CH_PSR_SSCMode_BRGIF_Msk (0x10000UL)
11594 /* ----------------------------- USIC_CH_PSR_IICMode ---------------------------- */
11595 #define USIC_CH_PSR_IICMode_SLSEL_Pos (0UL)
11596 #define USIC_CH_PSR_IICMode_SLSEL_Msk (0x1UL)
11597 #define USIC_CH_PSR_IICMode_WTDF_Pos (1UL)
11598 #define USIC_CH_PSR_IICMode_WTDF_Msk (0x2UL)
11599 #define USIC_CH_PSR_IICMode_SCR_Pos (2UL)
11600 #define USIC_CH_PSR_IICMode_SCR_Msk (0x4UL)
11601 #define USIC_CH_PSR_IICMode_RSCR_Pos (3UL)
11602 #define USIC_CH_PSR_IICMode_RSCR_Msk (0x8UL)
11603 #define USIC_CH_PSR_IICMode_PCR_Pos (4UL)
11604 #define USIC_CH_PSR_IICMode_PCR_Msk (0x10UL)
11605 #define USIC_CH_PSR_IICMode_NACK_Pos (5UL)
11606 #define USIC_CH_PSR_IICMode_NACK_Msk (0x20UL)
11607 #define USIC_CH_PSR_IICMode_ARL_Pos (6UL)
11608 #define USIC_CH_PSR_IICMode_ARL_Msk (0x40UL)
11609 #define USIC_CH_PSR_IICMode_SRR_Pos (7UL)
11610 #define USIC_CH_PSR_IICMode_SRR_Msk (0x80UL)
11611 #define USIC_CH_PSR_IICMode_ERR_Pos (8UL)
11612 #define USIC_CH_PSR_IICMode_ERR_Msk (0x100UL)
11613 #define USIC_CH_PSR_IICMode_ACK_Pos (9UL)
11614 #define USIC_CH_PSR_IICMode_ACK_Msk (0x200UL)
11615 #define USIC_CH_PSR_IICMode_RSIF_Pos (10UL)
11616 #define USIC_CH_PSR_IICMode_RSIF_Msk (0x400UL)
11617 #define USIC_CH_PSR_IICMode_DLIF_Pos (11UL)
11618 #define USIC_CH_PSR_IICMode_DLIF_Msk (0x800UL)
11619 #define USIC_CH_PSR_IICMode_TSIF_Pos (12UL)
11620 #define USIC_CH_PSR_IICMode_TSIF_Msk (0x1000UL)
11621 #define USIC_CH_PSR_IICMode_TBIF_Pos (13UL)
11622 #define USIC_CH_PSR_IICMode_TBIF_Msk (0x2000UL)
11623 #define USIC_CH_PSR_IICMode_RIF_Pos (14UL)
11624 #define USIC_CH_PSR_IICMode_RIF_Msk (0x4000UL)
11625 #define USIC_CH_PSR_IICMode_AIF_Pos (15UL)
11626 #define USIC_CH_PSR_IICMode_AIF_Msk (0x8000UL)
11627 #define USIC_CH_PSR_IICMode_BRGIF_Pos (16UL)
11628 #define USIC_CH_PSR_IICMode_BRGIF_Msk (0x10000UL)
11630 /* ----------------------------- USIC_CH_PSR_IISMode ---------------------------- */
11631 #define USIC_CH_PSR_IISMode_WA_Pos (0UL)
11632 #define USIC_CH_PSR_IISMode_WA_Msk (0x1UL)
11633 #define USIC_CH_PSR_IISMode_DX2S_Pos (1UL)
11634 #define USIC_CH_PSR_IISMode_DX2S_Msk (0x2UL)
11635 #define USIC_CH_PSR_IISMode_DX2TEV_Pos (3UL)
11636 #define USIC_CH_PSR_IISMode_DX2TEV_Msk (0x8UL)
11637 #define USIC_CH_PSR_IISMode_WAFE_Pos (4UL)
11638 #define USIC_CH_PSR_IISMode_WAFE_Msk (0x10UL)
11639 #define USIC_CH_PSR_IISMode_WARE_Pos (5UL)
11640 #define USIC_CH_PSR_IISMode_WARE_Msk (0x20UL)
11641 #define USIC_CH_PSR_IISMode_END_Pos (6UL)
11642 #define USIC_CH_PSR_IISMode_END_Msk (0x40UL)
11643 #define USIC_CH_PSR_IISMode_RSIF_Pos (10UL)
11644 #define USIC_CH_PSR_IISMode_RSIF_Msk (0x400UL)
11645 #define USIC_CH_PSR_IISMode_DLIF_Pos (11UL)
11646 #define USIC_CH_PSR_IISMode_DLIF_Msk (0x800UL)
11647 #define USIC_CH_PSR_IISMode_TSIF_Pos (12UL)
11648 #define USIC_CH_PSR_IISMode_TSIF_Msk (0x1000UL)
11649 #define USIC_CH_PSR_IISMode_TBIF_Pos (13UL)
11650 #define USIC_CH_PSR_IISMode_TBIF_Msk (0x2000UL)
11651 #define USIC_CH_PSR_IISMode_RIF_Pos (14UL)
11652 #define USIC_CH_PSR_IISMode_RIF_Msk (0x4000UL)
11653 #define USIC_CH_PSR_IISMode_AIF_Pos (15UL)
11654 #define USIC_CH_PSR_IISMode_AIF_Msk (0x8000UL)
11655 #define USIC_CH_PSR_IISMode_BRGIF_Pos (16UL)
11656 #define USIC_CH_PSR_IISMode_BRGIF_Msk (0x10000UL)
11658 /* -------------------------------- USIC_CH_PSCR -------------------------------- */
11659 #define USIC_CH_PSCR_CST0_Pos (0UL)
11660 #define USIC_CH_PSCR_CST0_Msk (0x1UL)
11661 #define USIC_CH_PSCR_CST1_Pos (1UL)
11662 #define USIC_CH_PSCR_CST1_Msk (0x2UL)
11663 #define USIC_CH_PSCR_CST2_Pos (2UL)
11664 #define USIC_CH_PSCR_CST2_Msk (0x4UL)
11665 #define USIC_CH_PSCR_CST3_Pos (3UL)
11666 #define USIC_CH_PSCR_CST3_Msk (0x8UL)
11667 #define USIC_CH_PSCR_CST4_Pos (4UL)
11668 #define USIC_CH_PSCR_CST4_Msk (0x10UL)
11669 #define USIC_CH_PSCR_CST5_Pos (5UL)
11670 #define USIC_CH_PSCR_CST5_Msk (0x20UL)
11671 #define USIC_CH_PSCR_CST6_Pos (6UL)
11672 #define USIC_CH_PSCR_CST6_Msk (0x40UL)
11673 #define USIC_CH_PSCR_CST7_Pos (7UL)
11674 #define USIC_CH_PSCR_CST7_Msk (0x80UL)
11675 #define USIC_CH_PSCR_CST8_Pos (8UL)
11676 #define USIC_CH_PSCR_CST8_Msk (0x100UL)
11677 #define USIC_CH_PSCR_CST9_Pos (9UL)
11678 #define USIC_CH_PSCR_CST9_Msk (0x200UL)
11679 #define USIC_CH_PSCR_CRSIF_Pos (10UL)
11680 #define USIC_CH_PSCR_CRSIF_Msk (0x400UL)
11681 #define USIC_CH_PSCR_CDLIF_Pos (11UL)
11682 #define USIC_CH_PSCR_CDLIF_Msk (0x800UL)
11683 #define USIC_CH_PSCR_CTSIF_Pos (12UL)
11684 #define USIC_CH_PSCR_CTSIF_Msk (0x1000UL)
11685 #define USIC_CH_PSCR_CTBIF_Pos (13UL)
11686 #define USIC_CH_PSCR_CTBIF_Msk (0x2000UL)
11687 #define USIC_CH_PSCR_CRIF_Pos (14UL)
11688 #define USIC_CH_PSCR_CRIF_Msk (0x4000UL)
11689 #define USIC_CH_PSCR_CAIF_Pos (15UL)
11690 #define USIC_CH_PSCR_CAIF_Msk (0x8000UL)
11691 #define USIC_CH_PSCR_CBRGIF_Pos (16UL)
11692 #define USIC_CH_PSCR_CBRGIF_Msk (0x10000UL)
11694 /* ------------------------------- USIC_CH_RBUFSR ------------------------------- */
11695 #define USIC_CH_RBUFSR_WLEN_Pos (0UL)
11696 #define USIC_CH_RBUFSR_WLEN_Msk (0xfUL)
11697 #define USIC_CH_RBUFSR_SOF_Pos (6UL)
11698 #define USIC_CH_RBUFSR_SOF_Msk (0x40UL)
11699 #define USIC_CH_RBUFSR_PAR_Pos (8UL)
11700 #define USIC_CH_RBUFSR_PAR_Msk (0x100UL)
11701 #define USIC_CH_RBUFSR_PERR_Pos (9UL)
11702 #define USIC_CH_RBUFSR_PERR_Msk (0x200UL)
11703 #define USIC_CH_RBUFSR_RDV0_Pos (13UL)
11704 #define USIC_CH_RBUFSR_RDV0_Msk (0x2000UL)
11705 #define USIC_CH_RBUFSR_RDV1_Pos (14UL)
11706 #define USIC_CH_RBUFSR_RDV1_Msk (0x4000UL)
11707 #define USIC_CH_RBUFSR_DS_Pos (15UL)
11708 #define USIC_CH_RBUFSR_DS_Msk (0x8000UL)
11710 /* -------------------------------- USIC_CH_RBUF -------------------------------- */
11711 #define USIC_CH_RBUF_DSR_Pos (0UL)
11712 #define USIC_CH_RBUF_DSR_Msk (0xffffUL)
11714 /* -------------------------------- USIC_CH_RBUFD ------------------------------- */
11715 #define USIC_CH_RBUFD_DSR_Pos (0UL)
11716 #define USIC_CH_RBUFD_DSR_Msk (0xffffUL)
11718 /* -------------------------------- USIC_CH_RBUF0 ------------------------------- */
11719 #define USIC_CH_RBUF0_DSR0_Pos (0UL)
11720 #define USIC_CH_RBUF0_DSR0_Msk (0xffffUL)
11722 /* -------------------------------- USIC_CH_RBUF1 ------------------------------- */
11723 #define USIC_CH_RBUF1_DSR1_Pos (0UL)
11724 #define USIC_CH_RBUF1_DSR1_Msk (0xffffUL)
11726 /* ------------------------------ USIC_CH_RBUF01SR ------------------------------ */
11727 #define USIC_CH_RBUF01SR_WLEN0_Pos (0UL)
11728 #define USIC_CH_RBUF01SR_WLEN0_Msk (0xfUL)
11729 #define USIC_CH_RBUF01SR_SOF0_Pos (6UL)
11730 #define USIC_CH_RBUF01SR_SOF0_Msk (0x40UL)
11731 #define USIC_CH_RBUF01SR_PAR0_Pos (8UL)
11732 #define USIC_CH_RBUF01SR_PAR0_Msk (0x100UL)
11733 #define USIC_CH_RBUF01SR_PERR0_Pos (9UL)
11734 #define USIC_CH_RBUF01SR_PERR0_Msk (0x200UL)
11735 #define USIC_CH_RBUF01SR_RDV00_Pos (13UL)
11736 #define USIC_CH_RBUF01SR_RDV00_Msk (0x2000UL)
11737 #define USIC_CH_RBUF01SR_RDV01_Pos (14UL)
11738 #define USIC_CH_RBUF01SR_RDV01_Msk (0x4000UL)
11739 #define USIC_CH_RBUF01SR_DS0_Pos (15UL)
11740 #define USIC_CH_RBUF01SR_DS0_Msk (0x8000UL)
11741 #define USIC_CH_RBUF01SR_WLEN1_Pos (16UL)
11742 #define USIC_CH_RBUF01SR_WLEN1_Msk (0xf0000UL)
11743 #define USIC_CH_RBUF01SR_SOF1_Pos (22UL)
11744 #define USIC_CH_RBUF01SR_SOF1_Msk (0x400000UL)
11745 #define USIC_CH_RBUF01SR_PAR1_Pos (24UL)
11746 #define USIC_CH_RBUF01SR_PAR1_Msk (0x1000000UL)
11747 #define USIC_CH_RBUF01SR_PERR1_Pos (25UL)
11748 #define USIC_CH_RBUF01SR_PERR1_Msk (0x2000000UL)
11749 #define USIC_CH_RBUF01SR_RDV10_Pos (29UL)
11750 #define USIC_CH_RBUF01SR_RDV10_Msk (0x20000000UL)
11751 #define USIC_CH_RBUF01SR_RDV11_Pos (30UL)
11752 #define USIC_CH_RBUF01SR_RDV11_Msk (0x40000000UL)
11753 #define USIC_CH_RBUF01SR_DS1_Pos (31UL)
11754 #define USIC_CH_RBUF01SR_DS1_Msk (0x80000000UL)
11756 /* --------------------------------- USIC_CH_FMR -------------------------------- */
11757 #define USIC_CH_FMR_MTDV_Pos (0UL)
11758 #define USIC_CH_FMR_MTDV_Msk (0x3UL)
11759 #define USIC_CH_FMR_ATVC_Pos (4UL)
11760 #define USIC_CH_FMR_ATVC_Msk (0x10UL)
11761 #define USIC_CH_FMR_CRDV0_Pos (14UL)
11762 #define USIC_CH_FMR_CRDV0_Msk (0x4000UL)
11763 #define USIC_CH_FMR_CRDV1_Pos (15UL)
11764 #define USIC_CH_FMR_CRDV1_Msk (0x8000UL)
11765 #define USIC_CH_FMR_SIO0_Pos (16UL)
11766 #define USIC_CH_FMR_SIO0_Msk (0x10000UL)
11767 #define USIC_CH_FMR_SIO1_Pos (17UL)
11768 #define USIC_CH_FMR_SIO1_Msk (0x20000UL)
11769 #define USIC_CH_FMR_SIO2_Pos (18UL)
11770 #define USIC_CH_FMR_SIO2_Msk (0x40000UL)
11771 #define USIC_CH_FMR_SIO3_Pos (19UL)
11772 #define USIC_CH_FMR_SIO3_Msk (0x80000UL)
11773 #define USIC_CH_FMR_SIO4_Pos (20UL)
11774 #define USIC_CH_FMR_SIO4_Msk (0x100000UL)
11775 #define USIC_CH_FMR_SIO5_Pos (21UL)
11776 #define USIC_CH_FMR_SIO5_Msk (0x200000UL)
11778 /* -------------------------------- USIC_CH_TBUF -------------------------------- */
11779 #define USIC_CH_TBUF_TDATA_Pos (0UL)
11780 #define USIC_CH_TBUF_TDATA_Msk (0xffffUL)
11782 /* --------------------------------- USIC_CH_BYP -------------------------------- */
11783 #define USIC_CH_BYP_BDATA_Pos (0UL)
11784 #define USIC_CH_BYP_BDATA_Msk (0xffffUL)
11786 /* -------------------------------- USIC_CH_BYPCR ------------------------------- */
11787 #define USIC_CH_BYPCR_BWLE_Pos (0UL)
11788 #define USIC_CH_BYPCR_BWLE_Msk (0xfUL)
11789 #define USIC_CH_BYPCR_BDSSM_Pos (8UL)
11790 #define USIC_CH_BYPCR_BDSSM_Msk (0x100UL)
11791 #define USIC_CH_BYPCR_BDEN_Pos (10UL)
11792 #define USIC_CH_BYPCR_BDEN_Msk (0xc00UL)
11793 #define USIC_CH_BYPCR_BDVTR_Pos (12UL)
11794 #define USIC_CH_BYPCR_BDVTR_Msk (0x1000UL)
11795 #define USIC_CH_BYPCR_BPRIO_Pos (13UL)
11796 #define USIC_CH_BYPCR_BPRIO_Msk (0x2000UL)
11797 #define USIC_CH_BYPCR_BDV_Pos (15UL)
11798 #define USIC_CH_BYPCR_BDV_Msk (0x8000UL)
11799 #define USIC_CH_BYPCR_BSELO_Pos (16UL)
11800 #define USIC_CH_BYPCR_BSELO_Msk (0x1f0000UL)
11801 #define USIC_CH_BYPCR_BHPC_Pos (21UL)
11802 #define USIC_CH_BYPCR_BHPC_Msk (0xe00000UL)
11804 /* -------------------------------- USIC_CH_TBCTR ------------------------------- */
11805 #define USIC_CH_TBCTR_DPTR_Pos (0UL)
11806 #define USIC_CH_TBCTR_DPTR_Msk (0x3fUL)
11807 #define USIC_CH_TBCTR_LIMIT_Pos (8UL)
11808 #define USIC_CH_TBCTR_LIMIT_Msk (0x3f00UL)
11809 #define USIC_CH_TBCTR_STBTM_Pos (14UL)
11810 #define USIC_CH_TBCTR_STBTM_Msk (0x4000UL)
11811 #define USIC_CH_TBCTR_STBTEN_Pos (15UL)
11812 #define USIC_CH_TBCTR_STBTEN_Msk (0x8000UL)
11813 #define USIC_CH_TBCTR_STBINP_Pos (16UL)
11814 #define USIC_CH_TBCTR_STBINP_Msk (0x70000UL)
11815 #define USIC_CH_TBCTR_ATBINP_Pos (19UL)
11816 #define USIC_CH_TBCTR_ATBINP_Msk (0x380000UL)
11817 #define USIC_CH_TBCTR_SIZE_Pos (24UL)
11818 #define USIC_CH_TBCTR_SIZE_Msk (0x7000000UL)
11819 #define USIC_CH_TBCTR_LOF_Pos (28UL)
11820 #define USIC_CH_TBCTR_LOF_Msk (0x10000000UL)
11821 #define USIC_CH_TBCTR_STBIEN_Pos (30UL)
11822 #define USIC_CH_TBCTR_STBIEN_Msk (0x40000000UL)
11823 #define USIC_CH_TBCTR_TBERIEN_Pos (31UL)
11824 #define USIC_CH_TBCTR_TBERIEN_Msk (0x80000000UL)
11826 /* -------------------------------- USIC_CH_RBCTR ------------------------------- */
11827 #define USIC_CH_RBCTR_DPTR_Pos (0UL)
11828 #define USIC_CH_RBCTR_DPTR_Msk (0x3fUL)
11829 #define USIC_CH_RBCTR_LIMIT_Pos (8UL)
11830 #define USIC_CH_RBCTR_LIMIT_Msk (0x3f00UL)
11831 #define USIC_CH_RBCTR_SRBTM_Pos (14UL)
11832 #define USIC_CH_RBCTR_SRBTM_Msk (0x4000UL)
11833 #define USIC_CH_RBCTR_SRBTEN_Pos (15UL)
11834 #define USIC_CH_RBCTR_SRBTEN_Msk (0x8000UL)
11835 #define USIC_CH_RBCTR_SRBINP_Pos (16UL)
11836 #define USIC_CH_RBCTR_SRBINP_Msk (0x70000UL)
11837 #define USIC_CH_RBCTR_ARBINP_Pos (19UL)
11838 #define USIC_CH_RBCTR_ARBINP_Msk (0x380000UL)
11839 #define USIC_CH_RBCTR_RCIM_Pos (22UL)
11840 #define USIC_CH_RBCTR_RCIM_Msk (0xc00000UL)
11841 #define USIC_CH_RBCTR_SIZE_Pos (24UL)
11842 #define USIC_CH_RBCTR_SIZE_Msk (0x7000000UL)
11843 #define USIC_CH_RBCTR_RNM_Pos (27UL)
11844 #define USIC_CH_RBCTR_RNM_Msk (0x8000000UL)
11845 #define USIC_CH_RBCTR_LOF_Pos (28UL)
11846 #define USIC_CH_RBCTR_LOF_Msk (0x10000000UL)
11847 #define USIC_CH_RBCTR_ARBIEN_Pos (29UL)
11848 #define USIC_CH_RBCTR_ARBIEN_Msk (0x20000000UL)
11849 #define USIC_CH_RBCTR_SRBIEN_Pos (30UL)
11850 #define USIC_CH_RBCTR_SRBIEN_Msk (0x40000000UL)
11851 #define USIC_CH_RBCTR_RBERIEN_Pos (31UL)
11852 #define USIC_CH_RBCTR_RBERIEN_Msk (0x80000000UL)
11854 /* ------------------------------- USIC_CH_TRBPTR ------------------------------- */
11855 #define USIC_CH_TRBPTR_TDIPTR_Pos (0UL)
11856 #define USIC_CH_TRBPTR_TDIPTR_Msk (0x3fUL)
11857 #define USIC_CH_TRBPTR_TDOPTR_Pos (8UL)
11858 #define USIC_CH_TRBPTR_TDOPTR_Msk (0x3f00UL)
11859 #define USIC_CH_TRBPTR_RDIPTR_Pos (16UL)
11860 #define USIC_CH_TRBPTR_RDIPTR_Msk (0x3f0000UL)
11861 #define USIC_CH_TRBPTR_RDOPTR_Pos (24UL)
11862 #define USIC_CH_TRBPTR_RDOPTR_Msk (0x3f000000UL)
11864 /* -------------------------------- USIC_CH_TRBSR ------------------------------- */
11865 #define USIC_CH_TRBSR_SRBI_Pos (0UL)
11866 #define USIC_CH_TRBSR_SRBI_Msk (0x1UL)
11867 #define USIC_CH_TRBSR_RBERI_Pos (1UL)
11868 #define USIC_CH_TRBSR_RBERI_Msk (0x2UL)
11869 #define USIC_CH_TRBSR_ARBI_Pos (2UL)
11870 #define USIC_CH_TRBSR_ARBI_Msk (0x4UL)
11871 #define USIC_CH_TRBSR_REMPTY_Pos (3UL)
11872 #define USIC_CH_TRBSR_REMPTY_Msk (0x8UL)
11873 #define USIC_CH_TRBSR_RFULL_Pos (4UL)
11874 #define USIC_CH_TRBSR_RFULL_Msk (0x10UL)
11875 #define USIC_CH_TRBSR_RBUS_Pos (5UL)
11876 #define USIC_CH_TRBSR_RBUS_Msk (0x20UL)
11877 #define USIC_CH_TRBSR_SRBT_Pos (6UL)
11878 #define USIC_CH_TRBSR_SRBT_Msk (0x40UL)
11879 #define USIC_CH_TRBSR_STBI_Pos (8UL)
11880 #define USIC_CH_TRBSR_STBI_Msk (0x100UL)
11881 #define USIC_CH_TRBSR_TBERI_Pos (9UL)
11882 #define USIC_CH_TRBSR_TBERI_Msk (0x200UL)
11883 #define USIC_CH_TRBSR_TEMPTY_Pos (11UL)
11884 #define USIC_CH_TRBSR_TEMPTY_Msk (0x800UL)
11885 #define USIC_CH_TRBSR_TFULL_Pos (12UL)
11886 #define USIC_CH_TRBSR_TFULL_Msk (0x1000UL)
11887 #define USIC_CH_TRBSR_TBUS_Pos (13UL)
11888 #define USIC_CH_TRBSR_TBUS_Msk (0x2000UL)
11889 #define USIC_CH_TRBSR_STBT_Pos (14UL)
11890 #define USIC_CH_TRBSR_STBT_Msk (0x4000UL)
11891 #define USIC_CH_TRBSR_RBFLVL_Pos (16UL)
11892 #define USIC_CH_TRBSR_RBFLVL_Msk (0x7f0000UL)
11893 #define USIC_CH_TRBSR_TBFLVL_Pos (24UL)
11894 #define USIC_CH_TRBSR_TBFLVL_Msk (0x7f000000UL)
11896 /* ------------------------------- USIC_CH_TRBSCR ------------------------------- */
11897 #define USIC_CH_TRBSCR_CSRBI_Pos (0UL)
11898 #define USIC_CH_TRBSCR_CSRBI_Msk (0x1UL)
11899 #define USIC_CH_TRBSCR_CRBERI_Pos (1UL)
11900 #define USIC_CH_TRBSCR_CRBERI_Msk (0x2UL)
11901 #define USIC_CH_TRBSCR_CARBI_Pos (2UL)
11902 #define USIC_CH_TRBSCR_CARBI_Msk (0x4UL)
11903 #define USIC_CH_TRBSCR_CSTBI_Pos (8UL)
11904 #define USIC_CH_TRBSCR_CSTBI_Msk (0x100UL)
11905 #define USIC_CH_TRBSCR_CTBERI_Pos (9UL)
11906 #define USIC_CH_TRBSCR_CTBERI_Msk (0x200UL)
11907 #define USIC_CH_TRBSCR_CBDV_Pos (10UL)
11908 #define USIC_CH_TRBSCR_CBDV_Msk (0x400UL)
11909 #define USIC_CH_TRBSCR_FLUSHRB_Pos (14UL)
11910 #define USIC_CH_TRBSCR_FLUSHRB_Msk (0x4000UL)
11911 #define USIC_CH_TRBSCR_FLUSHTB_Pos (15UL)
11912 #define USIC_CH_TRBSCR_FLUSHTB_Msk (0x8000UL)
11914 /* -------------------------------- USIC_CH_OUTR -------------------------------- */
11915 #define USIC_CH_OUTR_DSR_Pos (0UL)
11916 #define USIC_CH_OUTR_DSR_Msk (0xffffUL)
11917 #define USIC_CH_OUTR_RCI_Pos (16UL)
11918 #define USIC_CH_OUTR_RCI_Msk (0x1f0000UL)
11920 /* -------------------------------- USIC_CH_OUTDR ------------------------------- */
11921 #define USIC_CH_OUTDR_DSR_Pos (0UL)
11922 #define USIC_CH_OUTDR_DSR_Msk (0xffffUL)
11923 #define USIC_CH_OUTDR_RCI_Pos (16UL)
11924 #define USIC_CH_OUTDR_RCI_Msk (0x1f0000UL)
11926 /* --------------------------------- USIC_CH_IN --------------------------------- */
11927 #define USIC_CH_IN_TDATA_Pos (0UL)
11928 #define USIC_CH_IN_TDATA_Msk (0xffffUL)
11931 /* ================================================================================ */
11932 /* ================ struct 'CAN' Position & Mask ================ */
11933 /* ================================================================================ */
11934 
11935 
11936 /* ----------------------------------- CAN_CLC ---------------------------------- */
11937 #define CAN_CLC_DISR_Pos (0UL)
11938 #define CAN_CLC_DISR_Msk (0x1UL)
11939 #define CAN_CLC_DISS_Pos (1UL)
11940 #define CAN_CLC_DISS_Msk (0x2UL)
11941 #define CAN_CLC_EDIS_Pos (3UL)
11942 #define CAN_CLC_EDIS_Msk (0x8UL)
11944 /* ----------------------------------- CAN_ID ----------------------------------- */
11945 #define CAN_ID_MOD_REV_Pos (0UL)
11946 #define CAN_ID_MOD_REV_Msk (0xffUL)
11947 #define CAN_ID_MOD_TYPE_Pos (8UL)
11948 #define CAN_ID_MOD_TYPE_Msk (0xff00UL)
11949 #define CAN_ID_MOD_NUMBER_Pos (16UL)
11950 #define CAN_ID_MOD_NUMBER_Msk (0xffff0000UL)
11952 /* ----------------------------------- CAN_FDR ---------------------------------- */
11953 #define CAN_FDR_STEP_Pos (0UL)
11954 #define CAN_FDR_STEP_Msk (0x3ffUL)
11955 #define CAN_FDR_DM_Pos (14UL)
11956 #define CAN_FDR_DM_Msk (0xc000UL)
11958 /* ---------------------------------- CAN_LIST ---------------------------------- */
11959 #define CAN_LIST_BEGIN_Pos (0UL)
11960 #define CAN_LIST_BEGIN_Msk (0xffUL)
11961 #define CAN_LIST_END_Pos (8UL)
11962 #define CAN_LIST_END_Msk (0xff00UL)
11963 #define CAN_LIST_SIZE_Pos (16UL)
11964 #define CAN_LIST_SIZE_Msk (0xff0000UL)
11965 #define CAN_LIST_EMPTY_Pos (24UL)
11966 #define CAN_LIST_EMPTY_Msk (0x1000000UL)
11968 /* ---------------------------------- CAN_MSPND --------------------------------- */
11969 #define CAN_MSPND_PND_Pos (0UL)
11970 #define CAN_MSPND_PND_Msk (0xffffffffUL)
11972 /* ---------------------------------- CAN_MSID ---------------------------------- */
11973 #define CAN_MSID_INDEX_Pos (0UL)
11974 #define CAN_MSID_INDEX_Msk (0x3fUL)
11976 /* --------------------------------- CAN_MSIMASK -------------------------------- */
11977 #define CAN_MSIMASK_IM_Pos (0UL)
11978 #define CAN_MSIMASK_IM_Msk (0xffffffffUL)
11980 /* --------------------------------- CAN_PANCTR --------------------------------- */
11981 #define CAN_PANCTR_PANCMD_Pos (0UL)
11982 #define CAN_PANCTR_PANCMD_Msk (0xffUL)
11983 #define CAN_PANCTR_BUSY_Pos (8UL)
11984 #define CAN_PANCTR_BUSY_Msk (0x100UL)
11985 #define CAN_PANCTR_RBUSY_Pos (9UL)
11986 #define CAN_PANCTR_RBUSY_Msk (0x200UL)
11987 #define CAN_PANCTR_PANAR1_Pos (16UL)
11988 #define CAN_PANCTR_PANAR1_Msk (0xff0000UL)
11989 #define CAN_PANCTR_PANAR2_Pos (24UL)
11990 #define CAN_PANCTR_PANAR2_Msk (0xff000000UL)
11992 /* ----------------------------------- CAN_MCR ---------------------------------- */
11993 #define CAN_MCR_CLKSEL_Pos (0UL)
11994 #define CAN_MCR_CLKSEL_Msk (0xfUL)
11995 #define CAN_MCR_MPSEL_Pos (12UL)
11996 #define CAN_MCR_MPSEL_Msk (0xf000UL)
11998 /* ---------------------------------- CAN_MITR ---------------------------------- */
11999 #define CAN_MITR_IT_Pos (0UL)
12000 #define CAN_MITR_IT_Msk (0xffUL)
12003 /* ================================================================================ */
12004 /* ================ Group 'CAN_NODE' Position & Mask ================ */
12005 /* ================================================================================ */
12006 
12007 
12008 /* -------------------------------- CAN_NODE_NCR -------------------------------- */
12009 #define CAN_NODE_NCR_INIT_Pos (0UL)
12010 #define CAN_NODE_NCR_INIT_Msk (0x1UL)
12011 #define CAN_NODE_NCR_TRIE_Pos (1UL)
12012 #define CAN_NODE_NCR_TRIE_Msk (0x2UL)
12013 #define CAN_NODE_NCR_LECIE_Pos (2UL)
12014 #define CAN_NODE_NCR_LECIE_Msk (0x4UL)
12015 #define CAN_NODE_NCR_ALIE_Pos (3UL)
12016 #define CAN_NODE_NCR_ALIE_Msk (0x8UL)
12017 #define CAN_NODE_NCR_CANDIS_Pos (4UL)
12018 #define CAN_NODE_NCR_CANDIS_Msk (0x10UL)
12019 #define CAN_NODE_NCR_TXDIS_Pos (5UL)
12020 #define CAN_NODE_NCR_TXDIS_Msk (0x20UL)
12021 #define CAN_NODE_NCR_CCE_Pos (6UL)
12022 #define CAN_NODE_NCR_CCE_Msk (0x40UL)
12023 #define CAN_NODE_NCR_CALM_Pos (7UL)
12024 #define CAN_NODE_NCR_CALM_Msk (0x80UL)
12026 /* -------------------------------- CAN_NODE_NSR -------------------------------- */
12027 #define CAN_NODE_NSR_LEC_Pos (0UL)
12028 #define CAN_NODE_NSR_LEC_Msk (0x7UL)
12029 #define CAN_NODE_NSR_TXOK_Pos (3UL)
12030 #define CAN_NODE_NSR_TXOK_Msk (0x8UL)
12031 #define CAN_NODE_NSR_RXOK_Pos (4UL)
12032 #define CAN_NODE_NSR_RXOK_Msk (0x10UL)
12033 #define CAN_NODE_NSR_ALERT_Pos (5UL)
12034 #define CAN_NODE_NSR_ALERT_Msk (0x20UL)
12035 #define CAN_NODE_NSR_EWRN_Pos (6UL)
12036 #define CAN_NODE_NSR_EWRN_Msk (0x40UL)
12037 #define CAN_NODE_NSR_BOFF_Pos (7UL)
12038 #define CAN_NODE_NSR_BOFF_Msk (0x80UL)
12039 #define CAN_NODE_NSR_LLE_Pos (8UL)
12040 #define CAN_NODE_NSR_LLE_Msk (0x100UL)
12041 #define CAN_NODE_NSR_LOE_Pos (9UL)
12042 #define CAN_NODE_NSR_LOE_Msk (0x200UL)
12044 /* -------------------------------- CAN_NODE_NIPR ------------------------------- */
12045 #define CAN_NODE_NIPR_ALINP_Pos (0UL)
12046 #define CAN_NODE_NIPR_ALINP_Msk (0xfUL)
12047 #define CAN_NODE_NIPR_LECINP_Pos (4UL)
12048 #define CAN_NODE_NIPR_LECINP_Msk (0xf0UL)
12049 #define CAN_NODE_NIPR_TRINP_Pos (8UL)
12050 #define CAN_NODE_NIPR_TRINP_Msk (0xf00UL)
12051 #define CAN_NODE_NIPR_CFCINP_Pos (12UL)
12052 #define CAN_NODE_NIPR_CFCINP_Msk (0xf000UL)
12054 /* -------------------------------- CAN_NODE_NPCR ------------------------------- */
12055 #define CAN_NODE_NPCR_RXSEL_Pos (0UL)
12056 #define CAN_NODE_NPCR_RXSEL_Msk (0x7UL)
12057 #define CAN_NODE_NPCR_LBM_Pos (8UL)
12058 #define CAN_NODE_NPCR_LBM_Msk (0x100UL)
12060 /* -------------------------------- CAN_NODE_NBTR ------------------------------- */
12061 #define CAN_NODE_NBTR_BRP_Pos (0UL)
12062 #define CAN_NODE_NBTR_BRP_Msk (0x3fUL)
12063 #define CAN_NODE_NBTR_SJW_Pos (6UL)
12064 #define CAN_NODE_NBTR_SJW_Msk (0xc0UL)
12065 #define CAN_NODE_NBTR_TSEG1_Pos (8UL)
12066 #define CAN_NODE_NBTR_TSEG1_Msk (0xf00UL)
12067 #define CAN_NODE_NBTR_TSEG2_Pos (12UL)
12068 #define CAN_NODE_NBTR_TSEG2_Msk (0x7000UL)
12069 #define CAN_NODE_NBTR_DIV8_Pos (15UL)
12070 #define CAN_NODE_NBTR_DIV8_Msk (0x8000UL)
12072 /* ------------------------------- CAN_NODE_NECNT ------------------------------- */
12073 #define CAN_NODE_NECNT_REC_Pos (0UL)
12074 #define CAN_NODE_NECNT_REC_Msk (0xffUL)
12075 #define CAN_NODE_NECNT_TEC_Pos (8UL)
12076 #define CAN_NODE_NECNT_TEC_Msk (0xff00UL)
12077 #define CAN_NODE_NECNT_EWRNLVL_Pos (16UL)
12078 #define CAN_NODE_NECNT_EWRNLVL_Msk (0xff0000UL)
12079 #define CAN_NODE_NECNT_LETD_Pos (24UL)
12080 #define CAN_NODE_NECNT_LETD_Msk (0x1000000UL)
12081 #define CAN_NODE_NECNT_LEINC_Pos (25UL)
12082 #define CAN_NODE_NECNT_LEINC_Msk (0x2000000UL)
12084 /* -------------------------------- CAN_NODE_NFCR ------------------------------- */
12085 #define CAN_NODE_NFCR_CFC_Pos (0UL)
12086 #define CAN_NODE_NFCR_CFC_Msk (0xffffUL)
12087 #define CAN_NODE_NFCR_CFSEL_Pos (16UL)
12088 #define CAN_NODE_NFCR_CFSEL_Msk (0x70000UL)
12089 #define CAN_NODE_NFCR_CFMOD_Pos (19UL)
12090 #define CAN_NODE_NFCR_CFMOD_Msk (0x180000UL)
12091 #define CAN_NODE_NFCR_CFCIE_Pos (22UL)
12092 #define CAN_NODE_NFCR_CFCIE_Msk (0x400000UL)
12093 #define CAN_NODE_NFCR_CFCOV_Pos (23UL)
12094 #define CAN_NODE_NFCR_CFCOV_Msk (0x800000UL)
12097 /* ================================================================================ */
12098 /* ================ Cluster Group 'CAN_MO' Position & Mask ================ */
12099 /* ================================================================================ */
12100 
12101 
12102 /* -------------------------------- CAN_MO_MOFCR -------------------------------- */
12103 #define CAN_MO_MOFCR_MMC_Pos (0UL)
12104 #define CAN_MO_MOFCR_MMC_Msk (0xfUL)
12105 #define CAN_MO_MOFCR_RXTOE_Pos (4UL)
12106 #define CAN_MO_MOFCR_RXTOE_Msk (0x10UL)
12107 #define CAN_MO_MOFCR_GDFS_Pos (8UL)
12108 #define CAN_MO_MOFCR_GDFS_Msk (0x100UL)
12109 #define CAN_MO_MOFCR_IDC_Pos (9UL)
12110 #define CAN_MO_MOFCR_IDC_Msk (0x200UL)
12111 #define CAN_MO_MOFCR_DLCC_Pos (10UL)
12112 #define CAN_MO_MOFCR_DLCC_Msk (0x400UL)
12113 #define CAN_MO_MOFCR_DATC_Pos (11UL)
12114 #define CAN_MO_MOFCR_DATC_Msk (0x800UL)
12115 #define CAN_MO_MOFCR_RXIE_Pos (16UL)
12116 #define CAN_MO_MOFCR_RXIE_Msk (0x10000UL)
12117 #define CAN_MO_MOFCR_TXIE_Pos (17UL)
12118 #define CAN_MO_MOFCR_TXIE_Msk (0x20000UL)
12119 #define CAN_MO_MOFCR_OVIE_Pos (18UL)
12120 #define CAN_MO_MOFCR_OVIE_Msk (0x40000UL)
12121 #define CAN_MO_MOFCR_FRREN_Pos (20UL)
12122 #define CAN_MO_MOFCR_FRREN_Msk (0x100000UL)
12123 #define CAN_MO_MOFCR_RMM_Pos (21UL)
12124 #define CAN_MO_MOFCR_RMM_Msk (0x200000UL)
12125 #define CAN_MO_MOFCR_SDT_Pos (22UL)
12126 #define CAN_MO_MOFCR_SDT_Msk (0x400000UL)
12127 #define CAN_MO_MOFCR_STT_Pos (23UL)
12128 #define CAN_MO_MOFCR_STT_Msk (0x800000UL)
12129 #define CAN_MO_MOFCR_DLC_Pos (24UL)
12130 #define CAN_MO_MOFCR_DLC_Msk (0xf000000UL)
12132 /* -------------------------------- CAN_MO_MOFGPR ------------------------------- */
12133 #define CAN_MO_MOFGPR_BOT_Pos (0UL)
12134 #define CAN_MO_MOFGPR_BOT_Msk (0xffUL)
12135 #define CAN_MO_MOFGPR_TOP_Pos (8UL)
12136 #define CAN_MO_MOFGPR_TOP_Msk (0xff00UL)
12137 #define CAN_MO_MOFGPR_CUR_Pos (16UL)
12138 #define CAN_MO_MOFGPR_CUR_Msk (0xff0000UL)
12139 #define CAN_MO_MOFGPR_SEL_Pos (24UL)
12140 #define CAN_MO_MOFGPR_SEL_Msk (0xff000000UL)
12142 /* -------------------------------- CAN_MO_MOIPR -------------------------------- */
12143 #define CAN_MO_MOIPR_RXINP_Pos (0UL)
12144 #define CAN_MO_MOIPR_RXINP_Msk (0xfUL)
12145 #define CAN_MO_MOIPR_TXINP_Pos (4UL)
12146 #define CAN_MO_MOIPR_TXINP_Msk (0xf0UL)
12147 #define CAN_MO_MOIPR_MPN_Pos (8UL)
12148 #define CAN_MO_MOIPR_MPN_Msk (0xff00UL)
12149 #define CAN_MO_MOIPR_CFCVAL_Pos (16UL)
12150 #define CAN_MO_MOIPR_CFCVAL_Msk (0xffff0000UL)
12152 /* -------------------------------- CAN_MO_MOAMR -------------------------------- */
12153 #define CAN_MO_MOAMR_AM_Pos (0UL)
12154 #define CAN_MO_MOAMR_AM_Msk (0x1fffffffUL)
12155 #define CAN_MO_MOAMR_MIDE_Pos (29UL)
12156 #define CAN_MO_MOAMR_MIDE_Msk (0x20000000UL)
12158 /* ------------------------------- CAN_MO_MODATAL ------------------------------- */
12159 #define CAN_MO_MODATAL_DB0_Pos (0UL)
12160 #define CAN_MO_MODATAL_DB0_Msk (0xffUL)
12161 #define CAN_MO_MODATAL_DB1_Pos (8UL)
12162 #define CAN_MO_MODATAL_DB1_Msk (0xff00UL)
12163 #define CAN_MO_MODATAL_DB2_Pos (16UL)
12164 #define CAN_MO_MODATAL_DB2_Msk (0xff0000UL)
12165 #define CAN_MO_MODATAL_DB3_Pos (24UL)
12166 #define CAN_MO_MODATAL_DB3_Msk (0xff000000UL)
12168 /* ------------------------------- CAN_MO_MODATAH ------------------------------- */
12169 #define CAN_MO_MODATAH_DB4_Pos (0UL)
12170 #define CAN_MO_MODATAH_DB4_Msk (0xffUL)
12171 #define CAN_MO_MODATAH_DB5_Pos (8UL)
12172 #define CAN_MO_MODATAH_DB5_Msk (0xff00UL)
12173 #define CAN_MO_MODATAH_DB6_Pos (16UL)
12174 #define CAN_MO_MODATAH_DB6_Msk (0xff0000UL)
12175 #define CAN_MO_MODATAH_DB7_Pos (24UL)
12176 #define CAN_MO_MODATAH_DB7_Msk (0xff000000UL)
12178 /* --------------------------------- CAN_MO_MOAR -------------------------------- */
12179 #define CAN_MO_MOAR_ID_Pos (0UL)
12180 #define CAN_MO_MOAR_ID_Msk (0x1fffffffUL)
12181 #define CAN_MO_MOAR_IDE_Pos (29UL)
12182 #define CAN_MO_MOAR_IDE_Msk (0x20000000UL)
12183 #define CAN_MO_MOAR_PRI_Pos (30UL)
12184 #define CAN_MO_MOAR_PRI_Msk (0xc0000000UL)
12186 /* -------------------------------- CAN_MO_MOCTR -------------------------------- */
12187 #define CAN_MO_MOCTR_RESRXPND_Pos (0UL)
12188 #define CAN_MO_MOCTR_RESRXPND_Msk (0x1UL)
12189 #define CAN_MO_MOCTR_RESTXPND_Pos (1UL)
12190 #define CAN_MO_MOCTR_RESTXPND_Msk (0x2UL)
12191 #define CAN_MO_MOCTR_RESRXUPD_Pos (2UL)
12192 #define CAN_MO_MOCTR_RESRXUPD_Msk (0x4UL)
12193 #define CAN_MO_MOCTR_RESNEWDAT_Pos (3UL)
12194 #define CAN_MO_MOCTR_RESNEWDAT_Msk (0x8UL)
12195 #define CAN_MO_MOCTR_RESMSGLST_Pos (4UL)
12196 #define CAN_MO_MOCTR_RESMSGLST_Msk (0x10UL)
12197 #define CAN_MO_MOCTR_RESMSGVAL_Pos (5UL)
12198 #define CAN_MO_MOCTR_RESMSGVAL_Msk (0x20UL)
12199 #define CAN_MO_MOCTR_RESRTSEL_Pos (6UL)
12200 #define CAN_MO_MOCTR_RESRTSEL_Msk (0x40UL)
12201 #define CAN_MO_MOCTR_RESRXEN_Pos (7UL)
12202 #define CAN_MO_MOCTR_RESRXEN_Msk (0x80UL)
12203 #define CAN_MO_MOCTR_RESTXRQ_Pos (8UL)
12204 #define CAN_MO_MOCTR_RESTXRQ_Msk (0x100UL)
12205 #define CAN_MO_MOCTR_RESTXEN0_Pos (9UL)
12206 #define CAN_MO_MOCTR_RESTXEN0_Msk (0x200UL)
12207 #define CAN_MO_MOCTR_RESTXEN1_Pos (10UL)
12208 #define CAN_MO_MOCTR_RESTXEN1_Msk (0x400UL)
12209 #define CAN_MO_MOCTR_RESDIR_Pos (11UL)
12210 #define CAN_MO_MOCTR_RESDIR_Msk (0x800UL)
12211 #define CAN_MO_MOCTR_SETRXPND_Pos (16UL)
12212 #define CAN_MO_MOCTR_SETRXPND_Msk (0x10000UL)
12213 #define CAN_MO_MOCTR_SETTXPND_Pos (17UL)
12214 #define CAN_MO_MOCTR_SETTXPND_Msk (0x20000UL)
12215 #define CAN_MO_MOCTR_SETRXUPD_Pos (18UL)
12216 #define CAN_MO_MOCTR_SETRXUPD_Msk (0x40000UL)
12217 #define CAN_MO_MOCTR_SETNEWDAT_Pos (19UL)
12218 #define CAN_MO_MOCTR_SETNEWDAT_Msk (0x80000UL)
12219 #define CAN_MO_MOCTR_SETMSGLST_Pos (20UL)
12220 #define CAN_MO_MOCTR_SETMSGLST_Msk (0x100000UL)
12221 #define CAN_MO_MOCTR_SETMSGVAL_Pos (21UL)
12222 #define CAN_MO_MOCTR_SETMSGVAL_Msk (0x200000UL)
12223 #define CAN_MO_MOCTR_SETRTSEL_Pos (22UL)
12224 #define CAN_MO_MOCTR_SETRTSEL_Msk (0x400000UL)
12225 #define CAN_MO_MOCTR_SETRXEN_Pos (23UL)
12226 #define CAN_MO_MOCTR_SETRXEN_Msk (0x800000UL)
12227 #define CAN_MO_MOCTR_SETTXRQ_Pos (24UL)
12228 #define CAN_MO_MOCTR_SETTXRQ_Msk (0x1000000UL)
12229 #define CAN_MO_MOCTR_SETTXEN0_Pos (25UL)
12230 #define CAN_MO_MOCTR_SETTXEN0_Msk (0x2000000UL)
12231 #define CAN_MO_MOCTR_SETTXEN1_Pos (26UL)
12232 #define CAN_MO_MOCTR_SETTXEN1_Msk (0x4000000UL)
12233 #define CAN_MO_MOCTR_SETDIR_Pos (27UL)
12234 #define CAN_MO_MOCTR_SETDIR_Msk (0x8000000UL)
12236 /* -------------------------------- CAN_MO_MOSTAT ------------------------------- */
12237 #define CAN_MO_MOSTAT_RXPND_Pos (0UL)
12238 #define CAN_MO_MOSTAT_RXPND_Msk (0x1UL)
12239 #define CAN_MO_MOSTAT_TXPND_Pos (1UL)
12240 #define CAN_MO_MOSTAT_TXPND_Msk (0x2UL)
12241 #define CAN_MO_MOSTAT_RXUPD_Pos (2UL)
12242 #define CAN_MO_MOSTAT_RXUPD_Msk (0x4UL)
12243 #define CAN_MO_MOSTAT_NEWDAT_Pos (3UL)
12244 #define CAN_MO_MOSTAT_NEWDAT_Msk (0x8UL)
12245 #define CAN_MO_MOSTAT_MSGLST_Pos (4UL)
12246 #define CAN_MO_MOSTAT_MSGLST_Msk (0x10UL)
12247 #define CAN_MO_MOSTAT_MSGVAL_Pos (5UL)
12248 #define CAN_MO_MOSTAT_MSGVAL_Msk (0x20UL)
12249 #define CAN_MO_MOSTAT_RTSEL_Pos (6UL)
12250 #define CAN_MO_MOSTAT_RTSEL_Msk (0x40UL)
12251 #define CAN_MO_MOSTAT_RXEN_Pos (7UL)
12252 #define CAN_MO_MOSTAT_RXEN_Msk (0x80UL)
12253 #define CAN_MO_MOSTAT_TXRQ_Pos (8UL)
12254 #define CAN_MO_MOSTAT_TXRQ_Msk (0x100UL)
12255 #define CAN_MO_MOSTAT_TXEN0_Pos (9UL)
12256 #define CAN_MO_MOSTAT_TXEN0_Msk (0x200UL)
12257 #define CAN_MO_MOSTAT_TXEN1_Pos (10UL)
12258 #define CAN_MO_MOSTAT_TXEN1_Msk (0x400UL)
12259 #define CAN_MO_MOSTAT_DIR_Pos (11UL)
12260 #define CAN_MO_MOSTAT_DIR_Msk (0x800UL)
12261 #define CAN_MO_MOSTAT_LIST_Pos (12UL)
12262 #define CAN_MO_MOSTAT_LIST_Msk (0xf000UL)
12263 #define CAN_MO_MOSTAT_PPREV_Pos (16UL)
12264 #define CAN_MO_MOSTAT_PPREV_Msk (0xff0000UL)
12265 #define CAN_MO_MOSTAT_PNEXT_Pos (24UL)
12266 #define CAN_MO_MOSTAT_PNEXT_Msk (0xff000000UL)
12269 /* ================================================================================ */
12270 /* ================ struct 'VADC' Position & Mask ================ */
12271 /* ================================================================================ */
12272 
12273 
12274 /* ---------------------------------- VADC_CLC ---------------------------------- */
12275 #define VADC_CLC_DISR_Pos (0UL)
12276 #define VADC_CLC_DISR_Msk (0x1UL)
12277 #define VADC_CLC_DISS_Pos (1UL)
12278 #define VADC_CLC_DISS_Msk (0x2UL)
12279 #define VADC_CLC_EDIS_Pos (3UL)
12280 #define VADC_CLC_EDIS_Msk (0x8UL)
12282 /* ----------------------------------- VADC_ID ---------------------------------- */
12283 #define VADC_ID_MOD_REV_Pos (0UL)
12284 #define VADC_ID_MOD_REV_Msk (0xffUL)
12285 #define VADC_ID_MOD_TYPE_Pos (8UL)
12286 #define VADC_ID_MOD_TYPE_Msk (0xff00UL)
12287 #define VADC_ID_MOD_NUMBER_Pos (16UL)
12288 #define VADC_ID_MOD_NUMBER_Msk (0xffff0000UL)
12290 /* ---------------------------------- VADC_OCS ---------------------------------- */
12291 #define VADC_OCS_TGS_Pos (0UL)
12292 #define VADC_OCS_TGS_Msk (0x3UL)
12293 #define VADC_OCS_TGB_Pos (2UL)
12294 #define VADC_OCS_TGB_Msk (0x4UL)
12295 #define VADC_OCS_TG_P_Pos (3UL)
12296 #define VADC_OCS_TG_P_Msk (0x8UL)
12297 #define VADC_OCS_SUS_Pos (24UL)
12298 #define VADC_OCS_SUS_Msk (0xf000000UL)
12299 #define VADC_OCS_SUS_P_Pos (28UL)
12300 #define VADC_OCS_SUS_P_Msk (0x10000000UL)
12301 #define VADC_OCS_SUSSTA_Pos (29UL)
12302 #define VADC_OCS_SUSSTA_Msk (0x20000000UL)
12304 /* -------------------------------- VADC_GLOBCFG -------------------------------- */
12305 #define VADC_GLOBCFG_DIVA_Pos (0UL)
12306 #define VADC_GLOBCFG_DIVA_Msk (0x1fUL)
12307 #define VADC_GLOBCFG_DCMSB_Pos (7UL)
12308 #define VADC_GLOBCFG_DCMSB_Msk (0x80UL)
12309 #define VADC_GLOBCFG_DIVD_Pos (8UL)
12310 #define VADC_GLOBCFG_DIVD_Msk (0x300UL)
12311 #define VADC_GLOBCFG_DIVWC_Pos (15UL)
12312 #define VADC_GLOBCFG_DIVWC_Msk (0x8000UL)
12313 #define VADC_GLOBCFG_DPCAL0_Pos (16UL)
12314 #define VADC_GLOBCFG_DPCAL0_Msk (0x10000UL)
12315 #define VADC_GLOBCFG_DPCAL1_Pos (17UL)
12316 #define VADC_GLOBCFG_DPCAL1_Msk (0x20000UL)
12317 #define VADC_GLOBCFG_DPCAL2_Pos (18UL)
12318 #define VADC_GLOBCFG_DPCAL2_Msk (0x40000UL)
12319 #define VADC_GLOBCFG_DPCAL3_Pos (19UL)
12320 #define VADC_GLOBCFG_DPCAL3_Msk (0x80000UL)
12321 #define VADC_GLOBCFG_SUCAL_Pos (31UL)
12322 #define VADC_GLOBCFG_SUCAL_Msk (0x80000000UL)
12324 /* ------------------------------- VADC_GLOBICLASS ------------------------------ */
12325 #define VADC_GLOBICLASS_STCS_Pos (0UL)
12326 #define VADC_GLOBICLASS_STCS_Msk (0x1fUL)
12327 #define VADC_GLOBICLASS_CMS_Pos (8UL)
12328 #define VADC_GLOBICLASS_CMS_Msk (0x700UL)
12329 #define VADC_GLOBICLASS_STCE_Pos (16UL)
12330 #define VADC_GLOBICLASS_STCE_Msk (0x1f0000UL)
12331 #define VADC_GLOBICLASS_CME_Pos (24UL)
12332 #define VADC_GLOBICLASS_CME_Msk (0x7000000UL)
12334 /* ------------------------------- VADC_GLOBBOUND ------------------------------- */
12335 #define VADC_GLOBBOUND_BOUNDARY0_Pos (0UL)
12336 #define VADC_GLOBBOUND_BOUNDARY0_Msk (0xfffUL)
12337 #define VADC_GLOBBOUND_BOUNDARY1_Pos (16UL)
12338 #define VADC_GLOBBOUND_BOUNDARY1_Msk (0xfff0000UL)
12340 /* ------------------------------- VADC_GLOBEFLAG ------------------------------- */
12341 #define VADC_GLOBEFLAG_SEVGLB_Pos (0UL)
12342 #define VADC_GLOBEFLAG_SEVGLB_Msk (0x1UL)
12343 #define VADC_GLOBEFLAG_REVGLB_Pos (8UL)
12344 #define VADC_GLOBEFLAG_REVGLB_Msk (0x100UL)
12345 #define VADC_GLOBEFLAG_SEVGLBCLR_Pos (16UL)
12346 #define VADC_GLOBEFLAG_SEVGLBCLR_Msk (0x10000UL)
12347 #define VADC_GLOBEFLAG_REVGLBCLR_Pos (24UL)
12348 #define VADC_GLOBEFLAG_REVGLBCLR_Msk (0x1000000UL)
12350 /* -------------------------------- VADC_GLOBEVNP ------------------------------- */
12351 #define VADC_GLOBEVNP_SEV0NP_Pos (0UL)
12352 #define VADC_GLOBEVNP_SEV0NP_Msk (0xfUL)
12353 #define VADC_GLOBEVNP_REV0NP_Pos (16UL)
12354 #define VADC_GLOBEVNP_REV0NP_Msk (0xf0000UL)
12356 /* --------------------------------- VADC_GLOBTF -------------------------------- */
12357 #define VADC_GLOBTF_CDGR_Pos (4UL)
12358 #define VADC_GLOBTF_CDGR_Msk (0xf0UL)
12359 #define VADC_GLOBTF_CDEN_Pos (8UL)
12360 #define VADC_GLOBTF_CDEN_Msk (0x100UL)
12361 #define VADC_GLOBTF_CDSEL_Pos (9UL)
12362 #define VADC_GLOBTF_CDSEL_Msk (0x600UL)
12363 #define VADC_GLOBTF_CDWC_Pos (15UL)
12364 #define VADC_GLOBTF_CDWC_Msk (0x8000UL)
12365 #define VADC_GLOBTF_PDD_Pos (16UL)
12366 #define VADC_GLOBTF_PDD_Msk (0x10000UL)
12367 #define VADC_GLOBTF_MDWC_Pos (23UL)
12368 #define VADC_GLOBTF_MDWC_Msk (0x800000UL)
12370 /* --------------------------------- VADC_BRSSEL -------------------------------- */
12371 #define VADC_BRSSEL_CHSELG0_Pos (0UL)
12372 #define VADC_BRSSEL_CHSELG0_Msk (0x1UL)
12373 #define VADC_BRSSEL_CHSELG1_Pos (1UL)
12374 #define VADC_BRSSEL_CHSELG1_Msk (0x2UL)
12375 #define VADC_BRSSEL_CHSELG2_Pos (2UL)
12376 #define VADC_BRSSEL_CHSELG2_Msk (0x4UL)
12377 #define VADC_BRSSEL_CHSELG3_Pos (3UL)
12378 #define VADC_BRSSEL_CHSELG3_Msk (0x8UL)
12379 #define VADC_BRSSEL_CHSELG4_Pos (4UL)
12380 #define VADC_BRSSEL_CHSELG4_Msk (0x10UL)
12381 #define VADC_BRSSEL_CHSELG5_Pos (5UL)
12382 #define VADC_BRSSEL_CHSELG5_Msk (0x20UL)
12383 #define VADC_BRSSEL_CHSELG6_Pos (6UL)
12384 #define VADC_BRSSEL_CHSELG6_Msk (0x40UL)
12385 #define VADC_BRSSEL_CHSELG7_Pos (7UL)
12386 #define VADC_BRSSEL_CHSELG7_Msk (0x80UL)
12388 /* --------------------------------- VADC_BRSPND -------------------------------- */
12389 #define VADC_BRSPND_CHPNDG0_Pos (0UL)
12390 #define VADC_BRSPND_CHPNDG0_Msk (0x1UL)
12391 #define VADC_BRSPND_CHPNDG1_Pos (1UL)
12392 #define VADC_BRSPND_CHPNDG1_Msk (0x2UL)
12393 #define VADC_BRSPND_CHPNDG2_Pos (2UL)
12394 #define VADC_BRSPND_CHPNDG2_Msk (0x4UL)
12395 #define VADC_BRSPND_CHPNDG3_Pos (3UL)
12396 #define VADC_BRSPND_CHPNDG3_Msk (0x8UL)
12397 #define VADC_BRSPND_CHPNDG4_Pos (4UL)
12398 #define VADC_BRSPND_CHPNDG4_Msk (0x10UL)
12399 #define VADC_BRSPND_CHPNDG5_Pos (5UL)
12400 #define VADC_BRSPND_CHPNDG5_Msk (0x20UL)
12401 #define VADC_BRSPND_CHPNDG6_Pos (6UL)
12402 #define VADC_BRSPND_CHPNDG6_Msk (0x40UL)
12403 #define VADC_BRSPND_CHPNDG7_Pos (7UL)
12404 #define VADC_BRSPND_CHPNDG7_Msk (0x80UL)
12406 /* -------------------------------- VADC_BRSCTRL -------------------------------- */
12407 #define VADC_BRSCTRL_SRCRESREG_Pos (0UL)
12408 #define VADC_BRSCTRL_SRCRESREG_Msk (0xfUL)
12409 #define VADC_BRSCTRL_XTSEL_Pos (8UL)
12410 #define VADC_BRSCTRL_XTSEL_Msk (0xf00UL)
12411 #define VADC_BRSCTRL_XTLVL_Pos (12UL)
12412 #define VADC_BRSCTRL_XTLVL_Msk (0x1000UL)
12413 #define VADC_BRSCTRL_XTMODE_Pos (13UL)
12414 #define VADC_BRSCTRL_XTMODE_Msk (0x6000UL)
12415 #define VADC_BRSCTRL_XTWC_Pos (15UL)
12416 #define VADC_BRSCTRL_XTWC_Msk (0x8000UL)
12417 #define VADC_BRSCTRL_GTSEL_Pos (16UL)
12418 #define VADC_BRSCTRL_GTSEL_Msk (0xf0000UL)
12419 #define VADC_BRSCTRL_GTLVL_Pos (20UL)
12420 #define VADC_BRSCTRL_GTLVL_Msk (0x100000UL)
12421 #define VADC_BRSCTRL_GTWC_Pos (23UL)
12422 #define VADC_BRSCTRL_GTWC_Msk (0x800000UL)
12424 /* --------------------------------- VADC_BRSMR --------------------------------- */
12425 #define VADC_BRSMR_ENGT_Pos (0UL)
12426 #define VADC_BRSMR_ENGT_Msk (0x3UL)
12427 #define VADC_BRSMR_ENTR_Pos (2UL)
12428 #define VADC_BRSMR_ENTR_Msk (0x4UL)
12429 #define VADC_BRSMR_ENSI_Pos (3UL)
12430 #define VADC_BRSMR_ENSI_Msk (0x8UL)
12431 #define VADC_BRSMR_SCAN_Pos (4UL)
12432 #define VADC_BRSMR_SCAN_Msk (0x10UL)
12433 #define VADC_BRSMR_LDM_Pos (5UL)
12434 #define VADC_BRSMR_LDM_Msk (0x20UL)
12435 #define VADC_BRSMR_REQGT_Pos (7UL)
12436 #define VADC_BRSMR_REQGT_Msk (0x80UL)
12437 #define VADC_BRSMR_CLRPND_Pos (8UL)
12438 #define VADC_BRSMR_CLRPND_Msk (0x100UL)
12439 #define VADC_BRSMR_LDEV_Pos (9UL)
12440 #define VADC_BRSMR_LDEV_Msk (0x200UL)
12441 #define VADC_BRSMR_RPTDIS_Pos (16UL)
12442 #define VADC_BRSMR_RPTDIS_Msk (0x10000UL)
12444 /* -------------------------------- VADC_GLOBRCR -------------------------------- */
12445 #define VADC_GLOBRCR_DRCTR_Pos (16UL)
12446 #define VADC_GLOBRCR_DRCTR_Msk (0xf0000UL)
12447 #define VADC_GLOBRCR_WFR_Pos (24UL)
12448 #define VADC_GLOBRCR_WFR_Msk (0x1000000UL)
12449 #define VADC_GLOBRCR_SRGEN_Pos (31UL)
12450 #define VADC_GLOBRCR_SRGEN_Msk (0x80000000UL)
12452 /* -------------------------------- VADC_GLOBRES -------------------------------- */
12453 #define VADC_GLOBRES_RESULT_Pos (0UL)
12454 #define VADC_GLOBRES_RESULT_Msk (0xffffUL)
12455 #define VADC_GLOBRES_GNR_Pos (16UL)
12456 #define VADC_GLOBRES_GNR_Msk (0xf0000UL)
12457 #define VADC_GLOBRES_CHNR_Pos (20UL)
12458 #define VADC_GLOBRES_CHNR_Msk (0x1f00000UL)
12459 #define VADC_GLOBRES_EMUX_Pos (25UL)
12460 #define VADC_GLOBRES_EMUX_Msk (0xe000000UL)
12461 #define VADC_GLOBRES_CRS_Pos (28UL)
12462 #define VADC_GLOBRES_CRS_Msk (0x30000000UL)
12463 #define VADC_GLOBRES_FCR_Pos (30UL)
12464 #define VADC_GLOBRES_FCR_Msk (0x40000000UL)
12465 #define VADC_GLOBRES_VF_Pos (31UL)
12466 #define VADC_GLOBRES_VF_Msk (0x80000000UL)
12468 /* -------------------------------- VADC_GLOBRESD ------------------------------- */
12469 #define VADC_GLOBRESD_RESULT_Pos (0UL)
12470 #define VADC_GLOBRESD_RESULT_Msk (0xffffUL)
12471 #define VADC_GLOBRESD_GNR_Pos (16UL)
12472 #define VADC_GLOBRESD_GNR_Msk (0xf0000UL)
12473 #define VADC_GLOBRESD_CHNR_Pos (20UL)
12474 #define VADC_GLOBRESD_CHNR_Msk (0x1f00000UL)
12475 #define VADC_GLOBRESD_EMUX_Pos (25UL)
12476 #define VADC_GLOBRESD_EMUX_Msk (0xe000000UL)
12477 #define VADC_GLOBRESD_CRS_Pos (28UL)
12478 #define VADC_GLOBRESD_CRS_Msk (0x30000000UL)
12479 #define VADC_GLOBRESD_FCR_Pos (30UL)
12480 #define VADC_GLOBRESD_FCR_Msk (0x40000000UL)
12481 #define VADC_GLOBRESD_VF_Pos (31UL)
12482 #define VADC_GLOBRESD_VF_Msk (0x80000000UL)
12484 /* -------------------------------- VADC_EMUXSEL -------------------------------- */
12485 #define VADC_EMUXSEL_EMUXGRP0_Pos (0UL)
12486 #define VADC_EMUXSEL_EMUXGRP0_Msk (0xfUL)
12487 #define VADC_EMUXSEL_EMUXGRP1_Pos (4UL)
12488 #define VADC_EMUXSEL_EMUXGRP1_Msk (0xf0UL)
12491 /* ================================================================================ */
12492 /* ================ Group 'VADC_G' Position & Mask ================ */
12493 /* ================================================================================ */
12494 
12495 
12496 /* -------------------------------- VADC_G_ARBCFG ------------------------------- */
12497 #define VADC_G_ARBCFG_ANONC_Pos (0UL)
12498 #define VADC_G_ARBCFG_ANONC_Msk (0x3UL)
12499 #define VADC_G_ARBCFG_ARBRND_Pos (4UL)
12500 #define VADC_G_ARBCFG_ARBRND_Msk (0x30UL)
12501 #define VADC_G_ARBCFG_ARBM_Pos (7UL)
12502 #define VADC_G_ARBCFG_ARBM_Msk (0x80UL)
12503 #define VADC_G_ARBCFG_ANONS_Pos (16UL)
12504 #define VADC_G_ARBCFG_ANONS_Msk (0x30000UL)
12505 #define VADC_G_ARBCFG_CAL_Pos (28UL)
12506 #define VADC_G_ARBCFG_CAL_Msk (0x10000000UL)
12507 #define VADC_G_ARBCFG_BUSY_Pos (30UL)
12508 #define VADC_G_ARBCFG_BUSY_Msk (0x40000000UL)
12509 #define VADC_G_ARBCFG_SAMPLE_Pos (31UL)
12510 #define VADC_G_ARBCFG_SAMPLE_Msk (0x80000000UL)
12512 /* -------------------------------- VADC_G_ARBPR -------------------------------- */
12513 #define VADC_G_ARBPR_PRIO0_Pos (0UL)
12514 #define VADC_G_ARBPR_PRIO0_Msk (0x3UL)
12515 #define VADC_G_ARBPR_CSM0_Pos (3UL)
12516 #define VADC_G_ARBPR_CSM0_Msk (0x8UL)
12517 #define VADC_G_ARBPR_PRIO1_Pos (4UL)
12518 #define VADC_G_ARBPR_PRIO1_Msk (0x30UL)
12519 #define VADC_G_ARBPR_CSM1_Pos (7UL)
12520 #define VADC_G_ARBPR_CSM1_Msk (0x80UL)
12521 #define VADC_G_ARBPR_PRIO2_Pos (8UL)
12522 #define VADC_G_ARBPR_PRIO2_Msk (0x300UL)
12523 #define VADC_G_ARBPR_CSM2_Pos (11UL)
12524 #define VADC_G_ARBPR_CSM2_Msk (0x800UL)
12525 #define VADC_G_ARBPR_ASEN0_Pos (24UL)
12526 #define VADC_G_ARBPR_ASEN0_Msk (0x1000000UL)
12527 #define VADC_G_ARBPR_ASEN1_Pos (25UL)
12528 #define VADC_G_ARBPR_ASEN1_Msk (0x2000000UL)
12529 #define VADC_G_ARBPR_ASEN2_Pos (26UL)
12530 #define VADC_G_ARBPR_ASEN2_Msk (0x4000000UL)
12532 /* -------------------------------- VADC_G_CHASS -------------------------------- */
12533 #define VADC_G_CHASS_ASSCH0_Pos (0UL)
12534 #define VADC_G_CHASS_ASSCH0_Msk (0x1UL)
12535 #define VADC_G_CHASS_ASSCH1_Pos (1UL)
12536 #define VADC_G_CHASS_ASSCH1_Msk (0x2UL)
12537 #define VADC_G_CHASS_ASSCH2_Pos (2UL)
12538 #define VADC_G_CHASS_ASSCH2_Msk (0x4UL)
12539 #define VADC_G_CHASS_ASSCH3_Pos (3UL)
12540 #define VADC_G_CHASS_ASSCH3_Msk (0x8UL)
12541 #define VADC_G_CHASS_ASSCH4_Pos (4UL)
12542 #define VADC_G_CHASS_ASSCH4_Msk (0x10UL)
12543 #define VADC_G_CHASS_ASSCH5_Pos (5UL)
12544 #define VADC_G_CHASS_ASSCH5_Msk (0x20UL)
12545 #define VADC_G_CHASS_ASSCH6_Pos (6UL)
12546 #define VADC_G_CHASS_ASSCH6_Msk (0x40UL)
12547 #define VADC_G_CHASS_ASSCH7_Pos (7UL)
12548 #define VADC_G_CHASS_ASSCH7_Msk (0x80UL)
12550 /* -------------------------------- VADC_G_ICLASS ------------------------------- */
12551 #define VADC_G_ICLASS_STCS_Pos (0UL)
12552 #define VADC_G_ICLASS_STCS_Msk (0x1fUL)
12553 #define VADC_G_ICLASS_CMS_Pos (8UL)
12554 #define VADC_G_ICLASS_CMS_Msk (0x700UL)
12555 #define VADC_G_ICLASS_STCE_Pos (16UL)
12556 #define VADC_G_ICLASS_STCE_Msk (0x1f0000UL)
12557 #define VADC_G_ICLASS_CME_Pos (24UL)
12558 #define VADC_G_ICLASS_CME_Msk (0x7000000UL)
12560 /* -------------------------------- VADC_G_ALIAS -------------------------------- */
12561 #define VADC_G_ALIAS_ALIAS0_Pos (0UL)
12562 #define VADC_G_ALIAS_ALIAS0_Msk (0x1fUL)
12563 #define VADC_G_ALIAS_ALIAS1_Pos (8UL)
12564 #define VADC_G_ALIAS_ALIAS1_Msk (0x1f00UL)
12566 /* -------------------------------- VADC_G_BOUND -------------------------------- */
12567 #define VADC_G_BOUND_BOUNDARY0_Pos (0UL)
12568 #define VADC_G_BOUND_BOUNDARY0_Msk (0xfffUL)
12569 #define VADC_G_BOUND_BOUNDARY1_Pos (16UL)
12570 #define VADC_G_BOUND_BOUNDARY1_Msk (0xfff0000UL)
12572 /* -------------------------------- VADC_G_SYNCTR ------------------------------- */
12573 #define VADC_G_SYNCTR_STSEL_Pos (0UL)
12574 #define VADC_G_SYNCTR_STSEL_Msk (0x3UL)
12575 #define VADC_G_SYNCTR_EVALR1_Pos (4UL)
12576 #define VADC_G_SYNCTR_EVALR1_Msk (0x10UL)
12577 #define VADC_G_SYNCTR_EVALR2_Pos (5UL)
12578 #define VADC_G_SYNCTR_EVALR2_Msk (0x20UL)
12579 #define VADC_G_SYNCTR_EVALR3_Pos (6UL)
12580 #define VADC_G_SYNCTR_EVALR3_Msk (0x40UL)
12582 /* --------------------------------- VADC_G_BFL --------------------------------- */
12583 #define VADC_G_BFL_BFL0_Pos (0UL)
12584 #define VADC_G_BFL_BFL0_Msk (0x1UL)
12585 #define VADC_G_BFL_BFL1_Pos (1UL)
12586 #define VADC_G_BFL_BFL1_Msk (0x2UL)
12587 #define VADC_G_BFL_BFL2_Pos (2UL)
12588 #define VADC_G_BFL_BFL2_Msk (0x4UL)
12589 #define VADC_G_BFL_BFL3_Pos (3UL)
12590 #define VADC_G_BFL_BFL3_Msk (0x8UL)
12591 #define VADC_G_BFL_BFA0_Pos (8UL)
12592 #define VADC_G_BFL_BFA0_Msk (0x100UL)
12593 #define VADC_G_BFL_BFA1_Pos (9UL)
12594 #define VADC_G_BFL_BFA1_Msk (0x200UL)
12595 #define VADC_G_BFL_BFA2_Pos (10UL)
12596 #define VADC_G_BFL_BFA2_Msk (0x400UL)
12597 #define VADC_G_BFL_BFA3_Pos (11UL)
12598 #define VADC_G_BFL_BFA3_Msk (0x800UL)
12599 #define VADC_G_BFL_BFI0_Pos (16UL)
12600 #define VADC_G_BFL_BFI0_Msk (0x10000UL)
12601 #define VADC_G_BFL_BFI1_Pos (17UL)
12602 #define VADC_G_BFL_BFI1_Msk (0x20000UL)
12603 #define VADC_G_BFL_BFI2_Pos (18UL)
12604 #define VADC_G_BFL_BFI2_Msk (0x40000UL)
12605 #define VADC_G_BFL_BFI3_Pos (19UL)
12606 #define VADC_G_BFL_BFI3_Msk (0x80000UL)
12608 /* --------------------------------- VADC_G_BFLS -------------------------------- */
12609 #define VADC_G_BFLS_BFC0_Pos (0UL)
12610 #define VADC_G_BFLS_BFC0_Msk (0x1UL)
12611 #define VADC_G_BFLS_BFC1_Pos (1UL)
12612 #define VADC_G_BFLS_BFC1_Msk (0x2UL)
12613 #define VADC_G_BFLS_BFC2_Pos (2UL)
12614 #define VADC_G_BFLS_BFC2_Msk (0x4UL)
12615 #define VADC_G_BFLS_BFC3_Pos (3UL)
12616 #define VADC_G_BFLS_BFC3_Msk (0x8UL)
12617 #define VADC_G_BFLS_BFS0_Pos (16UL)
12618 #define VADC_G_BFLS_BFS0_Msk (0x10000UL)
12619 #define VADC_G_BFLS_BFS1_Pos (17UL)
12620 #define VADC_G_BFLS_BFS1_Msk (0x20000UL)
12621 #define VADC_G_BFLS_BFS2_Pos (18UL)
12622 #define VADC_G_BFLS_BFS2_Msk (0x40000UL)
12623 #define VADC_G_BFLS_BFS3_Pos (19UL)
12624 #define VADC_G_BFLS_BFS3_Msk (0x80000UL)
12626 /* --------------------------------- VADC_G_BFLC -------------------------------- */
12627 #define VADC_G_BFLC_BFM0_Pos (0UL)
12628 #define VADC_G_BFLC_BFM0_Msk (0xfUL)
12629 #define VADC_G_BFLC_BFM1_Pos (4UL)
12630 #define VADC_G_BFLC_BFM1_Msk (0xf0UL)
12631 #define VADC_G_BFLC_BFM2_Pos (8UL)
12632 #define VADC_G_BFLC_BFM2_Msk (0xf00UL)
12633 #define VADC_G_BFLC_BFM3_Pos (12UL)
12634 #define VADC_G_BFLC_BFM3_Msk (0xf000UL)
12636 /* -------------------------------- VADC_G_BFLNP -------------------------------- */
12637 #define VADC_G_BFLNP_BFL0NP_Pos (0UL)
12638 #define VADC_G_BFLNP_BFL0NP_Msk (0xfUL)
12639 #define VADC_G_BFLNP_BFL1NP_Pos (4UL)
12640 #define VADC_G_BFLNP_BFL1NP_Msk (0xf0UL)
12641 #define VADC_G_BFLNP_BFL2NP_Pos (8UL)
12642 #define VADC_G_BFLNP_BFL2NP_Msk (0xf00UL)
12643 #define VADC_G_BFLNP_BFL3NP_Pos (12UL)
12644 #define VADC_G_BFLNP_BFL3NP_Msk (0xf000UL)
12646 /* -------------------------------- VADC_G_QCTRL0 ------------------------------- */
12647 #define VADC_G_QCTRL0_SRCRESREG_Pos (0UL)
12648 #define VADC_G_QCTRL0_SRCRESREG_Msk (0xfUL)
12649 #define VADC_G_QCTRL0_XTSEL_Pos (8UL)
12650 #define VADC_G_QCTRL0_XTSEL_Msk (0xf00UL)
12651 #define VADC_G_QCTRL0_XTLVL_Pos (12UL)
12652 #define VADC_G_QCTRL0_XTLVL_Msk (0x1000UL)
12653 #define VADC_G_QCTRL0_XTMODE_Pos (13UL)
12654 #define VADC_G_QCTRL0_XTMODE_Msk (0x6000UL)
12655 #define VADC_G_QCTRL0_XTWC_Pos (15UL)
12656 #define VADC_G_QCTRL0_XTWC_Msk (0x8000UL)
12657 #define VADC_G_QCTRL0_GTSEL_Pos (16UL)
12658 #define VADC_G_QCTRL0_GTSEL_Msk (0xf0000UL)
12659 #define VADC_G_QCTRL0_GTLVL_Pos (20UL)
12660 #define VADC_G_QCTRL0_GTLVL_Msk (0x100000UL)
12661 #define VADC_G_QCTRL0_GTWC_Pos (23UL)
12662 #define VADC_G_QCTRL0_GTWC_Msk (0x800000UL)
12663 #define VADC_G_QCTRL0_TMEN_Pos (28UL)
12664 #define VADC_G_QCTRL0_TMEN_Msk (0x10000000UL)
12665 #define VADC_G_QCTRL0_TMWC_Pos (31UL)
12666 #define VADC_G_QCTRL0_TMWC_Msk (0x80000000UL)
12668 /* --------------------------------- VADC_G_QMR0 -------------------------------- */
12669 #define VADC_G_QMR0_ENGT_Pos (0UL)
12670 #define VADC_G_QMR0_ENGT_Msk (0x3UL)
12671 #define VADC_G_QMR0_ENTR_Pos (2UL)
12672 #define VADC_G_QMR0_ENTR_Msk (0x4UL)
12673 #define VADC_G_QMR0_CLRV_Pos (8UL)
12674 #define VADC_G_QMR0_CLRV_Msk (0x100UL)
12675 #define VADC_G_QMR0_TREV_Pos (9UL)
12676 #define VADC_G_QMR0_TREV_Msk (0x200UL)
12677 #define VADC_G_QMR0_FLUSH_Pos (10UL)
12678 #define VADC_G_QMR0_FLUSH_Msk (0x400UL)
12679 #define VADC_G_QMR0_CEV_Pos (11UL)
12680 #define VADC_G_QMR0_CEV_Msk (0x800UL)
12681 #define VADC_G_QMR0_RPTDIS_Pos (16UL)
12682 #define VADC_G_QMR0_RPTDIS_Msk (0x10000UL)
12684 /* --------------------------------- VADC_G_QSR0 -------------------------------- */
12685 #define VADC_G_QSR0_FILL_Pos (0UL)
12686 #define VADC_G_QSR0_FILL_Msk (0xfUL)
12687 #define VADC_G_QSR0_EMPTY_Pos (5UL)
12688 #define VADC_G_QSR0_EMPTY_Msk (0x20UL)
12689 #define VADC_G_QSR0_REQGT_Pos (7UL)
12690 #define VADC_G_QSR0_REQGT_Msk (0x80UL)
12691 #define VADC_G_QSR0_EV_Pos (8UL)
12692 #define VADC_G_QSR0_EV_Msk (0x100UL)
12694 /* --------------------------------- VADC_G_Q0R0 -------------------------------- */
12695 #define VADC_G_Q0R0_REQCHNR_Pos (0UL)
12696 #define VADC_G_Q0R0_REQCHNR_Msk (0x1fUL)
12697 #define VADC_G_Q0R0_RF_Pos (5UL)
12698 #define VADC_G_Q0R0_RF_Msk (0x20UL)
12699 #define VADC_G_Q0R0_ENSI_Pos (6UL)
12700 #define VADC_G_Q0R0_ENSI_Msk (0x40UL)
12701 #define VADC_G_Q0R0_EXTR_Pos (7UL)
12702 #define VADC_G_Q0R0_EXTR_Msk (0x80UL)
12703 #define VADC_G_Q0R0_V_Pos (8UL)
12704 #define VADC_G_Q0R0_V_Msk (0x100UL)
12706 /* -------------------------------- VADC_G_QINR0 -------------------------------- */
12707 #define VADC_G_QINR0_REQCHNR_Pos (0UL)
12708 #define VADC_G_QINR0_REQCHNR_Msk (0x1fUL)
12709 #define VADC_G_QINR0_RF_Pos (5UL)
12710 #define VADC_G_QINR0_RF_Msk (0x20UL)
12711 #define VADC_G_QINR0_ENSI_Pos (6UL)
12712 #define VADC_G_QINR0_ENSI_Msk (0x40UL)
12713 #define VADC_G_QINR0_EXTR_Pos (7UL)
12714 #define VADC_G_QINR0_EXTR_Msk (0x80UL)
12716 /* -------------------------------- VADC_G_QBUR0 -------------------------------- */
12717 #define VADC_G_QBUR0_REQCHNR_Pos (0UL)
12718 #define VADC_G_QBUR0_REQCHNR_Msk (0x1fUL)
12719 #define VADC_G_QBUR0_RF_Pos (5UL)
12720 #define VADC_G_QBUR0_RF_Msk (0x20UL)
12721 #define VADC_G_QBUR0_ENSI_Pos (6UL)
12722 #define VADC_G_QBUR0_ENSI_Msk (0x40UL)
12723 #define VADC_G_QBUR0_EXTR_Pos (7UL)
12724 #define VADC_G_QBUR0_EXTR_Msk (0x80UL)
12725 #define VADC_G_QBUR0_V_Pos (8UL)
12726 #define VADC_G_QBUR0_V_Msk (0x100UL)
12728 /* -------------------------------- VADC_G_ASCTRL ------------------------------- */
12729 #define VADC_G_ASCTRL_SRCRESREG_Pos (0UL)
12730 #define VADC_G_ASCTRL_SRCRESREG_Msk (0xfUL)
12731 #define VADC_G_ASCTRL_XTSEL_Pos (8UL)
12732 #define VADC_G_ASCTRL_XTSEL_Msk (0xf00UL)
12733 #define VADC_G_ASCTRL_XTLVL_Pos (12UL)
12734 #define VADC_G_ASCTRL_XTLVL_Msk (0x1000UL)
12735 #define VADC_G_ASCTRL_XTMODE_Pos (13UL)
12736 #define VADC_G_ASCTRL_XTMODE_Msk (0x6000UL)
12737 #define VADC_G_ASCTRL_XTWC_Pos (15UL)
12738 #define VADC_G_ASCTRL_XTWC_Msk (0x8000UL)
12739 #define VADC_G_ASCTRL_GTSEL_Pos (16UL)
12740 #define VADC_G_ASCTRL_GTSEL_Msk (0xf0000UL)
12741 #define VADC_G_ASCTRL_GTLVL_Pos (20UL)
12742 #define VADC_G_ASCTRL_GTLVL_Msk (0x100000UL)
12743 #define VADC_G_ASCTRL_GTWC_Pos (23UL)
12744 #define VADC_G_ASCTRL_GTWC_Msk (0x800000UL)
12745 #define VADC_G_ASCTRL_TMEN_Pos (28UL)
12746 #define VADC_G_ASCTRL_TMEN_Msk (0x10000000UL)
12747 #define VADC_G_ASCTRL_TMWC_Pos (31UL)
12748 #define VADC_G_ASCTRL_TMWC_Msk (0x80000000UL)
12750 /* --------------------------------- VADC_G_ASMR -------------------------------- */
12751 #define VADC_G_ASMR_ENGT_Pos (0UL)
12752 #define VADC_G_ASMR_ENGT_Msk (0x3UL)
12753 #define VADC_G_ASMR_ENTR_Pos (2UL)
12754 #define VADC_G_ASMR_ENTR_Msk (0x4UL)
12755 #define VADC_G_ASMR_ENSI_Pos (3UL)
12756 #define VADC_G_ASMR_ENSI_Msk (0x8UL)
12757 #define VADC_G_ASMR_SCAN_Pos (4UL)
12758 #define VADC_G_ASMR_SCAN_Msk (0x10UL)
12759 #define VADC_G_ASMR_LDM_Pos (5UL)
12760 #define VADC_G_ASMR_LDM_Msk (0x20UL)
12761 #define VADC_G_ASMR_REQGT_Pos (7UL)
12762 #define VADC_G_ASMR_REQGT_Msk (0x80UL)
12763 #define VADC_G_ASMR_CLRPND_Pos (8UL)
12764 #define VADC_G_ASMR_CLRPND_Msk (0x100UL)
12765 #define VADC_G_ASMR_LDEV_Pos (9UL)
12766 #define VADC_G_ASMR_LDEV_Msk (0x200UL)
12767 #define VADC_G_ASMR_RPTDIS_Pos (16UL)
12768 #define VADC_G_ASMR_RPTDIS_Msk (0x10000UL)
12770 /* -------------------------------- VADC_G_ASSEL -------------------------------- */
12771 #define VADC_G_ASSEL_CHSEL0_Pos (0UL)
12772 #define VADC_G_ASSEL_CHSEL0_Msk (0x1UL)
12773 #define VADC_G_ASSEL_CHSEL1_Pos (1UL)
12774 #define VADC_G_ASSEL_CHSEL1_Msk (0x2UL)
12775 #define VADC_G_ASSEL_CHSEL2_Pos (2UL)
12776 #define VADC_G_ASSEL_CHSEL2_Msk (0x4UL)
12777 #define VADC_G_ASSEL_CHSEL3_Pos (3UL)
12778 #define VADC_G_ASSEL_CHSEL3_Msk (0x8UL)
12779 #define VADC_G_ASSEL_CHSEL4_Pos (4UL)
12780 #define VADC_G_ASSEL_CHSEL4_Msk (0x10UL)
12781 #define VADC_G_ASSEL_CHSEL5_Pos (5UL)
12782 #define VADC_G_ASSEL_CHSEL5_Msk (0x20UL)
12783 #define VADC_G_ASSEL_CHSEL6_Pos (6UL)
12784 #define VADC_G_ASSEL_CHSEL6_Msk (0x40UL)
12785 #define VADC_G_ASSEL_CHSEL7_Pos (7UL)
12786 #define VADC_G_ASSEL_CHSEL7_Msk (0x80UL)
12788 /* -------------------------------- VADC_G_ASPND -------------------------------- */
12789 #define VADC_G_ASPND_CHPND0_Pos (0UL)
12790 #define VADC_G_ASPND_CHPND0_Msk (0x1UL)
12791 #define VADC_G_ASPND_CHPND1_Pos (1UL)
12792 #define VADC_G_ASPND_CHPND1_Msk (0x2UL)
12793 #define VADC_G_ASPND_CHPND2_Pos (2UL)
12794 #define VADC_G_ASPND_CHPND2_Msk (0x4UL)
12795 #define VADC_G_ASPND_CHPND3_Pos (3UL)
12796 #define VADC_G_ASPND_CHPND3_Msk (0x8UL)
12797 #define VADC_G_ASPND_CHPND4_Pos (4UL)
12798 #define VADC_G_ASPND_CHPND4_Msk (0x10UL)
12799 #define VADC_G_ASPND_CHPND5_Pos (5UL)
12800 #define VADC_G_ASPND_CHPND5_Msk (0x20UL)
12801 #define VADC_G_ASPND_CHPND6_Pos (6UL)
12802 #define VADC_G_ASPND_CHPND6_Msk (0x40UL)
12803 #define VADC_G_ASPND_CHPND7_Pos (7UL)
12804 #define VADC_G_ASPND_CHPND7_Msk (0x80UL)
12806 /* -------------------------------- VADC_G_CEFLAG ------------------------------- */
12807 #define VADC_G_CEFLAG_CEV0_Pos (0UL)
12808 #define VADC_G_CEFLAG_CEV0_Msk (0x1UL)
12809 #define VADC_G_CEFLAG_CEV1_Pos (1UL)
12810 #define VADC_G_CEFLAG_CEV1_Msk (0x2UL)
12811 #define VADC_G_CEFLAG_CEV2_Pos (2UL)
12812 #define VADC_G_CEFLAG_CEV2_Msk (0x4UL)
12813 #define VADC_G_CEFLAG_CEV3_Pos (3UL)
12814 #define VADC_G_CEFLAG_CEV3_Msk (0x8UL)
12815 #define VADC_G_CEFLAG_CEV4_Pos (4UL)
12816 #define VADC_G_CEFLAG_CEV4_Msk (0x10UL)
12817 #define VADC_G_CEFLAG_CEV5_Pos (5UL)
12818 #define VADC_G_CEFLAG_CEV5_Msk (0x20UL)
12819 #define VADC_G_CEFLAG_CEV6_Pos (6UL)
12820 #define VADC_G_CEFLAG_CEV6_Msk (0x40UL)
12821 #define VADC_G_CEFLAG_CEV7_Pos (7UL)
12822 #define VADC_G_CEFLAG_CEV7_Msk (0x80UL)
12824 /* -------------------------------- VADC_G_REFLAG ------------------------------- */
12825 #define VADC_G_REFLAG_REV0_Pos (0UL)
12826 #define VADC_G_REFLAG_REV0_Msk (0x1UL)
12827 #define VADC_G_REFLAG_REV1_Pos (1UL)
12828 #define VADC_G_REFLAG_REV1_Msk (0x2UL)
12829 #define VADC_G_REFLAG_REV2_Pos (2UL)
12830 #define VADC_G_REFLAG_REV2_Msk (0x4UL)
12831 #define VADC_G_REFLAG_REV3_Pos (3UL)
12832 #define VADC_G_REFLAG_REV3_Msk (0x8UL)
12833 #define VADC_G_REFLAG_REV4_Pos (4UL)
12834 #define VADC_G_REFLAG_REV4_Msk (0x10UL)
12835 #define VADC_G_REFLAG_REV5_Pos (5UL)
12836 #define VADC_G_REFLAG_REV5_Msk (0x20UL)
12837 #define VADC_G_REFLAG_REV6_Pos (6UL)
12838 #define VADC_G_REFLAG_REV6_Msk (0x40UL)
12839 #define VADC_G_REFLAG_REV7_Pos (7UL)
12840 #define VADC_G_REFLAG_REV7_Msk (0x80UL)
12841 #define VADC_G_REFLAG_REV8_Pos (8UL)
12842 #define VADC_G_REFLAG_REV8_Msk (0x100UL)
12843 #define VADC_G_REFLAG_REV9_Pos (9UL)
12844 #define VADC_G_REFLAG_REV9_Msk (0x200UL)
12845 #define VADC_G_REFLAG_REV10_Pos (10UL)
12846 #define VADC_G_REFLAG_REV10_Msk (0x400UL)
12847 #define VADC_G_REFLAG_REV11_Pos (11UL)
12848 #define VADC_G_REFLAG_REV11_Msk (0x800UL)
12849 #define VADC_G_REFLAG_REV12_Pos (12UL)
12850 #define VADC_G_REFLAG_REV12_Msk (0x1000UL)
12851 #define VADC_G_REFLAG_REV13_Pos (13UL)
12852 #define VADC_G_REFLAG_REV13_Msk (0x2000UL)
12853 #define VADC_G_REFLAG_REV14_Pos (14UL)
12854 #define VADC_G_REFLAG_REV14_Msk (0x4000UL)
12855 #define VADC_G_REFLAG_REV15_Pos (15UL)
12856 #define VADC_G_REFLAG_REV15_Msk (0x8000UL)
12858 /* -------------------------------- VADC_G_SEFLAG ------------------------------- */
12859 #define VADC_G_SEFLAG_SEV0_Pos (0UL)
12860 #define VADC_G_SEFLAG_SEV0_Msk (0x1UL)
12861 #define VADC_G_SEFLAG_SEV1_Pos (1UL)
12862 #define VADC_G_SEFLAG_SEV1_Msk (0x2UL)
12864 /* -------------------------------- VADC_G_CEFCLR ------------------------------- */
12865 #define VADC_G_CEFCLR_CEV0_Pos (0UL)
12866 #define VADC_G_CEFCLR_CEV0_Msk (0x1UL)
12867 #define VADC_G_CEFCLR_CEV1_Pos (1UL)
12868 #define VADC_G_CEFCLR_CEV1_Msk (0x2UL)
12869 #define VADC_G_CEFCLR_CEV2_Pos (2UL)
12870 #define VADC_G_CEFCLR_CEV2_Msk (0x4UL)
12871 #define VADC_G_CEFCLR_CEV3_Pos (3UL)
12872 #define VADC_G_CEFCLR_CEV3_Msk (0x8UL)
12873 #define VADC_G_CEFCLR_CEV4_Pos (4UL)
12874 #define VADC_G_CEFCLR_CEV4_Msk (0x10UL)
12875 #define VADC_G_CEFCLR_CEV5_Pos (5UL)
12876 #define VADC_G_CEFCLR_CEV5_Msk (0x20UL)
12877 #define VADC_G_CEFCLR_CEV6_Pos (6UL)
12878 #define VADC_G_CEFCLR_CEV6_Msk (0x40UL)
12879 #define VADC_G_CEFCLR_CEV7_Pos (7UL)
12880 #define VADC_G_CEFCLR_CEV7_Msk (0x80UL)
12882 /* -------------------------------- VADC_G_REFCLR ------------------------------- */
12883 #define VADC_G_REFCLR_REV0_Pos (0UL)
12884 #define VADC_G_REFCLR_REV0_Msk (0x1UL)
12885 #define VADC_G_REFCLR_REV1_Pos (1UL)
12886 #define VADC_G_REFCLR_REV1_Msk (0x2UL)
12887 #define VADC_G_REFCLR_REV2_Pos (2UL)
12888 #define VADC_G_REFCLR_REV2_Msk (0x4UL)
12889 #define VADC_G_REFCLR_REV3_Pos (3UL)
12890 #define VADC_G_REFCLR_REV3_Msk (0x8UL)
12891 #define VADC_G_REFCLR_REV4_Pos (4UL)
12892 #define VADC_G_REFCLR_REV4_Msk (0x10UL)
12893 #define VADC_G_REFCLR_REV5_Pos (5UL)
12894 #define VADC_G_REFCLR_REV5_Msk (0x20UL)
12895 #define VADC_G_REFCLR_REV6_Pos (6UL)
12896 #define VADC_G_REFCLR_REV6_Msk (0x40UL)
12897 #define VADC_G_REFCLR_REV7_Pos (7UL)
12898 #define VADC_G_REFCLR_REV7_Msk (0x80UL)
12899 #define VADC_G_REFCLR_REV8_Pos (8UL)
12900 #define VADC_G_REFCLR_REV8_Msk (0x100UL)
12901 #define VADC_G_REFCLR_REV9_Pos (9UL)
12902 #define VADC_G_REFCLR_REV9_Msk (0x200UL)
12903 #define VADC_G_REFCLR_REV10_Pos (10UL)
12904 #define VADC_G_REFCLR_REV10_Msk (0x400UL)
12905 #define VADC_G_REFCLR_REV11_Pos (11UL)
12906 #define VADC_G_REFCLR_REV11_Msk (0x800UL)
12907 #define VADC_G_REFCLR_REV12_Pos (12UL)
12908 #define VADC_G_REFCLR_REV12_Msk (0x1000UL)
12909 #define VADC_G_REFCLR_REV13_Pos (13UL)
12910 #define VADC_G_REFCLR_REV13_Msk (0x2000UL)
12911 #define VADC_G_REFCLR_REV14_Pos (14UL)
12912 #define VADC_G_REFCLR_REV14_Msk (0x4000UL)
12913 #define VADC_G_REFCLR_REV15_Pos (15UL)
12914 #define VADC_G_REFCLR_REV15_Msk (0x8000UL)
12916 /* -------------------------------- VADC_G_SEFCLR ------------------------------- */
12917 #define VADC_G_SEFCLR_SEV0_Pos (0UL)
12918 #define VADC_G_SEFCLR_SEV0_Msk (0x1UL)
12919 #define VADC_G_SEFCLR_SEV1_Pos (1UL)
12920 #define VADC_G_SEFCLR_SEV1_Msk (0x2UL)
12922 /* -------------------------------- VADC_G_CEVNP0 ------------------------------- */
12923 #define VADC_G_CEVNP0_CEV0NP_Pos (0UL)
12924 #define VADC_G_CEVNP0_CEV0NP_Msk (0xfUL)
12925 #define VADC_G_CEVNP0_CEV1NP_Pos (4UL)
12926 #define VADC_G_CEVNP0_CEV1NP_Msk (0xf0UL)
12927 #define VADC_G_CEVNP0_CEV2NP_Pos (8UL)
12928 #define VADC_G_CEVNP0_CEV2NP_Msk (0xf00UL)
12929 #define VADC_G_CEVNP0_CEV3NP_Pos (12UL)
12930 #define VADC_G_CEVNP0_CEV3NP_Msk (0xf000UL)
12931 #define VADC_G_CEVNP0_CEV4NP_Pos (16UL)
12932 #define VADC_G_CEVNP0_CEV4NP_Msk (0xf0000UL)
12933 #define VADC_G_CEVNP0_CEV5NP_Pos (20UL)
12934 #define VADC_G_CEVNP0_CEV5NP_Msk (0xf00000UL)
12935 #define VADC_G_CEVNP0_CEV6NP_Pos (24UL)
12936 #define VADC_G_CEVNP0_CEV6NP_Msk (0xf000000UL)
12937 #define VADC_G_CEVNP0_CEV7NP_Pos (28UL)
12938 #define VADC_G_CEVNP0_CEV7NP_Msk (0xf0000000UL)
12940 /* -------------------------------- VADC_G_REVNP0 ------------------------------- */
12941 #define VADC_G_REVNP0_REV0NP_Pos (0UL)
12942 #define VADC_G_REVNP0_REV0NP_Msk (0xfUL)
12943 #define VADC_G_REVNP0_REV1NP_Pos (4UL)
12944 #define VADC_G_REVNP0_REV1NP_Msk (0xf0UL)
12945 #define VADC_G_REVNP0_REV2NP_Pos (8UL)
12946 #define VADC_G_REVNP0_REV2NP_Msk (0xf00UL)
12947 #define VADC_G_REVNP0_REV3NP_Pos (12UL)
12948 #define VADC_G_REVNP0_REV3NP_Msk (0xf000UL)
12949 #define VADC_G_REVNP0_REV4NP_Pos (16UL)
12950 #define VADC_G_REVNP0_REV4NP_Msk (0xf0000UL)
12951 #define VADC_G_REVNP0_REV5NP_Pos (20UL)
12952 #define VADC_G_REVNP0_REV5NP_Msk (0xf00000UL)
12953 #define VADC_G_REVNP0_REV6NP_Pos (24UL)
12954 #define VADC_G_REVNP0_REV6NP_Msk (0xf000000UL)
12955 #define VADC_G_REVNP0_REV7NP_Pos (28UL)
12956 #define VADC_G_REVNP0_REV7NP_Msk (0xf0000000UL)
12958 /* -------------------------------- VADC_G_REVNP1 ------------------------------- */
12959 #define VADC_G_REVNP1_REV8NP_Pos (0UL)
12960 #define VADC_G_REVNP1_REV8NP_Msk (0xfUL)
12961 #define VADC_G_REVNP1_REV9NP_Pos (4UL)
12962 #define VADC_G_REVNP1_REV9NP_Msk (0xf0UL)
12963 #define VADC_G_REVNP1_REV10NP_Pos (8UL)
12964 #define VADC_G_REVNP1_REV10NP_Msk (0xf00UL)
12965 #define VADC_G_REVNP1_REV11NP_Pos (12UL)
12966 #define VADC_G_REVNP1_REV11NP_Msk (0xf000UL)
12967 #define VADC_G_REVNP1_REV12NP_Pos (16UL)
12968 #define VADC_G_REVNP1_REV12NP_Msk (0xf0000UL)
12969 #define VADC_G_REVNP1_REV13NP_Pos (20UL)
12970 #define VADC_G_REVNP1_REV13NP_Msk (0xf00000UL)
12971 #define VADC_G_REVNP1_REV14NP_Pos (24UL)
12972 #define VADC_G_REVNP1_REV14NP_Msk (0xf000000UL)
12973 #define VADC_G_REVNP1_REV15NP_Pos (28UL)
12974 #define VADC_G_REVNP1_REV15NP_Msk (0xf0000000UL)
12976 /* -------------------------------- VADC_G_SEVNP -------------------------------- */
12977 #define VADC_G_SEVNP_SEV0NP_Pos (0UL)
12978 #define VADC_G_SEVNP_SEV0NP_Msk (0xfUL)
12979 #define VADC_G_SEVNP_SEV1NP_Pos (4UL)
12980 #define VADC_G_SEVNP_SEV1NP_Msk (0xf0UL)
12982 /* -------------------------------- VADC_G_SRACT -------------------------------- */
12983 #define VADC_G_SRACT_AGSR0_Pos (0UL)
12984 #define VADC_G_SRACT_AGSR0_Msk (0x1UL)
12985 #define VADC_G_SRACT_AGSR1_Pos (1UL)
12986 #define VADC_G_SRACT_AGSR1_Msk (0x2UL)
12987 #define VADC_G_SRACT_AGSR2_Pos (2UL)
12988 #define VADC_G_SRACT_AGSR2_Msk (0x4UL)
12989 #define VADC_G_SRACT_AGSR3_Pos (3UL)
12990 #define VADC_G_SRACT_AGSR3_Msk (0x8UL)
12991 #define VADC_G_SRACT_ASSR0_Pos (8UL)
12992 #define VADC_G_SRACT_ASSR0_Msk (0x100UL)
12993 #define VADC_G_SRACT_ASSR1_Pos (9UL)
12994 #define VADC_G_SRACT_ASSR1_Msk (0x200UL)
12995 #define VADC_G_SRACT_ASSR2_Pos (10UL)
12996 #define VADC_G_SRACT_ASSR2_Msk (0x400UL)
12997 #define VADC_G_SRACT_ASSR3_Pos (11UL)
12998 #define VADC_G_SRACT_ASSR3_Msk (0x800UL)
13000 /* ------------------------------- VADC_G_EMUXCTR ------------------------------- */
13001 #define VADC_G_EMUXCTR_EMUXSET_Pos (0UL)
13002 #define VADC_G_EMUXCTR_EMUXSET_Msk (0x7UL)
13003 #define VADC_G_EMUXCTR_EMUXACT_Pos (8UL)
13004 #define VADC_G_EMUXCTR_EMUXACT_Msk (0x700UL)
13005 #define VADC_G_EMUXCTR_EMUXCH_Pos (16UL)
13006 #define VADC_G_EMUXCTR_EMUXCH_Msk (0x3ff0000UL)
13007 #define VADC_G_EMUXCTR_EMUXMODE_Pos (26UL)
13008 #define VADC_G_EMUXCTR_EMUXMODE_Msk (0xc000000UL)
13009 #define VADC_G_EMUXCTR_EMXCOD_Pos (28UL)
13010 #define VADC_G_EMUXCTR_EMXCOD_Msk (0x10000000UL)
13011 #define VADC_G_EMUXCTR_EMXST_Pos (29UL)
13012 #define VADC_G_EMUXCTR_EMXST_Msk (0x20000000UL)
13013 #define VADC_G_EMUXCTR_EMXCSS_Pos (30UL)
13014 #define VADC_G_EMUXCTR_EMXCSS_Msk (0x40000000UL)
13015 #define VADC_G_EMUXCTR_EMXWC_Pos (31UL)
13016 #define VADC_G_EMUXCTR_EMXWC_Msk (0x80000000UL)
13018 /* --------------------------------- VADC_G_VFR --------------------------------- */
13019 #define VADC_G_VFR_VF0_Pos (0UL)
13020 #define VADC_G_VFR_VF0_Msk (0x1UL)
13021 #define VADC_G_VFR_VF1_Pos (1UL)
13022 #define VADC_G_VFR_VF1_Msk (0x2UL)
13023 #define VADC_G_VFR_VF2_Pos (2UL)
13024 #define VADC_G_VFR_VF2_Msk (0x4UL)
13025 #define VADC_G_VFR_VF3_Pos (3UL)
13026 #define VADC_G_VFR_VF3_Msk (0x8UL)
13027 #define VADC_G_VFR_VF4_Pos (4UL)
13028 #define VADC_G_VFR_VF4_Msk (0x10UL)
13029 #define VADC_G_VFR_VF5_Pos (5UL)
13030 #define VADC_G_VFR_VF5_Msk (0x20UL)
13031 #define VADC_G_VFR_VF6_Pos (6UL)
13032 #define VADC_G_VFR_VF6_Msk (0x40UL)
13033 #define VADC_G_VFR_VF7_Pos (7UL)
13034 #define VADC_G_VFR_VF7_Msk (0x80UL)
13035 #define VADC_G_VFR_VF8_Pos (8UL)
13036 #define VADC_G_VFR_VF8_Msk (0x100UL)
13037 #define VADC_G_VFR_VF9_Pos (9UL)
13038 #define VADC_G_VFR_VF9_Msk (0x200UL)
13039 #define VADC_G_VFR_VF10_Pos (10UL)
13040 #define VADC_G_VFR_VF10_Msk (0x400UL)
13041 #define VADC_G_VFR_VF11_Pos (11UL)
13042 #define VADC_G_VFR_VF11_Msk (0x800UL)
13043 #define VADC_G_VFR_VF12_Pos (12UL)
13044 #define VADC_G_VFR_VF12_Msk (0x1000UL)
13045 #define VADC_G_VFR_VF13_Pos (13UL)
13046 #define VADC_G_VFR_VF13_Msk (0x2000UL)
13047 #define VADC_G_VFR_VF14_Pos (14UL)
13048 #define VADC_G_VFR_VF14_Msk (0x4000UL)
13049 #define VADC_G_VFR_VF15_Pos (15UL)
13050 #define VADC_G_VFR_VF15_Msk (0x8000UL)
13052 /* -------------------------------- VADC_G_CHCTR -------------------------------- */
13053 #define VADC_G_CHCTR_ICLSEL_Pos (0UL)
13054 #define VADC_G_CHCTR_ICLSEL_Msk (0x3UL)
13055 #define VADC_G_CHCTR_BNDSELL_Pos (4UL)
13056 #define VADC_G_CHCTR_BNDSELL_Msk (0x30UL)
13057 #define VADC_G_CHCTR_BNDSELU_Pos (6UL)
13058 #define VADC_G_CHCTR_BNDSELU_Msk (0xc0UL)
13059 #define VADC_G_CHCTR_CHEVMODE_Pos (8UL)
13060 #define VADC_G_CHCTR_CHEVMODE_Msk (0x300UL)
13061 #define VADC_G_CHCTR_SYNC_Pos (10UL)
13062 #define VADC_G_CHCTR_SYNC_Msk (0x400UL)
13063 #define VADC_G_CHCTR_REFSEL_Pos (11UL)
13064 #define VADC_G_CHCTR_REFSEL_Msk (0x800UL)
13065 #define VADC_G_CHCTR_RESREG_Pos (16UL)
13066 #define VADC_G_CHCTR_RESREG_Msk (0xf0000UL)
13067 #define VADC_G_CHCTR_RESTBS_Pos (20UL)
13068 #define VADC_G_CHCTR_RESTBS_Msk (0x100000UL)
13069 #define VADC_G_CHCTR_RESPOS_Pos (21UL)
13070 #define VADC_G_CHCTR_RESPOS_Msk (0x200000UL)
13071 #define VADC_G_CHCTR_BWDCH_Pos (28UL)
13072 #define VADC_G_CHCTR_BWDCH_Msk (0x30000000UL)
13073 #define VADC_G_CHCTR_BWDEN_Pos (30UL)
13074 #define VADC_G_CHCTR_BWDEN_Msk (0x40000000UL)
13076 /* --------------------------------- VADC_G_RCR --------------------------------- */
13077 #define VADC_G_RCR_DRCTR_Pos (16UL)
13078 #define VADC_G_RCR_DRCTR_Msk (0xf0000UL)
13079 #define VADC_G_RCR_DMM_Pos (20UL)
13080 #define VADC_G_RCR_DMM_Msk (0x300000UL)
13081 #define VADC_G_RCR_WFR_Pos (24UL)
13082 #define VADC_G_RCR_WFR_Msk (0x1000000UL)
13083 #define VADC_G_RCR_FEN_Pos (25UL)
13084 #define VADC_G_RCR_FEN_Msk (0x6000000UL)
13085 #define VADC_G_RCR_SRGEN_Pos (31UL)
13086 #define VADC_G_RCR_SRGEN_Msk (0x80000000UL)
13088 /* --------------------------------- VADC_G_RES --------------------------------- */
13089 #define VADC_G_RES_RESULT_Pos (0UL)
13090 #define VADC_G_RES_RESULT_Msk (0xffffUL)
13091 #define VADC_G_RES_DRC_Pos (16UL)
13092 #define VADC_G_RES_DRC_Msk (0xf0000UL)
13093 #define VADC_G_RES_CHNR_Pos (20UL)
13094 #define VADC_G_RES_CHNR_Msk (0x1f00000UL)
13095 #define VADC_G_RES_EMUX_Pos (25UL)
13096 #define VADC_G_RES_EMUX_Msk (0xe000000UL)
13097 #define VADC_G_RES_CRS_Pos (28UL)
13098 #define VADC_G_RES_CRS_Msk (0x30000000UL)
13099 #define VADC_G_RES_FCR_Pos (30UL)
13100 #define VADC_G_RES_FCR_Msk (0x40000000UL)
13101 #define VADC_G_RES_VF_Pos (31UL)
13102 #define VADC_G_RES_VF_Msk (0x80000000UL)
13104 /* --------------------------------- VADC_G_RESD -------------------------------- */
13105 #define VADC_G_RESD_RESULT_Pos (0UL)
13106 #define VADC_G_RESD_RESULT_Msk (0xffffUL)
13107 #define VADC_G_RESD_DRC_Pos (16UL)
13108 #define VADC_G_RESD_DRC_Msk (0xf0000UL)
13109 #define VADC_G_RESD_CHNR_Pos (20UL)
13110 #define VADC_G_RESD_CHNR_Msk (0x1f00000UL)
13111 #define VADC_G_RESD_EMUX_Pos (25UL)
13112 #define VADC_G_RESD_EMUX_Msk (0xe000000UL)
13113 #define VADC_G_RESD_CRS_Pos (28UL)
13114 #define VADC_G_RESD_CRS_Msk (0x30000000UL)
13115 #define VADC_G_RESD_FCR_Pos (30UL)
13116 #define VADC_G_RESD_FCR_Msk (0x40000000UL)
13117 #define VADC_G_RESD_VF_Pos (31UL)
13118 #define VADC_G_RESD_VF_Msk (0x80000000UL)
13121 /* ================================================================================ */
13122 /* ================ struct 'DSD' Position & Mask ================ */
13123 /* ================================================================================ */
13124 
13125 
13126 /* ----------------------------------- DSD_CLC ---------------------------------- */
13127 #define DSD_CLC_DISR_Pos (0UL)
13128 #define DSD_CLC_DISR_Msk (0x1UL)
13129 #define DSD_CLC_DISS_Pos (1UL)
13130 #define DSD_CLC_DISS_Msk (0x2UL)
13131 #define DSD_CLC_EDIS_Pos (3UL)
13132 #define DSD_CLC_EDIS_Msk (0x8UL)
13134 /* ----------------------------------- DSD_ID ----------------------------------- */
13135 #define DSD_ID_MOD_REV_Pos (0UL)
13136 #define DSD_ID_MOD_REV_Msk (0xffUL)
13137 #define DSD_ID_MOD_TYPE_Pos (8UL)
13138 #define DSD_ID_MOD_TYPE_Msk (0xff00UL)
13139 #define DSD_ID_MOD_NUMBER_Pos (16UL)
13140 #define DSD_ID_MOD_NUMBER_Msk (0xffff0000UL)
13142 /* ----------------------------------- DSD_OCS ---------------------------------- */
13143 #define DSD_OCS_SUS_Pos (24UL)
13144 #define DSD_OCS_SUS_Msk (0xf000000UL)
13145 #define DSD_OCS_SUS_P_Pos (28UL)
13146 #define DSD_OCS_SUS_P_Msk (0x10000000UL)
13147 #define DSD_OCS_SUSSTA_Pos (29UL)
13148 #define DSD_OCS_SUSSTA_Msk (0x20000000UL)
13150 /* --------------------------------- DSD_GLOBCFG -------------------------------- */
13151 #define DSD_GLOBCFG_MCSEL_Pos (0UL)
13152 #define DSD_GLOBCFG_MCSEL_Msk (0x7UL)
13154 /* --------------------------------- DSD_GLOBRC --------------------------------- */
13155 #define DSD_GLOBRC_CH0RUN_Pos (0UL)
13156 #define DSD_GLOBRC_CH0RUN_Msk (0x1UL)
13157 #define DSD_GLOBRC_CH1RUN_Pos (1UL)
13158 #define DSD_GLOBRC_CH1RUN_Msk (0x2UL)
13159 #define DSD_GLOBRC_CH2RUN_Pos (2UL)
13160 #define DSD_GLOBRC_CH2RUN_Msk (0x4UL)
13161 #define DSD_GLOBRC_CH3RUN_Pos (3UL)
13162 #define DSD_GLOBRC_CH3RUN_Msk (0x8UL)
13164 /* ---------------------------------- DSD_CGCFG --------------------------------- */
13165 #define DSD_CGCFG_CGMOD_Pos (0UL)
13166 #define DSD_CGCFG_CGMOD_Msk (0x3UL)
13167 #define DSD_CGCFG_BREV_Pos (2UL)
13168 #define DSD_CGCFG_BREV_Msk (0x4UL)
13169 #define DSD_CGCFG_SIGPOL_Pos (3UL)
13170 #define DSD_CGCFG_SIGPOL_Msk (0x8UL)
13171 #define DSD_CGCFG_DIVCG_Pos (4UL)
13172 #define DSD_CGCFG_DIVCG_Msk (0xf0UL)
13173 #define DSD_CGCFG_RUN_Pos (15UL)
13174 #define DSD_CGCFG_RUN_Msk (0x8000UL)
13175 #define DSD_CGCFG_BITCOUNT_Pos (16UL)
13176 #define DSD_CGCFG_BITCOUNT_Msk (0x1f0000UL)
13177 #define DSD_CGCFG_STEPCOUNT_Pos (24UL)
13178 #define DSD_CGCFG_STEPCOUNT_Msk (0xf000000UL)
13179 #define DSD_CGCFG_STEPS_Pos (28UL)
13180 #define DSD_CGCFG_STEPS_Msk (0x10000000UL)
13181 #define DSD_CGCFG_STEPD_Pos (29UL)
13182 #define DSD_CGCFG_STEPD_Msk (0x20000000UL)
13183 #define DSD_CGCFG_SGNCG_Pos (30UL)
13184 #define DSD_CGCFG_SGNCG_Msk (0x40000000UL)
13186 /* --------------------------------- DSD_EVFLAG --------------------------------- */
13187 #define DSD_EVFLAG_RESEV0_Pos (0UL)
13188 #define DSD_EVFLAG_RESEV0_Msk (0x1UL)
13189 #define DSD_EVFLAG_RESEV1_Pos (1UL)
13190 #define DSD_EVFLAG_RESEV1_Msk (0x2UL)
13191 #define DSD_EVFLAG_RESEV2_Pos (2UL)
13192 #define DSD_EVFLAG_RESEV2_Msk (0x4UL)
13193 #define DSD_EVFLAG_RESEV3_Pos (3UL)
13194 #define DSD_EVFLAG_RESEV3_Msk (0x8UL)
13195 #define DSD_EVFLAG_ALEV0_Pos (16UL)
13196 #define DSD_EVFLAG_ALEV0_Msk (0x10000UL)
13197 #define DSD_EVFLAG_ALEV1_Pos (17UL)
13198 #define DSD_EVFLAG_ALEV1_Msk (0x20000UL)
13199 #define DSD_EVFLAG_ALEV2_Pos (18UL)
13200 #define DSD_EVFLAG_ALEV2_Msk (0x40000UL)
13201 #define DSD_EVFLAG_ALEV3_Pos (19UL)
13202 #define DSD_EVFLAG_ALEV3_Msk (0x80000UL)
13204 /* -------------------------------- DSD_EVFLAGCLR ------------------------------- */
13205 #define DSD_EVFLAGCLR_RESEC0_Pos (0UL)
13206 #define DSD_EVFLAGCLR_RESEC0_Msk (0x1UL)
13207 #define DSD_EVFLAGCLR_RESEC1_Pos (1UL)
13208 #define DSD_EVFLAGCLR_RESEC1_Msk (0x2UL)
13209 #define DSD_EVFLAGCLR_RESEC2_Pos (2UL)
13210 #define DSD_EVFLAGCLR_RESEC2_Msk (0x4UL)
13211 #define DSD_EVFLAGCLR_RESEC3_Pos (3UL)
13212 #define DSD_EVFLAGCLR_RESEC3_Msk (0x8UL)
13213 #define DSD_EVFLAGCLR_ALEC0_Pos (16UL)
13214 #define DSD_EVFLAGCLR_ALEC0_Msk (0x10000UL)
13215 #define DSD_EVFLAGCLR_ALEC1_Pos (17UL)
13216 #define DSD_EVFLAGCLR_ALEC1_Msk (0x20000UL)
13217 #define DSD_EVFLAGCLR_ALEC2_Pos (18UL)
13218 #define DSD_EVFLAGCLR_ALEC2_Msk (0x40000UL)
13219 #define DSD_EVFLAGCLR_ALEC3_Pos (19UL)
13220 #define DSD_EVFLAGCLR_ALEC3_Msk (0x80000UL)
13223 /* ================================================================================ */
13224 /* ================ Group 'DSD_CH' Position & Mask ================ */
13225 /* ================================================================================ */
13226 
13227 
13228 /* -------------------------------- DSD_CH_MODCFG ------------------------------- */
13229 #define DSD_CH_MODCFG_DIVM_Pos (16UL)
13230 #define DSD_CH_MODCFG_DIVM_Msk (0xf0000UL)
13231 #define DSD_CH_MODCFG_DWC_Pos (23UL)
13232 #define DSD_CH_MODCFG_DWC_Msk (0x800000UL)
13234 /* -------------------------------- DSD_CH_DICFG -------------------------------- */
13235 #define DSD_CH_DICFG_DSRC_Pos (0UL)
13236 #define DSD_CH_DICFG_DSRC_Msk (0xfUL)
13237 #define DSD_CH_DICFG_DSWC_Pos (7UL)
13238 #define DSD_CH_DICFG_DSWC_Msk (0x80UL)
13239 #define DSD_CH_DICFG_ITRMODE_Pos (8UL)
13240 #define DSD_CH_DICFG_ITRMODE_Msk (0x300UL)
13241 #define DSD_CH_DICFG_TSTRMODE_Pos (10UL)
13242 #define DSD_CH_DICFG_TSTRMODE_Msk (0xc00UL)
13243 #define DSD_CH_DICFG_TRSEL_Pos (12UL)
13244 #define DSD_CH_DICFG_TRSEL_Msk (0x7000UL)
13245 #define DSD_CH_DICFG_TRWC_Pos (15UL)
13246 #define DSD_CH_DICFG_TRWC_Msk (0x8000UL)
13247 #define DSD_CH_DICFG_CSRC_Pos (16UL)
13248 #define DSD_CH_DICFG_CSRC_Msk (0xf0000UL)
13249 #define DSD_CH_DICFG_STROBE_Pos (20UL)
13250 #define DSD_CH_DICFG_STROBE_Msk (0xf00000UL)
13251 #define DSD_CH_DICFG_SCWC_Pos (31UL)
13252 #define DSD_CH_DICFG_SCWC_Msk (0x80000000UL)
13254 /* -------------------------------- DSD_CH_FCFGC -------------------------------- */
13255 #define DSD_CH_FCFGC_CFMDF_Pos (0UL)
13256 #define DSD_CH_FCFGC_CFMDF_Msk (0xffUL)
13257 #define DSD_CH_FCFGC_CFMC_Pos (8UL)
13258 #define DSD_CH_FCFGC_CFMC_Msk (0x300UL)
13259 #define DSD_CH_FCFGC_CFEN_Pos (10UL)
13260 #define DSD_CH_FCFGC_CFEN_Msk (0x400UL)
13261 #define DSD_CH_FCFGC_SRGM_Pos (14UL)
13262 #define DSD_CH_FCFGC_SRGM_Msk (0xc000UL)
13263 #define DSD_CH_FCFGC_CFMSV_Pos (16UL)
13264 #define DSD_CH_FCFGC_CFMSV_Msk (0xff0000UL)
13265 #define DSD_CH_FCFGC_CFMDCNT_Pos (24UL)
13266 #define DSD_CH_FCFGC_CFMDCNT_Msk (0xff000000UL)
13268 /* -------------------------------- DSD_CH_FCFGA -------------------------------- */
13269 #define DSD_CH_FCFGA_CFADF_Pos (0UL)
13270 #define DSD_CH_FCFGA_CFADF_Msk (0xffUL)
13271 #define DSD_CH_FCFGA_CFAC_Pos (8UL)
13272 #define DSD_CH_FCFGA_CFAC_Msk (0x300UL)
13273 #define DSD_CH_FCFGA_SRGA_Pos (10UL)
13274 #define DSD_CH_FCFGA_SRGA_Msk (0xc00UL)
13275 #define DSD_CH_FCFGA_ESEL_Pos (12UL)
13276 #define DSD_CH_FCFGA_ESEL_Msk (0x3000UL)
13277 #define DSD_CH_FCFGA_EGT_Pos (14UL)
13278 #define DSD_CH_FCFGA_EGT_Msk (0x4000UL)
13279 #define DSD_CH_FCFGA_CFADCNT_Pos (24UL)
13280 #define DSD_CH_FCFGA_CFADCNT_Msk (0xff000000UL)
13282 /* -------------------------------- DSD_CH_IWCTR -------------------------------- */
13283 #define DSD_CH_IWCTR_NVALCNT_Pos (0UL)
13284 #define DSD_CH_IWCTR_NVALCNT_Msk (0x3fUL)
13285 #define DSD_CH_IWCTR_INTEN_Pos (7UL)
13286 #define DSD_CH_IWCTR_INTEN_Msk (0x80UL)
13287 #define DSD_CH_IWCTR_REPCNT_Pos (8UL)
13288 #define DSD_CH_IWCTR_REPCNT_Msk (0xf00UL)
13289 #define DSD_CH_IWCTR_REPVAL_Pos (12UL)
13290 #define DSD_CH_IWCTR_REPVAL_Msk (0xf000UL)
13291 #define DSD_CH_IWCTR_NVALDIS_Pos (16UL)
13292 #define DSD_CH_IWCTR_NVALDIS_Msk (0x3f0000UL)
13293 #define DSD_CH_IWCTR_IWS_Pos (23UL)
13294 #define DSD_CH_IWCTR_IWS_Msk (0x800000UL)
13295 #define DSD_CH_IWCTR_NVALINT_Pos (24UL)
13296 #define DSD_CH_IWCTR_NVALINT_Msk (0x3f000000UL)
13298 /* ------------------------------- DSD_CH_BOUNDSEL ------------------------------ */
13299 #define DSD_CH_BOUNDSEL_BOUNDARYL_Pos (0UL)
13300 #define DSD_CH_BOUNDSEL_BOUNDARYL_Msk (0xffffUL)
13301 #define DSD_CH_BOUNDSEL_BOUNDARYU_Pos (16UL)
13302 #define DSD_CH_BOUNDSEL_BOUNDARYU_Msk (0xffff0000UL)
13304 /* --------------------------------- DSD_CH_RESM -------------------------------- */
13305 #define DSD_CH_RESM_RESULT_Pos (0UL)
13306 #define DSD_CH_RESM_RESULT_Msk (0xffffUL)
13308 /* --------------------------------- DSD_CH_OFFM -------------------------------- */
13309 #define DSD_CH_OFFM_OFFSET_Pos (0UL)
13310 #define DSD_CH_OFFM_OFFSET_Msk (0xffffUL)
13312 /* --------------------------------- DSD_CH_RESA -------------------------------- */
13313 #define DSD_CH_RESA_RESULT_Pos (0UL)
13314 #define DSD_CH_RESA_RESULT_Msk (0xffffUL)
13316 /* -------------------------------- DSD_CH_TSTMP -------------------------------- */
13317 #define DSD_CH_TSTMP_RESULT_Pos (0UL)
13318 #define DSD_CH_TSTMP_RESULT_Msk (0xffffUL)
13319 #define DSD_CH_TSTMP_CFMDCNT_Pos (16UL)
13320 #define DSD_CH_TSTMP_CFMDCNT_Msk (0xff0000UL)
13321 #define DSD_CH_TSTMP_NVALCNT_Pos (24UL)
13322 #define DSD_CH_TSTMP_NVALCNT_Msk (0x3f000000UL)
13324 /* -------------------------------- DSD_CH_CGSYNC ------------------------------- */
13325 #define DSD_CH_CGSYNC_SDCOUNT_Pos (0UL)
13326 #define DSD_CH_CGSYNC_SDCOUNT_Msk (0xffUL)
13327 #define DSD_CH_CGSYNC_SDCAP_Pos (8UL)
13328 #define DSD_CH_CGSYNC_SDCAP_Msk (0xff00UL)
13329 #define DSD_CH_CGSYNC_SDPOS_Pos (16UL)
13330 #define DSD_CH_CGSYNC_SDPOS_Msk (0xff0000UL)
13331 #define DSD_CH_CGSYNC_SDNEG_Pos (24UL)
13332 #define DSD_CH_CGSYNC_SDNEG_Msk (0xff000000UL)
13334 /* ------------------------------- DSD_CH_RECTCFG ------------------------------- */
13335 #define DSD_CH_RECTCFG_RFEN_Pos (0UL)
13336 #define DSD_CH_RECTCFG_RFEN_Msk (0x1UL)
13337 #define DSD_CH_RECTCFG_SSRC_Pos (4UL)
13338 #define DSD_CH_RECTCFG_SSRC_Msk (0x30UL)
13339 #define DSD_CH_RECTCFG_SDVAL_Pos (15UL)
13340 #define DSD_CH_RECTCFG_SDVAL_Msk (0x8000UL)
13341 #define DSD_CH_RECTCFG_SGNCS_Pos (30UL)
13342 #define DSD_CH_RECTCFG_SGNCS_Msk (0x40000000UL)
13343 #define DSD_CH_RECTCFG_SGND_Pos (31UL)
13344 #define DSD_CH_RECTCFG_SGND_Msk (0x80000000UL)
13347 /* ================================================================================ */
13348 /* ================ struct 'DAC' Position & Mask ================ */
13349 /* ================================================================================ */
13350 
13351 
13352 /* ----------------------------------- DAC_ID ----------------------------------- */
13353 #define DAC_ID_MODR_Pos (0UL)
13354 #define DAC_ID_MODR_Msk (0xffUL)
13355 #define DAC_ID_MODT_Pos (8UL)
13356 #define DAC_ID_MODT_Msk (0xff00UL)
13357 #define DAC_ID_MODN_Pos (16UL)
13358 #define DAC_ID_MODN_Msk (0xffff0000UL)
13360 /* -------------------------------- DAC_DAC0CFG0 -------------------------------- */
13361 #define DAC_DAC0CFG0_FREQ_Pos (0UL)
13362 #define DAC_DAC0CFG0_FREQ_Msk (0xfffffUL)
13363 #define DAC_DAC0CFG0_MODE_Pos (20UL)
13364 #define DAC_DAC0CFG0_MODE_Msk (0x700000UL)
13365 #define DAC_DAC0CFG0_SIGN_Pos (23UL)
13366 #define DAC_DAC0CFG0_SIGN_Msk (0x800000UL)
13367 #define DAC_DAC0CFG0_FIFOIND_Pos (24UL)
13368 #define DAC_DAC0CFG0_FIFOIND_Msk (0x3000000UL)
13369 #define DAC_DAC0CFG0_FIFOEMP_Pos (26UL)
13370 #define DAC_DAC0CFG0_FIFOEMP_Msk (0x4000000UL)
13371 #define DAC_DAC0CFG0_FIFOFUL_Pos (27UL)
13372 #define DAC_DAC0CFG0_FIFOFUL_Msk (0x8000000UL)
13373 #define DAC_DAC0CFG0_NEGATE_Pos (28UL)
13374 #define DAC_DAC0CFG0_NEGATE_Msk (0x10000000UL)
13375 #define DAC_DAC0CFG0_SIGNEN_Pos (29UL)
13376 #define DAC_DAC0CFG0_SIGNEN_Msk (0x20000000UL)
13377 #define DAC_DAC0CFG0_SREN_Pos (30UL)
13378 #define DAC_DAC0CFG0_SREN_Msk (0x40000000UL)
13379 #define DAC_DAC0CFG0_RUN_Pos (31UL)
13380 #define DAC_DAC0CFG0_RUN_Msk (0x80000000UL)
13382 /* -------------------------------- DAC_DAC0CFG1 -------------------------------- */
13383 #define DAC_DAC0CFG1_SCALE_Pos (0UL)
13384 #define DAC_DAC0CFG1_SCALE_Msk (0x7UL)
13385 #define DAC_DAC0CFG1_MULDIV_Pos (3UL)
13386 #define DAC_DAC0CFG1_MULDIV_Msk (0x8UL)
13387 #define DAC_DAC0CFG1_OFFS_Pos (4UL)
13388 #define DAC_DAC0CFG1_OFFS_Msk (0xff0UL)
13389 #define DAC_DAC0CFG1_TRIGSEL_Pos (12UL)
13390 #define DAC_DAC0CFG1_TRIGSEL_Msk (0x7000UL)
13391 #define DAC_DAC0CFG1_DATMOD_Pos (15UL)
13392 #define DAC_DAC0CFG1_DATMOD_Msk (0x8000UL)
13393 #define DAC_DAC0CFG1_SWTRIG_Pos (16UL)
13394 #define DAC_DAC0CFG1_SWTRIG_Msk (0x10000UL)
13395 #define DAC_DAC0CFG1_TRIGMOD_Pos (17UL)
13396 #define DAC_DAC0CFG1_TRIGMOD_Msk (0x60000UL)
13397 #define DAC_DAC0CFG1_ANACFG_Pos (19UL)
13398 #define DAC_DAC0CFG1_ANACFG_Msk (0xf80000UL)
13399 #define DAC_DAC0CFG1_ANAEN_Pos (24UL)
13400 #define DAC_DAC0CFG1_ANAEN_Msk (0x1000000UL)
13401 #define DAC_DAC0CFG1_REFCFGL_Pos (28UL)
13402 #define DAC_DAC0CFG1_REFCFGL_Msk (0xf0000000UL)
13404 /* -------------------------------- DAC_DAC1CFG0 -------------------------------- */
13405 #define DAC_DAC1CFG0_FREQ_Pos (0UL)
13406 #define DAC_DAC1CFG0_FREQ_Msk (0xfffffUL)
13407 #define DAC_DAC1CFG0_MODE_Pos (20UL)
13408 #define DAC_DAC1CFG0_MODE_Msk (0x700000UL)
13409 #define DAC_DAC1CFG0_SIGN_Pos (23UL)
13410 #define DAC_DAC1CFG0_SIGN_Msk (0x800000UL)
13411 #define DAC_DAC1CFG0_FIFOIND_Pos (24UL)
13412 #define DAC_DAC1CFG0_FIFOIND_Msk (0x3000000UL)
13413 #define DAC_DAC1CFG0_FIFOEMP_Pos (26UL)
13414 #define DAC_DAC1CFG0_FIFOEMP_Msk (0x4000000UL)
13415 #define DAC_DAC1CFG0_FIFOFUL_Pos (27UL)
13416 #define DAC_DAC1CFG0_FIFOFUL_Msk (0x8000000UL)
13417 #define DAC_DAC1CFG0_NEGATE_Pos (28UL)
13418 #define DAC_DAC1CFG0_NEGATE_Msk (0x10000000UL)
13419 #define DAC_DAC1CFG0_SIGNEN_Pos (29UL)
13420 #define DAC_DAC1CFG0_SIGNEN_Msk (0x20000000UL)
13421 #define DAC_DAC1CFG0_SREN_Pos (30UL)
13422 #define DAC_DAC1CFG0_SREN_Msk (0x40000000UL)
13423 #define DAC_DAC1CFG0_RUN_Pos (31UL)
13424 #define DAC_DAC1CFG0_RUN_Msk (0x80000000UL)
13426 /* -------------------------------- DAC_DAC1CFG1 -------------------------------- */
13427 #define DAC_DAC1CFG1_SCALE_Pos (0UL)
13428 #define DAC_DAC1CFG1_SCALE_Msk (0x7UL)
13429 #define DAC_DAC1CFG1_MULDIV_Pos (3UL)
13430 #define DAC_DAC1CFG1_MULDIV_Msk (0x8UL)
13431 #define DAC_DAC1CFG1_OFFS_Pos (4UL)
13432 #define DAC_DAC1CFG1_OFFS_Msk (0xff0UL)
13433 #define DAC_DAC1CFG1_TRIGSEL_Pos (12UL)
13434 #define DAC_DAC1CFG1_TRIGSEL_Msk (0x7000UL)
13435 #define DAC_DAC1CFG1_SWTRIG_Pos (16UL)
13436 #define DAC_DAC1CFG1_SWTRIG_Msk (0x10000UL)
13437 #define DAC_DAC1CFG1_TRIGMOD_Pos (17UL)
13438 #define DAC_DAC1CFG1_TRIGMOD_Msk (0x60000UL)
13439 #define DAC_DAC1CFG1_ANACFG_Pos (19UL)
13440 #define DAC_DAC1CFG1_ANACFG_Msk (0xf80000UL)
13441 #define DAC_DAC1CFG1_ANAEN_Pos (24UL)
13442 #define DAC_DAC1CFG1_ANAEN_Msk (0x1000000UL)
13443 #define DAC_DAC1CFG1_REFCFGH_Pos (28UL)
13444 #define DAC_DAC1CFG1_REFCFGH_Msk (0xf0000000UL)
13446 /* -------------------------------- DAC_DAC0DATA -------------------------------- */
13447 #define DAC_DAC0DATA_DATA0_Pos (0UL)
13448 #define DAC_DAC0DATA_DATA0_Msk (0xfffUL)
13450 /* -------------------------------- DAC_DAC1DATA -------------------------------- */
13451 #define DAC_DAC1DATA_DATA1_Pos (0UL)
13452 #define DAC_DAC1DATA_DATA1_Msk (0xfffUL)
13454 /* -------------------------------- DAC_DAC01DATA ------------------------------- */
13455 #define DAC_DAC01DATA_DATA0_Pos (0UL)
13456 #define DAC_DAC01DATA_DATA0_Msk (0xfffUL)
13457 #define DAC_DAC01DATA_DATA1_Pos (16UL)
13458 #define DAC_DAC01DATA_DATA1_Msk (0xfff0000UL)
13460 /* -------------------------------- DAC_DAC0PATL -------------------------------- */
13461 #define DAC_DAC0PATL_PAT0_Pos (0UL)
13462 #define DAC_DAC0PATL_PAT0_Msk (0x1fUL)
13463 #define DAC_DAC0PATL_PAT1_Pos (5UL)
13464 #define DAC_DAC0PATL_PAT1_Msk (0x3e0UL)
13465 #define DAC_DAC0PATL_PAT2_Pos (10UL)
13466 #define DAC_DAC0PATL_PAT2_Msk (0x7c00UL)
13467 #define DAC_DAC0PATL_PAT3_Pos (15UL)
13468 #define DAC_DAC0PATL_PAT3_Msk (0xf8000UL)
13469 #define DAC_DAC0PATL_PAT4_Pos (20UL)
13470 #define DAC_DAC0PATL_PAT4_Msk (0x1f00000UL)
13471 #define DAC_DAC0PATL_PAT5_Pos (25UL)
13472 #define DAC_DAC0PATL_PAT5_Msk (0x3e000000UL)
13474 /* -------------------------------- DAC_DAC0PATH -------------------------------- */
13475 #define DAC_DAC0PATH_PAT6_Pos (0UL)
13476 #define DAC_DAC0PATH_PAT6_Msk (0x1fUL)
13477 #define DAC_DAC0PATH_PAT7_Pos (5UL)
13478 #define DAC_DAC0PATH_PAT7_Msk (0x3e0UL)
13479 #define DAC_DAC0PATH_PAT8_Pos (10UL)
13480 #define DAC_DAC0PATH_PAT8_Msk (0x7c00UL)
13482 /* -------------------------------- DAC_DAC1PATL -------------------------------- */
13483 #define DAC_DAC1PATL_PAT0_Pos (0UL)
13484 #define DAC_DAC1PATL_PAT0_Msk (0x1fUL)
13485 #define DAC_DAC1PATL_PAT1_Pos (5UL)
13486 #define DAC_DAC1PATL_PAT1_Msk (0x3e0UL)
13487 #define DAC_DAC1PATL_PAT2_Pos (10UL)
13488 #define DAC_DAC1PATL_PAT2_Msk (0x7c00UL)
13489 #define DAC_DAC1PATL_PAT3_Pos (15UL)
13490 #define DAC_DAC1PATL_PAT3_Msk (0xf8000UL)
13491 #define DAC_DAC1PATL_PAT4_Pos (20UL)
13492 #define DAC_DAC1PATL_PAT4_Msk (0x1f00000UL)
13493 #define DAC_DAC1PATL_PAT5_Pos (25UL)
13494 #define DAC_DAC1PATL_PAT5_Msk (0x3e000000UL)
13496 /* -------------------------------- DAC_DAC1PATH -------------------------------- */
13497 #define DAC_DAC1PATH_PAT6_Pos (0UL)
13498 #define DAC_DAC1PATH_PAT6_Msk (0x1fUL)
13499 #define DAC_DAC1PATH_PAT7_Pos (5UL)
13500 #define DAC_DAC1PATH_PAT7_Msk (0x3e0UL)
13501 #define DAC_DAC1PATH_PAT8_Pos (10UL)
13502 #define DAC_DAC1PATH_PAT8_Msk (0x7c00UL)
13505 /* ================================================================================ */
13506 /* ================ Group 'CCU4' Position & Mask ================ */
13507 /* ================================================================================ */
13508 
13509 
13510 /* --------------------------------- CCU4_GCTRL --------------------------------- */
13511 #define CCU4_GCTRL_PRBC_Pos (0UL)
13512 #define CCU4_GCTRL_PRBC_Msk (0x7UL)
13513 #define CCU4_GCTRL_PCIS_Pos (4UL)
13514 #define CCU4_GCTRL_PCIS_Msk (0x30UL)
13515 #define CCU4_GCTRL_SUSCFG_Pos (8UL)
13516 #define CCU4_GCTRL_SUSCFG_Msk (0x300UL)
13517 #define CCU4_GCTRL_MSE0_Pos (10UL)
13518 #define CCU4_GCTRL_MSE0_Msk (0x400UL)
13519 #define CCU4_GCTRL_MSE1_Pos (11UL)
13520 #define CCU4_GCTRL_MSE1_Msk (0x800UL)
13521 #define CCU4_GCTRL_MSE2_Pos (12UL)
13522 #define CCU4_GCTRL_MSE2_Msk (0x1000UL)
13523 #define CCU4_GCTRL_MSE3_Pos (13UL)
13524 #define CCU4_GCTRL_MSE3_Msk (0x2000UL)
13525 #define CCU4_GCTRL_MSDE_Pos (14UL)
13526 #define CCU4_GCTRL_MSDE_Msk (0xc000UL)
13528 /* --------------------------------- CCU4_GSTAT --------------------------------- */
13529 #define CCU4_GSTAT_S0I_Pos (0UL)
13530 #define CCU4_GSTAT_S0I_Msk (0x1UL)
13531 #define CCU4_GSTAT_S1I_Pos (1UL)
13532 #define CCU4_GSTAT_S1I_Msk (0x2UL)
13533 #define CCU4_GSTAT_S2I_Pos (2UL)
13534 #define CCU4_GSTAT_S2I_Msk (0x4UL)
13535 #define CCU4_GSTAT_S3I_Pos (3UL)
13536 #define CCU4_GSTAT_S3I_Msk (0x8UL)
13537 #define CCU4_GSTAT_PRB_Pos (8UL)
13538 #define CCU4_GSTAT_PRB_Msk (0x100UL)
13540 /* --------------------------------- CCU4_GIDLS --------------------------------- */
13541 #define CCU4_GIDLS_SS0I_Pos (0UL)
13542 #define CCU4_GIDLS_SS0I_Msk (0x1UL)
13543 #define CCU4_GIDLS_SS1I_Pos (1UL)
13544 #define CCU4_GIDLS_SS1I_Msk (0x2UL)
13545 #define CCU4_GIDLS_SS2I_Pos (2UL)
13546 #define CCU4_GIDLS_SS2I_Msk (0x4UL)
13547 #define CCU4_GIDLS_SS3I_Pos (3UL)
13548 #define CCU4_GIDLS_SS3I_Msk (0x8UL)
13549 #define CCU4_GIDLS_CPRB_Pos (8UL)
13550 #define CCU4_GIDLS_CPRB_Msk (0x100UL)
13551 #define CCU4_GIDLS_PSIC_Pos (9UL)
13552 #define CCU4_GIDLS_PSIC_Msk (0x200UL)
13554 /* --------------------------------- CCU4_GIDLC --------------------------------- */
13555 #define CCU4_GIDLC_CS0I_Pos (0UL)
13556 #define CCU4_GIDLC_CS0I_Msk (0x1UL)
13557 #define CCU4_GIDLC_CS1I_Pos (1UL)
13558 #define CCU4_GIDLC_CS1I_Msk (0x2UL)
13559 #define CCU4_GIDLC_CS2I_Pos (2UL)
13560 #define CCU4_GIDLC_CS2I_Msk (0x4UL)
13561 #define CCU4_GIDLC_CS3I_Pos (3UL)
13562 #define CCU4_GIDLC_CS3I_Msk (0x8UL)
13563 #define CCU4_GIDLC_SPRB_Pos (8UL)
13564 #define CCU4_GIDLC_SPRB_Msk (0x100UL)
13566 /* ---------------------------------- CCU4_GCSS --------------------------------- */
13567 #define CCU4_GCSS_S0SE_Pos (0UL)
13568 #define CCU4_GCSS_S0SE_Msk (0x1UL)
13569 #define CCU4_GCSS_S0DSE_Pos (1UL)
13570 #define CCU4_GCSS_S0DSE_Msk (0x2UL)
13571 #define CCU4_GCSS_S0PSE_Pos (2UL)
13572 #define CCU4_GCSS_S0PSE_Msk (0x4UL)
13573 #define CCU4_GCSS_S1SE_Pos (4UL)
13574 #define CCU4_GCSS_S1SE_Msk (0x10UL)
13575 #define CCU4_GCSS_S1DSE_Pos (5UL)
13576 #define CCU4_GCSS_S1DSE_Msk (0x20UL)
13577 #define CCU4_GCSS_S1PSE_Pos (6UL)
13578 #define CCU4_GCSS_S1PSE_Msk (0x40UL)
13579 #define CCU4_GCSS_S2SE_Pos (8UL)
13580 #define CCU4_GCSS_S2SE_Msk (0x100UL)
13581 #define CCU4_GCSS_S2DSE_Pos (9UL)
13582 #define CCU4_GCSS_S2DSE_Msk (0x200UL)
13583 #define CCU4_GCSS_S2PSE_Pos (10UL)
13584 #define CCU4_GCSS_S2PSE_Msk (0x400UL)
13585 #define CCU4_GCSS_S3SE_Pos (12UL)
13586 #define CCU4_GCSS_S3SE_Msk (0x1000UL)
13587 #define CCU4_GCSS_S3DSE_Pos (13UL)
13588 #define CCU4_GCSS_S3DSE_Msk (0x2000UL)
13589 #define CCU4_GCSS_S3PSE_Pos (14UL)
13590 #define CCU4_GCSS_S3PSE_Msk (0x4000UL)
13591 #define CCU4_GCSS_S0STS_Pos (16UL)
13592 #define CCU4_GCSS_S0STS_Msk (0x10000UL)
13593 #define CCU4_GCSS_S1STS_Pos (17UL)
13594 #define CCU4_GCSS_S1STS_Msk (0x20000UL)
13595 #define CCU4_GCSS_S2STS_Pos (18UL)
13596 #define CCU4_GCSS_S2STS_Msk (0x40000UL)
13597 #define CCU4_GCSS_S3STS_Pos (19UL)
13598 #define CCU4_GCSS_S3STS_Msk (0x80000UL)
13600 /* ---------------------------------- CCU4_GCSC --------------------------------- */
13601 #define CCU4_GCSC_S0SC_Pos (0UL)
13602 #define CCU4_GCSC_S0SC_Msk (0x1UL)
13603 #define CCU4_GCSC_S0DSC_Pos (1UL)
13604 #define CCU4_GCSC_S0DSC_Msk (0x2UL)
13605 #define CCU4_GCSC_S0PSC_Pos (2UL)
13606 #define CCU4_GCSC_S0PSC_Msk (0x4UL)
13607 #define CCU4_GCSC_S1SC_Pos (4UL)
13608 #define CCU4_GCSC_S1SC_Msk (0x10UL)
13609 #define CCU4_GCSC_S1DSC_Pos (5UL)
13610 #define CCU4_GCSC_S1DSC_Msk (0x20UL)
13611 #define CCU4_GCSC_S1PSC_Pos (6UL)
13612 #define CCU4_GCSC_S1PSC_Msk (0x40UL)
13613 #define CCU4_GCSC_S2SC_Pos (8UL)
13614 #define CCU4_GCSC_S2SC_Msk (0x100UL)
13615 #define CCU4_GCSC_S2DSC_Pos (9UL)
13616 #define CCU4_GCSC_S2DSC_Msk (0x200UL)
13617 #define CCU4_GCSC_S2PSC_Pos (10UL)
13618 #define CCU4_GCSC_S2PSC_Msk (0x400UL)
13619 #define CCU4_GCSC_S3SC_Pos (12UL)
13620 #define CCU4_GCSC_S3SC_Msk (0x1000UL)
13621 #define CCU4_GCSC_S3DSC_Pos (13UL)
13622 #define CCU4_GCSC_S3DSC_Msk (0x2000UL)
13623 #define CCU4_GCSC_S3PSC_Pos (14UL)
13624 #define CCU4_GCSC_S3PSC_Msk (0x4000UL)
13625 #define CCU4_GCSC_S0STC_Pos (16UL)
13626 #define CCU4_GCSC_S0STC_Msk (0x10000UL)
13627 #define CCU4_GCSC_S1STC_Pos (17UL)
13628 #define CCU4_GCSC_S1STC_Msk (0x20000UL)
13629 #define CCU4_GCSC_S2STC_Pos (18UL)
13630 #define CCU4_GCSC_S2STC_Msk (0x40000UL)
13631 #define CCU4_GCSC_S3STC_Pos (19UL)
13632 #define CCU4_GCSC_S3STC_Msk (0x80000UL)
13634 /* ---------------------------------- CCU4_GCST --------------------------------- */
13635 #define CCU4_GCST_S0SS_Pos (0UL)
13636 #define CCU4_GCST_S0SS_Msk (0x1UL)
13637 #define CCU4_GCST_S0DSS_Pos (1UL)
13638 #define CCU4_GCST_S0DSS_Msk (0x2UL)
13639 #define CCU4_GCST_S0PSS_Pos (2UL)
13640 #define CCU4_GCST_S0PSS_Msk (0x4UL)
13641 #define CCU4_GCST_S1SS_Pos (4UL)
13642 #define CCU4_GCST_S1SS_Msk (0x10UL)
13643 #define CCU4_GCST_S1DSS_Pos (5UL)
13644 #define CCU4_GCST_S1DSS_Msk (0x20UL)
13645 #define CCU4_GCST_S1PSS_Pos (6UL)
13646 #define CCU4_GCST_S1PSS_Msk (0x40UL)
13647 #define CCU4_GCST_S2SS_Pos (8UL)
13648 #define CCU4_GCST_S2SS_Msk (0x100UL)
13649 #define CCU4_GCST_S2DSS_Pos (9UL)
13650 #define CCU4_GCST_S2DSS_Msk (0x200UL)
13651 #define CCU4_GCST_S2PSS_Pos (10UL)
13652 #define CCU4_GCST_S2PSS_Msk (0x400UL)
13653 #define CCU4_GCST_S3SS_Pos (12UL)
13654 #define CCU4_GCST_S3SS_Msk (0x1000UL)
13655 #define CCU4_GCST_S3DSS_Pos (13UL)
13656 #define CCU4_GCST_S3DSS_Msk (0x2000UL)
13657 #define CCU4_GCST_S3PSS_Pos (14UL)
13658 #define CCU4_GCST_S3PSS_Msk (0x4000UL)
13659 #define CCU4_GCST_CC40ST_Pos (16UL)
13660 #define CCU4_GCST_CC40ST_Msk (0x10000UL)
13661 #define CCU4_GCST_CC41ST_Pos (17UL)
13662 #define CCU4_GCST_CC41ST_Msk (0x20000UL)
13663 #define CCU4_GCST_CC42ST_Pos (18UL)
13664 #define CCU4_GCST_CC42ST_Msk (0x40000UL)
13665 #define CCU4_GCST_CC43ST_Pos (19UL)
13666 #define CCU4_GCST_CC43ST_Msk (0x80000UL)
13668 /* ---------------------------------- CCU4_MIDR --------------------------------- */
13669 #define CCU4_MIDR_MODR_Pos (0UL)
13670 #define CCU4_MIDR_MODR_Msk (0xffUL)
13671 #define CCU4_MIDR_MODT_Pos (8UL)
13672 #define CCU4_MIDR_MODT_Msk (0xff00UL)
13673 #define CCU4_MIDR_MODN_Pos (16UL)
13674 #define CCU4_MIDR_MODN_Msk (0xffff0000UL)
13677 /* ================================================================================ */
13678 /* ================ Group 'CCU4_CC4' Position & Mask ================ */
13679 /* ================================================================================ */
13680 
13681 
13682 /* -------------------------------- CCU4_CC4_INS -------------------------------- */
13683 #define CCU4_CC4_INS_EV0IS_Pos (0UL)
13684 #define CCU4_CC4_INS_EV0IS_Msk (0xfUL)
13685 #define CCU4_CC4_INS_EV1IS_Pos (4UL)
13686 #define CCU4_CC4_INS_EV1IS_Msk (0xf0UL)
13687 #define CCU4_CC4_INS_EV2IS_Pos (8UL)
13688 #define CCU4_CC4_INS_EV2IS_Msk (0xf00UL)
13689 #define CCU4_CC4_INS_EV0EM_Pos (16UL)
13690 #define CCU4_CC4_INS_EV0EM_Msk (0x30000UL)
13691 #define CCU4_CC4_INS_EV1EM_Pos (18UL)
13692 #define CCU4_CC4_INS_EV1EM_Msk (0xc0000UL)
13693 #define CCU4_CC4_INS_EV2EM_Pos (20UL)
13694 #define CCU4_CC4_INS_EV2EM_Msk (0x300000UL)
13695 #define CCU4_CC4_INS_EV0LM_Pos (22UL)
13696 #define CCU4_CC4_INS_EV0LM_Msk (0x400000UL)
13697 #define CCU4_CC4_INS_EV1LM_Pos (23UL)
13698 #define CCU4_CC4_INS_EV1LM_Msk (0x800000UL)
13699 #define CCU4_CC4_INS_EV2LM_Pos (24UL)
13700 #define CCU4_CC4_INS_EV2LM_Msk (0x1000000UL)
13701 #define CCU4_CC4_INS_LPF0M_Pos (25UL)
13702 #define CCU4_CC4_INS_LPF0M_Msk (0x6000000UL)
13703 #define CCU4_CC4_INS_LPF1M_Pos (27UL)
13704 #define CCU4_CC4_INS_LPF1M_Msk (0x18000000UL)
13705 #define CCU4_CC4_INS_LPF2M_Pos (29UL)
13706 #define CCU4_CC4_INS_LPF2M_Msk (0x60000000UL)
13708 /* -------------------------------- CCU4_CC4_CMC -------------------------------- */
13709 #define CCU4_CC4_CMC_STRTS_Pos (0UL)
13710 #define CCU4_CC4_CMC_STRTS_Msk (0x3UL)
13711 #define CCU4_CC4_CMC_ENDS_Pos (2UL)
13712 #define CCU4_CC4_CMC_ENDS_Msk (0xcUL)
13713 #define CCU4_CC4_CMC_CAP0S_Pos (4UL)
13714 #define CCU4_CC4_CMC_CAP0S_Msk (0x30UL)
13715 #define CCU4_CC4_CMC_CAP1S_Pos (6UL)
13716 #define CCU4_CC4_CMC_CAP1S_Msk (0xc0UL)
13717 #define CCU4_CC4_CMC_GATES_Pos (8UL)
13718 #define CCU4_CC4_CMC_GATES_Msk (0x300UL)
13719 #define CCU4_CC4_CMC_UDS_Pos (10UL)
13720 #define CCU4_CC4_CMC_UDS_Msk (0xc00UL)
13721 #define CCU4_CC4_CMC_LDS_Pos (12UL)
13722 #define CCU4_CC4_CMC_LDS_Msk (0x3000UL)
13723 #define CCU4_CC4_CMC_CNTS_Pos (14UL)
13724 #define CCU4_CC4_CMC_CNTS_Msk (0xc000UL)
13725 #define CCU4_CC4_CMC_OFS_Pos (16UL)
13726 #define CCU4_CC4_CMC_OFS_Msk (0x10000UL)
13727 #define CCU4_CC4_CMC_TS_Pos (17UL)
13728 #define CCU4_CC4_CMC_TS_Msk (0x20000UL)
13729 #define CCU4_CC4_CMC_MOS_Pos (18UL)
13730 #define CCU4_CC4_CMC_MOS_Msk (0xc0000UL)
13731 #define CCU4_CC4_CMC_TCE_Pos (20UL)
13732 #define CCU4_CC4_CMC_TCE_Msk (0x100000UL)
13734 /* -------------------------------- CCU4_CC4_TCST ------------------------------- */
13735 #define CCU4_CC4_TCST_TRB_Pos (0UL)
13736 #define CCU4_CC4_TCST_TRB_Msk (0x1UL)
13737 #define CCU4_CC4_TCST_CDIR_Pos (1UL)
13738 #define CCU4_CC4_TCST_CDIR_Msk (0x2UL)
13740 /* ------------------------------- CCU4_CC4_TCSET ------------------------------- */
13741 #define CCU4_CC4_TCSET_TRBS_Pos (0UL)
13742 #define CCU4_CC4_TCSET_TRBS_Msk (0x1UL)
13744 /* ------------------------------- CCU4_CC4_TCCLR ------------------------------- */
13745 #define CCU4_CC4_TCCLR_TRBC_Pos (0UL)
13746 #define CCU4_CC4_TCCLR_TRBC_Msk (0x1UL)
13747 #define CCU4_CC4_TCCLR_TCC_Pos (1UL)
13748 #define CCU4_CC4_TCCLR_TCC_Msk (0x2UL)
13749 #define CCU4_CC4_TCCLR_DITC_Pos (2UL)
13750 #define CCU4_CC4_TCCLR_DITC_Msk (0x4UL)
13752 /* --------------------------------- CCU4_CC4_TC -------------------------------- */
13753 #define CCU4_CC4_TC_TCM_Pos (0UL)
13754 #define CCU4_CC4_TC_TCM_Msk (0x1UL)
13755 #define CCU4_CC4_TC_TSSM_Pos (1UL)
13756 #define CCU4_CC4_TC_TSSM_Msk (0x2UL)
13757 #define CCU4_CC4_TC_CLST_Pos (2UL)
13758 #define CCU4_CC4_TC_CLST_Msk (0x4UL)
13759 #define CCU4_CC4_TC_CMOD_Pos (3UL)
13760 #define CCU4_CC4_TC_CMOD_Msk (0x8UL)
13761 #define CCU4_CC4_TC_ECM_Pos (4UL)
13762 #define CCU4_CC4_TC_ECM_Msk (0x10UL)
13763 #define CCU4_CC4_TC_CAPC_Pos (5UL)
13764 #define CCU4_CC4_TC_CAPC_Msk (0x60UL)
13765 #define CCU4_CC4_TC_ENDM_Pos (8UL)
13766 #define CCU4_CC4_TC_ENDM_Msk (0x300UL)
13767 #define CCU4_CC4_TC_STRM_Pos (10UL)
13768 #define CCU4_CC4_TC_STRM_Msk (0x400UL)
13769 #define CCU4_CC4_TC_SCE_Pos (11UL)
13770 #define CCU4_CC4_TC_SCE_Msk (0x800UL)
13771 #define CCU4_CC4_TC_CCS_Pos (12UL)
13772 #define CCU4_CC4_TC_CCS_Msk (0x1000UL)
13773 #define CCU4_CC4_TC_DITHE_Pos (13UL)
13774 #define CCU4_CC4_TC_DITHE_Msk (0x6000UL)
13775 #define CCU4_CC4_TC_DIM_Pos (15UL)
13776 #define CCU4_CC4_TC_DIM_Msk (0x8000UL)
13777 #define CCU4_CC4_TC_FPE_Pos (16UL)
13778 #define CCU4_CC4_TC_FPE_Msk (0x10000UL)
13779 #define CCU4_CC4_TC_TRAPE_Pos (17UL)
13780 #define CCU4_CC4_TC_TRAPE_Msk (0x20000UL)
13781 #define CCU4_CC4_TC_TRPSE_Pos (21UL)
13782 #define CCU4_CC4_TC_TRPSE_Msk (0x200000UL)
13783 #define CCU4_CC4_TC_TRPSW_Pos (22UL)
13784 #define CCU4_CC4_TC_TRPSW_Msk (0x400000UL)
13785 #define CCU4_CC4_TC_EMS_Pos (23UL)
13786 #define CCU4_CC4_TC_EMS_Msk (0x800000UL)
13787 #define CCU4_CC4_TC_EMT_Pos (24UL)
13788 #define CCU4_CC4_TC_EMT_Msk (0x1000000UL)
13789 #define CCU4_CC4_TC_MCME_Pos (25UL)
13790 #define CCU4_CC4_TC_MCME_Msk (0x2000000UL)
13792 /* -------------------------------- CCU4_CC4_PSL -------------------------------- */
13793 #define CCU4_CC4_PSL_PSL_Pos (0UL)
13794 #define CCU4_CC4_PSL_PSL_Msk (0x1UL)
13796 /* -------------------------------- CCU4_CC4_DIT -------------------------------- */
13797 #define CCU4_CC4_DIT_DCV_Pos (0UL)
13798 #define CCU4_CC4_DIT_DCV_Msk (0xfUL)
13799 #define CCU4_CC4_DIT_DCNT_Pos (8UL)
13800 #define CCU4_CC4_DIT_DCNT_Msk (0xf00UL)
13802 /* -------------------------------- CCU4_CC4_DITS ------------------------------- */
13803 #define CCU4_CC4_DITS_DCVS_Pos (0UL)
13804 #define CCU4_CC4_DITS_DCVS_Msk (0xfUL)
13806 /* -------------------------------- CCU4_CC4_PSC -------------------------------- */
13807 #define CCU4_CC4_PSC_PSIV_Pos (0UL)
13808 #define CCU4_CC4_PSC_PSIV_Msk (0xfUL)
13810 /* -------------------------------- CCU4_CC4_FPC -------------------------------- */
13811 #define CCU4_CC4_FPC_PCMP_Pos (0UL)
13812 #define CCU4_CC4_FPC_PCMP_Msk (0xfUL)
13813 #define CCU4_CC4_FPC_PVAL_Pos (8UL)
13814 #define CCU4_CC4_FPC_PVAL_Msk (0xf00UL)
13816 /* -------------------------------- CCU4_CC4_FPCS ------------------------------- */
13817 #define CCU4_CC4_FPCS_PCMP_Pos (0UL)
13818 #define CCU4_CC4_FPCS_PCMP_Msk (0xfUL)
13820 /* --------------------------------- CCU4_CC4_PR -------------------------------- */
13821 #define CCU4_CC4_PR_PR_Pos (0UL)
13822 #define CCU4_CC4_PR_PR_Msk (0xffffUL)
13824 /* -------------------------------- CCU4_CC4_PRS -------------------------------- */
13825 #define CCU4_CC4_PRS_PRS_Pos (0UL)
13826 #define CCU4_CC4_PRS_PRS_Msk (0xffffUL)
13828 /* --------------------------------- CCU4_CC4_CR -------------------------------- */
13829 #define CCU4_CC4_CR_CR_Pos (0UL)
13830 #define CCU4_CC4_CR_CR_Msk (0xffffUL)
13832 /* -------------------------------- CCU4_CC4_CRS -------------------------------- */
13833 #define CCU4_CC4_CRS_CRS_Pos (0UL)
13834 #define CCU4_CC4_CRS_CRS_Msk (0xffffUL)
13836 /* ------------------------------- CCU4_CC4_TIMER ------------------------------- */
13837 #define CCU4_CC4_TIMER_TVAL_Pos (0UL)
13838 #define CCU4_CC4_TIMER_TVAL_Msk (0xffffUL)
13840 /* --------------------------------- CCU4_CC4_CV -------------------------------- */
13841 #define CCU4_CC4_CV_CAPTV_Pos (0UL)
13842 #define CCU4_CC4_CV_CAPTV_Msk (0xffffUL)
13843 #define CCU4_CC4_CV_FPCV_Pos (16UL)
13844 #define CCU4_CC4_CV_FPCV_Msk (0xf0000UL)
13845 #define CCU4_CC4_CV_FFL_Pos (20UL)
13846 #define CCU4_CC4_CV_FFL_Msk (0x100000UL)
13848 /* -------------------------------- CCU4_CC4_INTS ------------------------------- */
13849 #define CCU4_CC4_INTS_PMUS_Pos (0UL)
13850 #define CCU4_CC4_INTS_PMUS_Msk (0x1UL)
13851 #define CCU4_CC4_INTS_OMDS_Pos (1UL)
13852 #define CCU4_CC4_INTS_OMDS_Msk (0x2UL)
13853 #define CCU4_CC4_INTS_CMUS_Pos (2UL)
13854 #define CCU4_CC4_INTS_CMUS_Msk (0x4UL)
13855 #define CCU4_CC4_INTS_CMDS_Pos (3UL)
13856 #define CCU4_CC4_INTS_CMDS_Msk (0x8UL)
13857 #define CCU4_CC4_INTS_E0AS_Pos (8UL)
13858 #define CCU4_CC4_INTS_E0AS_Msk (0x100UL)
13859 #define CCU4_CC4_INTS_E1AS_Pos (9UL)
13860 #define CCU4_CC4_INTS_E1AS_Msk (0x200UL)
13861 #define CCU4_CC4_INTS_E2AS_Pos (10UL)
13862 #define CCU4_CC4_INTS_E2AS_Msk (0x400UL)
13863 #define CCU4_CC4_INTS_TRPF_Pos (11UL)
13864 #define CCU4_CC4_INTS_TRPF_Msk (0x800UL)
13866 /* -------------------------------- CCU4_CC4_INTE ------------------------------- */
13867 #define CCU4_CC4_INTE_PME_Pos (0UL)
13868 #define CCU4_CC4_INTE_PME_Msk (0x1UL)
13869 #define CCU4_CC4_INTE_OME_Pos (1UL)
13870 #define CCU4_CC4_INTE_OME_Msk (0x2UL)
13871 #define CCU4_CC4_INTE_CMUE_Pos (2UL)
13872 #define CCU4_CC4_INTE_CMUE_Msk (0x4UL)
13873 #define CCU4_CC4_INTE_CMDE_Pos (3UL)
13874 #define CCU4_CC4_INTE_CMDE_Msk (0x8UL)
13875 #define CCU4_CC4_INTE_E0AE_Pos (8UL)
13876 #define CCU4_CC4_INTE_E0AE_Msk (0x100UL)
13877 #define CCU4_CC4_INTE_E1AE_Pos (9UL)
13878 #define CCU4_CC4_INTE_E1AE_Msk (0x200UL)
13879 #define CCU4_CC4_INTE_E2AE_Pos (10UL)
13880 #define CCU4_CC4_INTE_E2AE_Msk (0x400UL)
13882 /* -------------------------------- CCU4_CC4_SRS -------------------------------- */
13883 #define CCU4_CC4_SRS_POSR_Pos (0UL)
13884 #define CCU4_CC4_SRS_POSR_Msk (0x3UL)
13885 #define CCU4_CC4_SRS_CMSR_Pos (2UL)
13886 #define CCU4_CC4_SRS_CMSR_Msk (0xcUL)
13887 #define CCU4_CC4_SRS_E0SR_Pos (8UL)
13888 #define CCU4_CC4_SRS_E0SR_Msk (0x300UL)
13889 #define CCU4_CC4_SRS_E1SR_Pos (10UL)
13890 #define CCU4_CC4_SRS_E1SR_Msk (0xc00UL)
13891 #define CCU4_CC4_SRS_E2SR_Pos (12UL)
13892 #define CCU4_CC4_SRS_E2SR_Msk (0x3000UL)
13894 /* -------------------------------- CCU4_CC4_SWS -------------------------------- */
13895 #define CCU4_CC4_SWS_SPM_Pos (0UL)
13896 #define CCU4_CC4_SWS_SPM_Msk (0x1UL)
13897 #define CCU4_CC4_SWS_SOM_Pos (1UL)
13898 #define CCU4_CC4_SWS_SOM_Msk (0x2UL)
13899 #define CCU4_CC4_SWS_SCMU_Pos (2UL)
13900 #define CCU4_CC4_SWS_SCMU_Msk (0x4UL)
13901 #define CCU4_CC4_SWS_SCMD_Pos (3UL)
13902 #define CCU4_CC4_SWS_SCMD_Msk (0x8UL)
13903 #define CCU4_CC4_SWS_SE0A_Pos (8UL)
13904 #define CCU4_CC4_SWS_SE0A_Msk (0x100UL)
13905 #define CCU4_CC4_SWS_SE1A_Pos (9UL)
13906 #define CCU4_CC4_SWS_SE1A_Msk (0x200UL)
13907 #define CCU4_CC4_SWS_SE2A_Pos (10UL)
13908 #define CCU4_CC4_SWS_SE2A_Msk (0x400UL)
13909 #define CCU4_CC4_SWS_STRPF_Pos (11UL)
13910 #define CCU4_CC4_SWS_STRPF_Msk (0x800UL)
13912 /* -------------------------------- CCU4_CC4_SWR -------------------------------- */
13913 #define CCU4_CC4_SWR_RPM_Pos (0UL)
13914 #define CCU4_CC4_SWR_RPM_Msk (0x1UL)
13915 #define CCU4_CC4_SWR_ROM_Pos (1UL)
13916 #define CCU4_CC4_SWR_ROM_Msk (0x2UL)
13917 #define CCU4_CC4_SWR_RCMU_Pos (2UL)
13918 #define CCU4_CC4_SWR_RCMU_Msk (0x4UL)
13919 #define CCU4_CC4_SWR_RCMD_Pos (3UL)
13920 #define CCU4_CC4_SWR_RCMD_Msk (0x8UL)
13921 #define CCU4_CC4_SWR_RE0A_Pos (8UL)
13922 #define CCU4_CC4_SWR_RE0A_Msk (0x100UL)
13923 #define CCU4_CC4_SWR_RE1A_Pos (9UL)
13924 #define CCU4_CC4_SWR_RE1A_Msk (0x200UL)
13925 #define CCU4_CC4_SWR_RE2A_Pos (10UL)
13926 #define CCU4_CC4_SWR_RE2A_Msk (0x400UL)
13927 #define CCU4_CC4_SWR_RTRPF_Pos (11UL)
13928 #define CCU4_CC4_SWR_RTRPF_Msk (0x800UL)
13930 /* ------------------------------- CCU4_CC4_ECRD0 ------------------------------- */
13931 #define CCU4_CC4_ECRD0_CAPV_Pos (0UL)
13932 #define CCU4_CC4_ECRD0_CAPV_Msk (0xffffUL)
13933 #define CCU4_CC4_ECRD0_FPCV_Pos (16UL)
13934 #define CCU4_CC4_ECRD0_FPCV_Msk (0xf0000UL)
13935 #define CCU4_CC4_ECRD0_SPTR_Pos (20UL)
13936 #define CCU4_CC4_ECRD0_SPTR_Msk (0x300000UL)
13937 #define CCU4_CC4_ECRD0_VPTR_Pos (22UL)
13938 #define CCU4_CC4_ECRD0_VPTR_Msk (0xc00000UL)
13939 #define CCU4_CC4_ECRD0_FFL_Pos (24UL)
13940 #define CCU4_CC4_ECRD0_FFL_Msk (0x1000000UL)
13941 #define CCU4_CC4_ECRD0_LCV_Pos (25UL)
13942 #define CCU4_CC4_ECRD0_LCV_Msk (0x2000000UL)
13944 /* ------------------------------- CCU4_CC4_ECRD1 ------------------------------- */
13945 #define CCU4_CC4_ECRD1_CAPV_Pos (0UL)
13946 #define CCU4_CC4_ECRD1_CAPV_Msk (0xffffUL)
13947 #define CCU4_CC4_ECRD1_FPCV_Pos (16UL)
13948 #define CCU4_CC4_ECRD1_FPCV_Msk (0xf0000UL)
13949 #define CCU4_CC4_ECRD1_SPTR_Pos (20UL)
13950 #define CCU4_CC4_ECRD1_SPTR_Msk (0x300000UL)
13951 #define CCU4_CC4_ECRD1_VPTR_Pos (22UL)
13952 #define CCU4_CC4_ECRD1_VPTR_Msk (0xc00000UL)
13953 #define CCU4_CC4_ECRD1_FFL_Pos (24UL)
13954 #define CCU4_CC4_ECRD1_FFL_Msk (0x1000000UL)
13955 #define CCU4_CC4_ECRD1_LCV_Pos (25UL)
13956 #define CCU4_CC4_ECRD1_LCV_Msk (0x2000000UL)
13959 /* ================================================================================ */
13960 /* ================ Group 'CCU8' Position & Mask ================ */
13961 /* ================================================================================ */
13962 
13963 
13964 /* --------------------------------- CCU8_GCTRL --------------------------------- */
13965 #define CCU8_GCTRL_PRBC_Pos (0UL)
13966 #define CCU8_GCTRL_PRBC_Msk (0x7UL)
13967 #define CCU8_GCTRL_PCIS_Pos (4UL)
13968 #define CCU8_GCTRL_PCIS_Msk (0x30UL)
13969 #define CCU8_GCTRL_SUSCFG_Pos (8UL)
13970 #define CCU8_GCTRL_SUSCFG_Msk (0x300UL)
13971 #define CCU8_GCTRL_MSE0_Pos (10UL)
13972 #define CCU8_GCTRL_MSE0_Msk (0x400UL)
13973 #define CCU8_GCTRL_MSE1_Pos (11UL)
13974 #define CCU8_GCTRL_MSE1_Msk (0x800UL)
13975 #define CCU8_GCTRL_MSE2_Pos (12UL)
13976 #define CCU8_GCTRL_MSE2_Msk (0x1000UL)
13977 #define CCU8_GCTRL_MSE3_Pos (13UL)
13978 #define CCU8_GCTRL_MSE3_Msk (0x2000UL)
13979 #define CCU8_GCTRL_MSDE_Pos (14UL)
13980 #define CCU8_GCTRL_MSDE_Msk (0xc000UL)
13982 /* --------------------------------- CCU8_GSTAT --------------------------------- */
13983 #define CCU8_GSTAT_S0I_Pos (0UL)
13984 #define CCU8_GSTAT_S0I_Msk (0x1UL)
13985 #define CCU8_GSTAT_S1I_Pos (1UL)
13986 #define CCU8_GSTAT_S1I_Msk (0x2UL)
13987 #define CCU8_GSTAT_S2I_Pos (2UL)
13988 #define CCU8_GSTAT_S2I_Msk (0x4UL)
13989 #define CCU8_GSTAT_S3I_Pos (3UL)
13990 #define CCU8_GSTAT_S3I_Msk (0x8UL)
13991 #define CCU8_GSTAT_PRB_Pos (8UL)
13992 #define CCU8_GSTAT_PRB_Msk (0x100UL)
13993 #define CCU8_GSTAT_PCRB_Pos (10UL)
13994 #define CCU8_GSTAT_PCRB_Msk (0x400UL)
13996 /* --------------------------------- CCU8_GIDLS --------------------------------- */
13997 #define CCU8_GIDLS_SS0I_Pos (0UL)
13998 #define CCU8_GIDLS_SS0I_Msk (0x1UL)
13999 #define CCU8_GIDLS_SS1I_Pos (1UL)
14000 #define CCU8_GIDLS_SS1I_Msk (0x2UL)
14001 #define CCU8_GIDLS_SS2I_Pos (2UL)
14002 #define CCU8_GIDLS_SS2I_Msk (0x4UL)
14003 #define CCU8_GIDLS_SS3I_Pos (3UL)
14004 #define CCU8_GIDLS_SS3I_Msk (0x8UL)
14005 #define CCU8_GIDLS_CPRB_Pos (8UL)
14006 #define CCU8_GIDLS_CPRB_Msk (0x100UL)
14007 #define CCU8_GIDLS_PSIC_Pos (9UL)
14008 #define CCU8_GIDLS_PSIC_Msk (0x200UL)
14009 #define CCU8_GIDLS_CPCH_Pos (10UL)
14010 #define CCU8_GIDLS_CPCH_Msk (0x400UL)
14012 /* --------------------------------- CCU8_GIDLC --------------------------------- */
14013 #define CCU8_GIDLC_CS0I_Pos (0UL)
14014 #define CCU8_GIDLC_CS0I_Msk (0x1UL)
14015 #define CCU8_GIDLC_CS1I_Pos (1UL)
14016 #define CCU8_GIDLC_CS1I_Msk (0x2UL)
14017 #define CCU8_GIDLC_CS2I_Pos (2UL)
14018 #define CCU8_GIDLC_CS2I_Msk (0x4UL)
14019 #define CCU8_GIDLC_CS3I_Pos (3UL)
14020 #define CCU8_GIDLC_CS3I_Msk (0x8UL)
14021 #define CCU8_GIDLC_SPRB_Pos (8UL)
14022 #define CCU8_GIDLC_SPRB_Msk (0x100UL)
14023 #define CCU8_GIDLC_SPCH_Pos (10UL)
14024 #define CCU8_GIDLC_SPCH_Msk (0x400UL)
14026 /* ---------------------------------- CCU8_GCSS --------------------------------- */
14027 #define CCU8_GCSS_S0SE_Pos (0UL)
14028 #define CCU8_GCSS_S0SE_Msk (0x1UL)
14029 #define CCU8_GCSS_S0DSE_Pos (1UL)
14030 #define CCU8_GCSS_S0DSE_Msk (0x2UL)
14031 #define CCU8_GCSS_S0PSE_Pos (2UL)
14032 #define CCU8_GCSS_S0PSE_Msk (0x4UL)
14033 #define CCU8_GCSS_S1SE_Pos (4UL)
14034 #define CCU8_GCSS_S1SE_Msk (0x10UL)
14035 #define CCU8_GCSS_S1DSE_Pos (5UL)
14036 #define CCU8_GCSS_S1DSE_Msk (0x20UL)
14037 #define CCU8_GCSS_S1PSE_Pos (6UL)
14038 #define CCU8_GCSS_S1PSE_Msk (0x40UL)
14039 #define CCU8_GCSS_S2SE_Pos (8UL)
14040 #define CCU8_GCSS_S2SE_Msk (0x100UL)
14041 #define CCU8_GCSS_S2DSE_Pos (9UL)
14042 #define CCU8_GCSS_S2DSE_Msk (0x200UL)
14043 #define CCU8_GCSS_S2PSE_Pos (10UL)
14044 #define CCU8_GCSS_S2PSE_Msk (0x400UL)
14045 #define CCU8_GCSS_S3SE_Pos (12UL)
14046 #define CCU8_GCSS_S3SE_Msk (0x1000UL)
14047 #define CCU8_GCSS_S3DSE_Pos (13UL)
14048 #define CCU8_GCSS_S3DSE_Msk (0x2000UL)
14049 #define CCU8_GCSS_S3PSE_Pos (14UL)
14050 #define CCU8_GCSS_S3PSE_Msk (0x4000UL)
14051 #define CCU8_GCSS_S0ST1S_Pos (16UL)
14052 #define CCU8_GCSS_S0ST1S_Msk (0x10000UL)
14053 #define CCU8_GCSS_S1ST1S_Pos (17UL)
14054 #define CCU8_GCSS_S1ST1S_Msk (0x20000UL)
14055 #define CCU8_GCSS_S2ST1S_Pos (18UL)
14056 #define CCU8_GCSS_S2ST1S_Msk (0x40000UL)
14057 #define CCU8_GCSS_S3ST1S_Pos (19UL)
14058 #define CCU8_GCSS_S3ST1S_Msk (0x80000UL)
14059 #define CCU8_GCSS_S0ST2S_Pos (20UL)
14060 #define CCU8_GCSS_S0ST2S_Msk (0x100000UL)
14061 #define CCU8_GCSS_S1ST2S_Pos (21UL)
14062 #define CCU8_GCSS_S1ST2S_Msk (0x200000UL)
14063 #define CCU8_GCSS_S2ST2S_Pos (22UL)
14064 #define CCU8_GCSS_S2ST2S_Msk (0x400000UL)
14065 #define CCU8_GCSS_S3ST2S_Pos (23UL)
14066 #define CCU8_GCSS_S3ST2S_Msk (0x800000UL)
14068 /* ---------------------------------- CCU8_GCSC --------------------------------- */
14069 #define CCU8_GCSC_S0SC_Pos (0UL)
14070 #define CCU8_GCSC_S0SC_Msk (0x1UL)
14071 #define CCU8_GCSC_S0DSC_Pos (1UL)
14072 #define CCU8_GCSC_S0DSC_Msk (0x2UL)
14073 #define CCU8_GCSC_S0PSC_Pos (2UL)
14074 #define CCU8_GCSC_S0PSC_Msk (0x4UL)
14075 #define CCU8_GCSC_S1SC_Pos (4UL)
14076 #define CCU8_GCSC_S1SC_Msk (0x10UL)
14077 #define CCU8_GCSC_S1DSC_Pos (5UL)
14078 #define CCU8_GCSC_S1DSC_Msk (0x20UL)
14079 #define CCU8_GCSC_S1PSC_Pos (6UL)
14080 #define CCU8_GCSC_S1PSC_Msk (0x40UL)
14081 #define CCU8_GCSC_S2SC_Pos (8UL)
14082 #define CCU8_GCSC_S2SC_Msk (0x100UL)
14083 #define CCU8_GCSC_S2DSC_Pos (9UL)
14084 #define CCU8_GCSC_S2DSC_Msk (0x200UL)
14085 #define CCU8_GCSC_S2PSC_Pos (10UL)
14086 #define CCU8_GCSC_S2PSC_Msk (0x400UL)
14087 #define CCU8_GCSC_S3SC_Pos (12UL)
14088 #define CCU8_GCSC_S3SC_Msk (0x1000UL)
14089 #define CCU8_GCSC_S3DSC_Pos (13UL)
14090 #define CCU8_GCSC_S3DSC_Msk (0x2000UL)
14091 #define CCU8_GCSC_S3PSC_Pos (14UL)
14092 #define CCU8_GCSC_S3PSC_Msk (0x4000UL)
14093 #define CCU8_GCSC_S0ST1C_Pos (16UL)
14094 #define CCU8_GCSC_S0ST1C_Msk (0x10000UL)
14095 #define CCU8_GCSC_S1ST1C_Pos (17UL)
14096 #define CCU8_GCSC_S1ST1C_Msk (0x20000UL)
14097 #define CCU8_GCSC_S2ST1C_Pos (18UL)
14098 #define CCU8_GCSC_S2ST1C_Msk (0x40000UL)
14099 #define CCU8_GCSC_S3ST1C_Pos (19UL)
14100 #define CCU8_GCSC_S3ST1C_Msk (0x80000UL)
14101 #define CCU8_GCSC_S0ST2C_Pos (20UL)
14102 #define CCU8_GCSC_S0ST2C_Msk (0x100000UL)
14103 #define CCU8_GCSC_S1ST2C_Pos (21UL)
14104 #define CCU8_GCSC_S1ST2C_Msk (0x200000UL)
14105 #define CCU8_GCSC_S2ST2C_Pos (22UL)
14106 #define CCU8_GCSC_S2ST2C_Msk (0x400000UL)
14107 #define CCU8_GCSC_S3ST2C_Pos (23UL)
14108 #define CCU8_GCSC_S3ST2C_Msk (0x800000UL)
14110 /* ---------------------------------- CCU8_GCST --------------------------------- */
14111 #define CCU8_GCST_S0SS_Pos (0UL)
14112 #define CCU8_GCST_S0SS_Msk (0x1UL)
14113 #define CCU8_GCST_S0DSS_Pos (1UL)
14114 #define CCU8_GCST_S0DSS_Msk (0x2UL)
14115 #define CCU8_GCST_S0PSS_Pos (2UL)
14116 #define CCU8_GCST_S0PSS_Msk (0x4UL)
14117 #define CCU8_GCST_S1SS_Pos (4UL)
14118 #define CCU8_GCST_S1SS_Msk (0x10UL)
14119 #define CCU8_GCST_S1DSS_Pos (5UL)
14120 #define CCU8_GCST_S1DSS_Msk (0x20UL)
14121 #define CCU8_GCST_S1PSS_Pos (6UL)
14122 #define CCU8_GCST_S1PSS_Msk (0x40UL)
14123 #define CCU8_GCST_S2SS_Pos (8UL)
14124 #define CCU8_GCST_S2SS_Msk (0x100UL)
14125 #define CCU8_GCST_S2DSS_Pos (9UL)
14126 #define CCU8_GCST_S2DSS_Msk (0x200UL)
14127 #define CCU8_GCST_S2PSS_Pos (10UL)
14128 #define CCU8_GCST_S2PSS_Msk (0x400UL)
14129 #define CCU8_GCST_S3SS_Pos (12UL)
14130 #define CCU8_GCST_S3SS_Msk (0x1000UL)
14131 #define CCU8_GCST_S3DSS_Pos (13UL)
14132 #define CCU8_GCST_S3DSS_Msk (0x2000UL)
14133 #define CCU8_GCST_S3PSS_Pos (14UL)
14134 #define CCU8_GCST_S3PSS_Msk (0x4000UL)
14135 #define CCU8_GCST_CC80ST1_Pos (16UL)
14136 #define CCU8_GCST_CC80ST1_Msk (0x10000UL)
14137 #define CCU8_GCST_CC81ST1_Pos (17UL)
14138 #define CCU8_GCST_CC81ST1_Msk (0x20000UL)
14139 #define CCU8_GCST_CC82ST1_Pos (18UL)
14140 #define CCU8_GCST_CC82ST1_Msk (0x40000UL)
14141 #define CCU8_GCST_CC83ST1_Pos (19UL)
14142 #define CCU8_GCST_CC83ST1_Msk (0x80000UL)
14143 #define CCU8_GCST_CC80ST2_Pos (20UL)
14144 #define CCU8_GCST_CC80ST2_Msk (0x100000UL)
14145 #define CCU8_GCST_CC81ST2_Pos (21UL)
14146 #define CCU8_GCST_CC81ST2_Msk (0x200000UL)
14147 #define CCU8_GCST_CC82ST2_Pos (22UL)
14148 #define CCU8_GCST_CC82ST2_Msk (0x400000UL)
14149 #define CCU8_GCST_CC83ST2_Pos (23UL)
14150 #define CCU8_GCST_CC83ST2_Msk (0x800000UL)
14152 /* --------------------------------- CCU8_GPCHK --------------------------------- */
14153 #define CCU8_GPCHK_PASE_Pos (0UL)
14154 #define CCU8_GPCHK_PASE_Msk (0x1UL)
14155 #define CCU8_GPCHK_PACS_Pos (1UL)
14156 #define CCU8_GPCHK_PACS_Msk (0x6UL)
14157 #define CCU8_GPCHK_PISEL_Pos (3UL)
14158 #define CCU8_GPCHK_PISEL_Msk (0x18UL)
14159 #define CCU8_GPCHK_PCDS_Pos (5UL)
14160 #define CCU8_GPCHK_PCDS_Msk (0x60UL)
14161 #define CCU8_GPCHK_PCTS_Pos (7UL)
14162 #define CCU8_GPCHK_PCTS_Msk (0x80UL)
14163 #define CCU8_GPCHK_PCST_Pos (15UL)
14164 #define CCU8_GPCHK_PCST_Msk (0x8000UL)
14165 #define CCU8_GPCHK_PCSEL0_Pos (16UL)
14166 #define CCU8_GPCHK_PCSEL0_Msk (0xf0000UL)
14167 #define CCU8_GPCHK_PCSEL1_Pos (20UL)
14168 #define CCU8_GPCHK_PCSEL1_Msk (0xf00000UL)
14169 #define CCU8_GPCHK_PCSEL2_Pos (24UL)
14170 #define CCU8_GPCHK_PCSEL2_Msk (0xf000000UL)
14171 #define CCU8_GPCHK_PCSEL3_Pos (28UL)
14172 #define CCU8_GPCHK_PCSEL3_Msk (0xf0000000UL)
14174 /* ---------------------------------- CCU8_MIDR --------------------------------- */
14175 #define CCU8_MIDR_MODR_Pos (0UL)
14176 #define CCU8_MIDR_MODR_Msk (0xffUL)
14177 #define CCU8_MIDR_MODT_Pos (8UL)
14178 #define CCU8_MIDR_MODT_Msk (0xff00UL)
14179 #define CCU8_MIDR_MODN_Pos (16UL)
14180 #define CCU8_MIDR_MODN_Msk (0xffff0000UL)
14183 /* ================================================================================ */
14184 /* ================ Group 'CCU8_CC8' Position & Mask ================ */
14185 /* ================================================================================ */
14186 
14187 
14188 /* -------------------------------- CCU8_CC8_INS -------------------------------- */
14189 #define CCU8_CC8_INS_EV0IS_Pos (0UL)
14190 #define CCU8_CC8_INS_EV0IS_Msk (0xfUL)
14191 #define CCU8_CC8_INS_EV1IS_Pos (4UL)
14192 #define CCU8_CC8_INS_EV1IS_Msk (0xf0UL)
14193 #define CCU8_CC8_INS_EV2IS_Pos (8UL)
14194 #define CCU8_CC8_INS_EV2IS_Msk (0xf00UL)
14195 #define CCU8_CC8_INS_EV0EM_Pos (16UL)
14196 #define CCU8_CC8_INS_EV0EM_Msk (0x30000UL)
14197 #define CCU8_CC8_INS_EV1EM_Pos (18UL)
14198 #define CCU8_CC8_INS_EV1EM_Msk (0xc0000UL)
14199 #define CCU8_CC8_INS_EV2EM_Pos (20UL)
14200 #define CCU8_CC8_INS_EV2EM_Msk (0x300000UL)
14201 #define CCU8_CC8_INS_EV0LM_Pos (22UL)
14202 #define CCU8_CC8_INS_EV0LM_Msk (0x400000UL)
14203 #define CCU8_CC8_INS_EV1LM_Pos (23UL)
14204 #define CCU8_CC8_INS_EV1LM_Msk (0x800000UL)
14205 #define CCU8_CC8_INS_EV2LM_Pos (24UL)
14206 #define CCU8_CC8_INS_EV2LM_Msk (0x1000000UL)
14207 #define CCU8_CC8_INS_LPF0M_Pos (25UL)
14208 #define CCU8_CC8_INS_LPF0M_Msk (0x6000000UL)
14209 #define CCU8_CC8_INS_LPF1M_Pos (27UL)
14210 #define CCU8_CC8_INS_LPF1M_Msk (0x18000000UL)
14211 #define CCU8_CC8_INS_LPF2M_Pos (29UL)
14212 #define CCU8_CC8_INS_LPF2M_Msk (0x60000000UL)
14214 /* -------------------------------- CCU8_CC8_CMC -------------------------------- */
14215 #define CCU8_CC8_CMC_STRTS_Pos (0UL)
14216 #define CCU8_CC8_CMC_STRTS_Msk (0x3UL)
14217 #define CCU8_CC8_CMC_ENDS_Pos (2UL)
14218 #define CCU8_CC8_CMC_ENDS_Msk (0xcUL)
14219 #define CCU8_CC8_CMC_CAP0S_Pos (4UL)
14220 #define CCU8_CC8_CMC_CAP0S_Msk (0x30UL)
14221 #define CCU8_CC8_CMC_CAP1S_Pos (6UL)
14222 #define CCU8_CC8_CMC_CAP1S_Msk (0xc0UL)
14223 #define CCU8_CC8_CMC_GATES_Pos (8UL)
14224 #define CCU8_CC8_CMC_GATES_Msk (0x300UL)
14225 #define CCU8_CC8_CMC_UDS_Pos (10UL)
14226 #define CCU8_CC8_CMC_UDS_Msk (0xc00UL)
14227 #define CCU8_CC8_CMC_LDS_Pos (12UL)
14228 #define CCU8_CC8_CMC_LDS_Msk (0x3000UL)
14229 #define CCU8_CC8_CMC_CNTS_Pos (14UL)
14230 #define CCU8_CC8_CMC_CNTS_Msk (0xc000UL)
14231 #define CCU8_CC8_CMC_OFS_Pos (16UL)
14232 #define CCU8_CC8_CMC_OFS_Msk (0x10000UL)
14233 #define CCU8_CC8_CMC_TS_Pos (17UL)
14234 #define CCU8_CC8_CMC_TS_Msk (0x20000UL)
14235 #define CCU8_CC8_CMC_MOS_Pos (18UL)
14236 #define CCU8_CC8_CMC_MOS_Msk (0xc0000UL)
14237 #define CCU8_CC8_CMC_TCE_Pos (20UL)
14238 #define CCU8_CC8_CMC_TCE_Msk (0x100000UL)
14240 /* -------------------------------- CCU8_CC8_TCST ------------------------------- */
14241 #define CCU8_CC8_TCST_TRB_Pos (0UL)
14242 #define CCU8_CC8_TCST_TRB_Msk (0x1UL)
14243 #define CCU8_CC8_TCST_CDIR_Pos (1UL)
14244 #define CCU8_CC8_TCST_CDIR_Msk (0x2UL)
14245 #define CCU8_CC8_TCST_DTR1_Pos (3UL)
14246 #define CCU8_CC8_TCST_DTR1_Msk (0x8UL)
14247 #define CCU8_CC8_TCST_DTR2_Pos (4UL)
14248 #define CCU8_CC8_TCST_DTR2_Msk (0x10UL)
14250 /* ------------------------------- CCU8_CC8_TCSET ------------------------------- */
14251 #define CCU8_CC8_TCSET_TRBS_Pos (0UL)
14252 #define CCU8_CC8_TCSET_TRBS_Msk (0x1UL)
14254 /* ------------------------------- CCU8_CC8_TCCLR ------------------------------- */
14255 #define CCU8_CC8_TCCLR_TRBC_Pos (0UL)
14256 #define CCU8_CC8_TCCLR_TRBC_Msk (0x1UL)
14257 #define CCU8_CC8_TCCLR_TCC_Pos (1UL)
14258 #define CCU8_CC8_TCCLR_TCC_Msk (0x2UL)
14259 #define CCU8_CC8_TCCLR_DITC_Pos (2UL)
14260 #define CCU8_CC8_TCCLR_DITC_Msk (0x4UL)
14261 #define CCU8_CC8_TCCLR_DTC1C_Pos (3UL)
14262 #define CCU8_CC8_TCCLR_DTC1C_Msk (0x8UL)
14263 #define CCU8_CC8_TCCLR_DTC2C_Pos (4UL)
14264 #define CCU8_CC8_TCCLR_DTC2C_Msk (0x10UL)
14266 /* --------------------------------- CCU8_CC8_TC -------------------------------- */
14267 #define CCU8_CC8_TC_TCM_Pos (0UL)
14268 #define CCU8_CC8_TC_TCM_Msk (0x1UL)
14269 #define CCU8_CC8_TC_TSSM_Pos (1UL)
14270 #define CCU8_CC8_TC_TSSM_Msk (0x2UL)
14271 #define CCU8_CC8_TC_CLST_Pos (2UL)
14272 #define CCU8_CC8_TC_CLST_Msk (0x4UL)
14273 #define CCU8_CC8_TC_CMOD_Pos (3UL)
14274 #define CCU8_CC8_TC_CMOD_Msk (0x8UL)
14275 #define CCU8_CC8_TC_ECM_Pos (4UL)
14276 #define CCU8_CC8_TC_ECM_Msk (0x10UL)
14277 #define CCU8_CC8_TC_CAPC_Pos (5UL)
14278 #define CCU8_CC8_TC_CAPC_Msk (0x60UL)
14279 #define CCU8_CC8_TC_TLS_Pos (7UL)
14280 #define CCU8_CC8_TC_TLS_Msk (0x80UL)
14281 #define CCU8_CC8_TC_ENDM_Pos (8UL)
14282 #define CCU8_CC8_TC_ENDM_Msk (0x300UL)
14283 #define CCU8_CC8_TC_STRM_Pos (10UL)
14284 #define CCU8_CC8_TC_STRM_Msk (0x400UL)
14285 #define CCU8_CC8_TC_SCE_Pos (11UL)
14286 #define CCU8_CC8_TC_SCE_Msk (0x800UL)
14287 #define CCU8_CC8_TC_CCS_Pos (12UL)
14288 #define CCU8_CC8_TC_CCS_Msk (0x1000UL)
14289 #define CCU8_CC8_TC_DITHE_Pos (13UL)
14290 #define CCU8_CC8_TC_DITHE_Msk (0x6000UL)
14291 #define CCU8_CC8_TC_DIM_Pos (15UL)
14292 #define CCU8_CC8_TC_DIM_Msk (0x8000UL)
14293 #define CCU8_CC8_TC_FPE_Pos (16UL)
14294 #define CCU8_CC8_TC_FPE_Msk (0x10000UL)
14295 #define CCU8_CC8_TC_TRAPE0_Pos (17UL)
14296 #define CCU8_CC8_TC_TRAPE0_Msk (0x20000UL)
14297 #define CCU8_CC8_TC_TRAPE1_Pos (18UL)
14298 #define CCU8_CC8_TC_TRAPE1_Msk (0x40000UL)
14299 #define CCU8_CC8_TC_TRAPE2_Pos (19UL)
14300 #define CCU8_CC8_TC_TRAPE2_Msk (0x80000UL)
14301 #define CCU8_CC8_TC_TRAPE3_Pos (20UL)
14302 #define CCU8_CC8_TC_TRAPE3_Msk (0x100000UL)
14303 #define CCU8_CC8_TC_TRPSE_Pos (21UL)
14304 #define CCU8_CC8_TC_TRPSE_Msk (0x200000UL)
14305 #define CCU8_CC8_TC_TRPSW_Pos (22UL)
14306 #define CCU8_CC8_TC_TRPSW_Msk (0x400000UL)
14307 #define CCU8_CC8_TC_EMS_Pos (23UL)
14308 #define CCU8_CC8_TC_EMS_Msk (0x800000UL)
14309 #define CCU8_CC8_TC_EMT_Pos (24UL)
14310 #define CCU8_CC8_TC_EMT_Msk (0x1000000UL)
14311 #define CCU8_CC8_TC_MCME1_Pos (25UL)
14312 #define CCU8_CC8_TC_MCME1_Msk (0x2000000UL)
14313 #define CCU8_CC8_TC_MCME2_Pos (26UL)
14314 #define CCU8_CC8_TC_MCME2_Msk (0x4000000UL)
14315 #define CCU8_CC8_TC_EME_Pos (27UL)
14316 #define CCU8_CC8_TC_EME_Msk (0x18000000UL)
14317 #define CCU8_CC8_TC_STOS_Pos (29UL)
14318 #define CCU8_CC8_TC_STOS_Msk (0x60000000UL)
14320 /* -------------------------------- CCU8_CC8_PSL -------------------------------- */
14321 #define CCU8_CC8_PSL_PSL11_Pos (0UL)
14322 #define CCU8_CC8_PSL_PSL11_Msk (0x1UL)
14323 #define CCU8_CC8_PSL_PSL12_Pos (1UL)
14324 #define CCU8_CC8_PSL_PSL12_Msk (0x2UL)
14325 #define CCU8_CC8_PSL_PSL21_Pos (2UL)
14326 #define CCU8_CC8_PSL_PSL21_Msk (0x4UL)
14327 #define CCU8_CC8_PSL_PSL22_Pos (3UL)
14328 #define CCU8_CC8_PSL_PSL22_Msk (0x8UL)
14330 /* -------------------------------- CCU8_CC8_DIT -------------------------------- */
14331 #define CCU8_CC8_DIT_DCV_Pos (0UL)
14332 #define CCU8_CC8_DIT_DCV_Msk (0xfUL)
14333 #define CCU8_CC8_DIT_DCNT_Pos (8UL)
14334 #define CCU8_CC8_DIT_DCNT_Msk (0xf00UL)
14336 /* -------------------------------- CCU8_CC8_DITS ------------------------------- */
14337 #define CCU8_CC8_DITS_DCVS_Pos (0UL)
14338 #define CCU8_CC8_DITS_DCVS_Msk (0xfUL)
14340 /* -------------------------------- CCU8_CC8_PSC -------------------------------- */
14341 #define CCU8_CC8_PSC_PSIV_Pos (0UL)
14342 #define CCU8_CC8_PSC_PSIV_Msk (0xfUL)
14344 /* -------------------------------- CCU8_CC8_FPC -------------------------------- */
14345 #define CCU8_CC8_FPC_PCMP_Pos (0UL)
14346 #define CCU8_CC8_FPC_PCMP_Msk (0xfUL)
14347 #define CCU8_CC8_FPC_PVAL_Pos (8UL)
14348 #define CCU8_CC8_FPC_PVAL_Msk (0xf00UL)
14350 /* -------------------------------- CCU8_CC8_FPCS ------------------------------- */
14351 #define CCU8_CC8_FPCS_PCMP_Pos (0UL)
14352 #define CCU8_CC8_FPCS_PCMP_Msk (0xfUL)
14354 /* --------------------------------- CCU8_CC8_PR -------------------------------- */
14355 #define CCU8_CC8_PR_PR_Pos (0UL)
14356 #define CCU8_CC8_PR_PR_Msk (0xffffUL)
14358 /* -------------------------------- CCU8_CC8_PRS -------------------------------- */
14359 #define CCU8_CC8_PRS_PRS_Pos (0UL)
14360 #define CCU8_CC8_PRS_PRS_Msk (0xffffUL)
14362 /* -------------------------------- CCU8_CC8_CR1 -------------------------------- */
14363 #define CCU8_CC8_CR1_CR1_Pos (0UL)
14364 #define CCU8_CC8_CR1_CR1_Msk (0xffffUL)
14366 /* -------------------------------- CCU8_CC8_CR1S ------------------------------- */
14367 #define CCU8_CC8_CR1S_CR1S_Pos (0UL)
14368 #define CCU8_CC8_CR1S_CR1S_Msk (0xffffUL)
14370 /* -------------------------------- CCU8_CC8_CR2 -------------------------------- */
14371 #define CCU8_CC8_CR2_CR2_Pos (0UL)
14372 #define CCU8_CC8_CR2_CR2_Msk (0xffffUL)
14374 /* -------------------------------- CCU8_CC8_CR2S ------------------------------- */
14375 #define CCU8_CC8_CR2S_CR2S_Pos (0UL)
14376 #define CCU8_CC8_CR2S_CR2S_Msk (0xffffUL)
14378 /* -------------------------------- CCU8_CC8_CHC -------------------------------- */
14379 #define CCU8_CC8_CHC_ASE_Pos (0UL)
14380 #define CCU8_CC8_CHC_ASE_Msk (0x1UL)
14381 #define CCU8_CC8_CHC_OCS1_Pos (1UL)
14382 #define CCU8_CC8_CHC_OCS1_Msk (0x2UL)
14383 #define CCU8_CC8_CHC_OCS2_Pos (2UL)
14384 #define CCU8_CC8_CHC_OCS2_Msk (0x4UL)
14385 #define CCU8_CC8_CHC_OCS3_Pos (3UL)
14386 #define CCU8_CC8_CHC_OCS3_Msk (0x8UL)
14387 #define CCU8_CC8_CHC_OCS4_Pos (4UL)
14388 #define CCU8_CC8_CHC_OCS4_Msk (0x10UL)
14390 /* -------------------------------- CCU8_CC8_DTC -------------------------------- */
14391 #define CCU8_CC8_DTC_DTE1_Pos (0UL)
14392 #define CCU8_CC8_DTC_DTE1_Msk (0x1UL)
14393 #define CCU8_CC8_DTC_DTE2_Pos (1UL)
14394 #define CCU8_CC8_DTC_DTE2_Msk (0x2UL)
14395 #define CCU8_CC8_DTC_DCEN1_Pos (2UL)
14396 #define CCU8_CC8_DTC_DCEN1_Msk (0x4UL)
14397 #define CCU8_CC8_DTC_DCEN2_Pos (3UL)
14398 #define CCU8_CC8_DTC_DCEN2_Msk (0x8UL)
14399 #define CCU8_CC8_DTC_DCEN3_Pos (4UL)
14400 #define CCU8_CC8_DTC_DCEN3_Msk (0x10UL)
14401 #define CCU8_CC8_DTC_DCEN4_Pos (5UL)
14402 #define CCU8_CC8_DTC_DCEN4_Msk (0x20UL)
14403 #define CCU8_CC8_DTC_DTCC_Pos (6UL)
14404 #define CCU8_CC8_DTC_DTCC_Msk (0xc0UL)
14406 /* -------------------------------- CCU8_CC8_DC1R ------------------------------- */
14407 #define CCU8_CC8_DC1R_DT1R_Pos (0UL)
14408 #define CCU8_CC8_DC1R_DT1R_Msk (0xffUL)
14409 #define CCU8_CC8_DC1R_DT1F_Pos (8UL)
14410 #define CCU8_CC8_DC1R_DT1F_Msk (0xff00UL)
14412 /* -------------------------------- CCU8_CC8_DC2R ------------------------------- */
14413 #define CCU8_CC8_DC2R_DT2R_Pos (0UL)
14414 #define CCU8_CC8_DC2R_DT2R_Msk (0xffUL)
14415 #define CCU8_CC8_DC2R_DT2F_Pos (8UL)
14416 #define CCU8_CC8_DC2R_DT2F_Msk (0xff00UL)
14418 /* ------------------------------- CCU8_CC8_TIMER ------------------------------- */
14419 #define CCU8_CC8_TIMER_TVAL_Pos (0UL)
14420 #define CCU8_CC8_TIMER_TVAL_Msk (0xffffUL)
14422 /* --------------------------------- CCU8_CC8_CV -------------------------------- */
14423 #define CCU8_CC8_CV_CAPTV_Pos (0UL)
14424 #define CCU8_CC8_CV_CAPTV_Msk (0xffffUL)
14425 #define CCU8_CC8_CV_FPCV_Pos (16UL)
14426 #define CCU8_CC8_CV_FPCV_Msk (0xf0000UL)
14427 #define CCU8_CC8_CV_FFL_Pos (20UL)
14428 #define CCU8_CC8_CV_FFL_Msk (0x100000UL)
14430 /* -------------------------------- CCU8_CC8_INTS ------------------------------- */
14431 #define CCU8_CC8_INTS_PMUS_Pos (0UL)
14432 #define CCU8_CC8_INTS_PMUS_Msk (0x1UL)
14433 #define CCU8_CC8_INTS_OMDS_Pos (1UL)
14434 #define CCU8_CC8_INTS_OMDS_Msk (0x2UL)
14435 #define CCU8_CC8_INTS_CMU1S_Pos (2UL)
14436 #define CCU8_CC8_INTS_CMU1S_Msk (0x4UL)
14437 #define CCU8_CC8_INTS_CMD1S_Pos (3UL)
14438 #define CCU8_CC8_INTS_CMD1S_Msk (0x8UL)
14439 #define CCU8_CC8_INTS_CMU2S_Pos (4UL)
14440 #define CCU8_CC8_INTS_CMU2S_Msk (0x10UL)
14441 #define CCU8_CC8_INTS_CMD2S_Pos (5UL)
14442 #define CCU8_CC8_INTS_CMD2S_Msk (0x20UL)
14443 #define CCU8_CC8_INTS_E0AS_Pos (8UL)
14444 #define CCU8_CC8_INTS_E0AS_Msk (0x100UL)
14445 #define CCU8_CC8_INTS_E1AS_Pos (9UL)
14446 #define CCU8_CC8_INTS_E1AS_Msk (0x200UL)
14447 #define CCU8_CC8_INTS_E2AS_Pos (10UL)
14448 #define CCU8_CC8_INTS_E2AS_Msk (0x400UL)
14449 #define CCU8_CC8_INTS_TRPF_Pos (11UL)
14450 #define CCU8_CC8_INTS_TRPF_Msk (0x800UL)
14452 /* -------------------------------- CCU8_CC8_INTE ------------------------------- */
14453 #define CCU8_CC8_INTE_PME_Pos (0UL)
14454 #define CCU8_CC8_INTE_PME_Msk (0x1UL)
14455 #define CCU8_CC8_INTE_OME_Pos (1UL)
14456 #define CCU8_CC8_INTE_OME_Msk (0x2UL)
14457 #define CCU8_CC8_INTE_CMU1E_Pos (2UL)
14458 #define CCU8_CC8_INTE_CMU1E_Msk (0x4UL)
14459 #define CCU8_CC8_INTE_CMD1E_Pos (3UL)
14460 #define CCU8_CC8_INTE_CMD1E_Msk (0x8UL)
14461 #define CCU8_CC8_INTE_CMU2E_Pos (4UL)
14462 #define CCU8_CC8_INTE_CMU2E_Msk (0x10UL)
14463 #define CCU8_CC8_INTE_CMD2E_Pos (5UL)
14464 #define CCU8_CC8_INTE_CMD2E_Msk (0x20UL)
14465 #define CCU8_CC8_INTE_E0AE_Pos (8UL)
14466 #define CCU8_CC8_INTE_E0AE_Msk (0x100UL)
14467 #define CCU8_CC8_INTE_E1AE_Pos (9UL)
14468 #define CCU8_CC8_INTE_E1AE_Msk (0x200UL)
14469 #define CCU8_CC8_INTE_E2AE_Pos (10UL)
14470 #define CCU8_CC8_INTE_E2AE_Msk (0x400UL)
14472 /* -------------------------------- CCU8_CC8_SRS -------------------------------- */
14473 #define CCU8_CC8_SRS_POSR_Pos (0UL)
14474 #define CCU8_CC8_SRS_POSR_Msk (0x3UL)
14475 #define CCU8_CC8_SRS_CM1SR_Pos (2UL)
14476 #define CCU8_CC8_SRS_CM1SR_Msk (0xcUL)
14477 #define CCU8_CC8_SRS_CM2SR_Pos (4UL)
14478 #define CCU8_CC8_SRS_CM2SR_Msk (0x30UL)
14479 #define CCU8_CC8_SRS_E0SR_Pos (8UL)
14480 #define CCU8_CC8_SRS_E0SR_Msk (0x300UL)
14481 #define CCU8_CC8_SRS_E1SR_Pos (10UL)
14482 #define CCU8_CC8_SRS_E1SR_Msk (0xc00UL)
14483 #define CCU8_CC8_SRS_E2SR_Pos (12UL)
14484 #define CCU8_CC8_SRS_E2SR_Msk (0x3000UL)
14486 /* -------------------------------- CCU8_CC8_SWS -------------------------------- */
14487 #define CCU8_CC8_SWS_SPM_Pos (0UL)
14488 #define CCU8_CC8_SWS_SPM_Msk (0x1UL)
14489 #define CCU8_CC8_SWS_SOM_Pos (1UL)
14490 #define CCU8_CC8_SWS_SOM_Msk (0x2UL)
14491 #define CCU8_CC8_SWS_SCM1U_Pos (2UL)
14492 #define CCU8_CC8_SWS_SCM1U_Msk (0x4UL)
14493 #define CCU8_CC8_SWS_SCM1D_Pos (3UL)
14494 #define CCU8_CC8_SWS_SCM1D_Msk (0x8UL)
14495 #define CCU8_CC8_SWS_SCM2U_Pos (4UL)
14496 #define CCU8_CC8_SWS_SCM2U_Msk (0x10UL)
14497 #define CCU8_CC8_SWS_SCM2D_Pos (5UL)
14498 #define CCU8_CC8_SWS_SCM2D_Msk (0x20UL)
14499 #define CCU8_CC8_SWS_SE0A_Pos (8UL)
14500 #define CCU8_CC8_SWS_SE0A_Msk (0x100UL)
14501 #define CCU8_CC8_SWS_SE1A_Pos (9UL)
14502 #define CCU8_CC8_SWS_SE1A_Msk (0x200UL)
14503 #define CCU8_CC8_SWS_SE2A_Pos (10UL)
14504 #define CCU8_CC8_SWS_SE2A_Msk (0x400UL)
14505 #define CCU8_CC8_SWS_STRPF_Pos (11UL)
14506 #define CCU8_CC8_SWS_STRPF_Msk (0x800UL)
14508 /* -------------------------------- CCU8_CC8_SWR -------------------------------- */
14509 #define CCU8_CC8_SWR_RPM_Pos (0UL)
14510 #define CCU8_CC8_SWR_RPM_Msk (0x1UL)
14511 #define CCU8_CC8_SWR_ROM_Pos (1UL)
14512 #define CCU8_CC8_SWR_ROM_Msk (0x2UL)
14513 #define CCU8_CC8_SWR_RCM1U_Pos (2UL)
14514 #define CCU8_CC8_SWR_RCM1U_Msk (0x4UL)
14515 #define CCU8_CC8_SWR_RCM1D_Pos (3UL)
14516 #define CCU8_CC8_SWR_RCM1D_Msk (0x8UL)
14517 #define CCU8_CC8_SWR_RCM2U_Pos (4UL)
14518 #define CCU8_CC8_SWR_RCM2U_Msk (0x10UL)
14519 #define CCU8_CC8_SWR_RCM2D_Pos (5UL)
14520 #define CCU8_CC8_SWR_RCM2D_Msk (0x20UL)
14521 #define CCU8_CC8_SWR_RE0A_Pos (8UL)
14522 #define CCU8_CC8_SWR_RE0A_Msk (0x100UL)
14523 #define CCU8_CC8_SWR_RE1A_Pos (9UL)
14524 #define CCU8_CC8_SWR_RE1A_Msk (0x200UL)
14525 #define CCU8_CC8_SWR_RE2A_Pos (10UL)
14526 #define CCU8_CC8_SWR_RE2A_Msk (0x400UL)
14527 #define CCU8_CC8_SWR_RTRPF_Pos (11UL)
14528 #define CCU8_CC8_SWR_RTRPF_Msk (0x800UL)
14530 /* -------------------------------- CCU8_CC8_STC -------------------------------- */
14531 #define CCU8_CC8_STC_CSE_Pos (0UL)
14532 #define CCU8_CC8_STC_CSE_Msk (0x1UL)
14533 #define CCU8_CC8_STC_STM_Pos (1UL)
14534 #define CCU8_CC8_STC_STM_Msk (0x6UL)
14536 /* ------------------------------- CCU8_CC8_ECRD0 ------------------------------- */
14537 #define CCU8_CC8_ECRD0_CAPV_Pos (0UL)
14538 #define CCU8_CC8_ECRD0_CAPV_Msk (0xffffUL)
14539 #define CCU8_CC8_ECRD0_FPCV_Pos (16UL)
14540 #define CCU8_CC8_ECRD0_FPCV_Msk (0xf0000UL)
14541 #define CCU8_CC8_ECRD0_SPTR_Pos (20UL)
14542 #define CCU8_CC8_ECRD0_SPTR_Msk (0x300000UL)
14543 #define CCU8_CC8_ECRD0_VPTR_Pos (22UL)
14544 #define CCU8_CC8_ECRD0_VPTR_Msk (0xc00000UL)
14545 #define CCU8_CC8_ECRD0_FFL_Pos (24UL)
14546 #define CCU8_CC8_ECRD0_FFL_Msk (0x1000000UL)
14547 #define CCU8_CC8_ECRD0_LCV_Pos (25UL)
14548 #define CCU8_CC8_ECRD0_LCV_Msk (0x2000000UL)
14550 /* ------------------------------- CCU8_CC8_ECRD1 ------------------------------- */
14551 #define CCU8_CC8_ECRD1_CAPV_Pos (0UL)
14552 #define CCU8_CC8_ECRD1_CAPV_Msk (0xffffUL)
14553 #define CCU8_CC8_ECRD1_FPCV_Pos (16UL)
14554 #define CCU8_CC8_ECRD1_FPCV_Msk (0xf0000UL)
14555 #define CCU8_CC8_ECRD1_SPTR_Pos (20UL)
14556 #define CCU8_CC8_ECRD1_SPTR_Msk (0x300000UL)
14557 #define CCU8_CC8_ECRD1_VPTR_Pos (22UL)
14558 #define CCU8_CC8_ECRD1_VPTR_Msk (0xc00000UL)
14559 #define CCU8_CC8_ECRD1_FFL_Pos (24UL)
14560 #define CCU8_CC8_ECRD1_FFL_Msk (0x1000000UL)
14561 #define CCU8_CC8_ECRD1_LCV_Pos (25UL)
14562 #define CCU8_CC8_ECRD1_LCV_Msk (0x2000000UL)
14565 /* ================================================================================ */
14566 /* ================ Group 'POSIF' Position & Mask ================ */
14567 /* ================================================================================ */
14568 
14569 
14570 /* --------------------------------- POSIF_PCONF -------------------------------- */
14571 #define POSIF_PCONF_FSEL_Pos (0UL)
14572 #define POSIF_PCONF_FSEL_Msk (0x3UL)
14573 #define POSIF_PCONF_QDCM_Pos (2UL)
14574 #define POSIF_PCONF_QDCM_Msk (0x4UL)
14575 #define POSIF_PCONF_HIDG_Pos (4UL)
14576 #define POSIF_PCONF_HIDG_Msk (0x10UL)
14577 #define POSIF_PCONF_MCUE_Pos (5UL)
14578 #define POSIF_PCONF_MCUE_Msk (0x20UL)
14579 #define POSIF_PCONF_INSEL0_Pos (8UL)
14580 #define POSIF_PCONF_INSEL0_Msk (0x300UL)
14581 #define POSIF_PCONF_INSEL1_Pos (10UL)
14582 #define POSIF_PCONF_INSEL1_Msk (0xc00UL)
14583 #define POSIF_PCONF_INSEL2_Pos (12UL)
14584 #define POSIF_PCONF_INSEL2_Msk (0x3000UL)
14585 #define POSIF_PCONF_DSEL_Pos (16UL)
14586 #define POSIF_PCONF_DSEL_Msk (0x10000UL)
14587 #define POSIF_PCONF_SPES_Pos (17UL)
14588 #define POSIF_PCONF_SPES_Msk (0x20000UL)
14589 #define POSIF_PCONF_MSETS_Pos (18UL)
14590 #define POSIF_PCONF_MSETS_Msk (0x1c0000UL)
14591 #define POSIF_PCONF_MSES_Pos (21UL)
14592 #define POSIF_PCONF_MSES_Msk (0x200000UL)
14593 #define POSIF_PCONF_MSYNS_Pos (22UL)
14594 #define POSIF_PCONF_MSYNS_Msk (0xc00000UL)
14595 #define POSIF_PCONF_EWIS_Pos (24UL)
14596 #define POSIF_PCONF_EWIS_Msk (0x3000000UL)
14597 #define POSIF_PCONF_EWIE_Pos (26UL)
14598 #define POSIF_PCONF_EWIE_Msk (0x4000000UL)
14599 #define POSIF_PCONF_EWIL_Pos (27UL)
14600 #define POSIF_PCONF_EWIL_Msk (0x8000000UL)
14601 #define POSIF_PCONF_LPC_Pos (28UL)
14602 #define POSIF_PCONF_LPC_Msk (0x70000000UL)
14604 /* --------------------------------- POSIF_PSUS --------------------------------- */
14605 #define POSIF_PSUS_QSUS_Pos (0UL)
14606 #define POSIF_PSUS_QSUS_Msk (0x3UL)
14607 #define POSIF_PSUS_MSUS_Pos (2UL)
14608 #define POSIF_PSUS_MSUS_Msk (0xcUL)
14610 /* --------------------------------- POSIF_PRUNS -------------------------------- */
14611 #define POSIF_PRUNS_SRB_Pos (0UL)
14612 #define POSIF_PRUNS_SRB_Msk (0x1UL)
14614 /* --------------------------------- POSIF_PRUNC -------------------------------- */
14615 #define POSIF_PRUNC_CRB_Pos (0UL)
14616 #define POSIF_PRUNC_CRB_Msk (0x1UL)
14617 #define POSIF_PRUNC_CSM_Pos (1UL)
14618 #define POSIF_PRUNC_CSM_Msk (0x2UL)
14620 /* --------------------------------- POSIF_PRUN --------------------------------- */
14621 #define POSIF_PRUN_RB_Pos (0UL)
14622 #define POSIF_PRUN_RB_Msk (0x1UL)
14624 /* --------------------------------- POSIF_MIDR --------------------------------- */
14625 #define POSIF_MIDR_MODR_Pos (0UL)
14626 #define POSIF_MIDR_MODR_Msk (0xffUL)
14627 #define POSIF_MIDR_MODT_Pos (8UL)
14628 #define POSIF_MIDR_MODT_Msk (0xff00UL)
14629 #define POSIF_MIDR_MODN_Pos (16UL)
14630 #define POSIF_MIDR_MODN_Msk (0xffff0000UL)
14632 /* --------------------------------- POSIF_HALP --------------------------------- */
14633 #define POSIF_HALP_HCP_Pos (0UL)
14634 #define POSIF_HALP_HCP_Msk (0x7UL)
14635 #define POSIF_HALP_HEP_Pos (3UL)
14636 #define POSIF_HALP_HEP_Msk (0x38UL)
14638 /* --------------------------------- POSIF_HALPS -------------------------------- */
14639 #define POSIF_HALPS_HCPS_Pos (0UL)
14640 #define POSIF_HALPS_HCPS_Msk (0x7UL)
14641 #define POSIF_HALPS_HEPS_Pos (3UL)
14642 #define POSIF_HALPS_HEPS_Msk (0x38UL)
14644 /* ---------------------------------- POSIF_MCM --------------------------------- */
14645 #define POSIF_MCM_MCMP_Pos (0UL)
14646 #define POSIF_MCM_MCMP_Msk (0xffffUL)
14648 /* --------------------------------- POSIF_MCSM --------------------------------- */
14649 #define POSIF_MCSM_MCMPS_Pos (0UL)
14650 #define POSIF_MCSM_MCMPS_Msk (0xffffUL)
14652 /* --------------------------------- POSIF_MCMS --------------------------------- */
14653 #define POSIF_MCMS_MNPS_Pos (0UL)
14654 #define POSIF_MCMS_MNPS_Msk (0x1UL)
14655 #define POSIF_MCMS_STHR_Pos (1UL)
14656 #define POSIF_MCMS_STHR_Msk (0x2UL)
14657 #define POSIF_MCMS_STMR_Pos (2UL)
14658 #define POSIF_MCMS_STMR_Msk (0x4UL)
14660 /* --------------------------------- POSIF_MCMC --------------------------------- */
14661 #define POSIF_MCMC_MNPC_Pos (0UL)
14662 #define POSIF_MCMC_MNPC_Msk (0x1UL)
14663 #define POSIF_MCMC_MPC_Pos (1UL)
14664 #define POSIF_MCMC_MPC_Msk (0x2UL)
14666 /* --------------------------------- POSIF_MCMF --------------------------------- */
14667 #define POSIF_MCMF_MSS_Pos (0UL)
14668 #define POSIF_MCMF_MSS_Msk (0x1UL)
14670 /* ---------------------------------- POSIF_QDC --------------------------------- */
14671 #define POSIF_QDC_PALS_Pos (0UL)
14672 #define POSIF_QDC_PALS_Msk (0x1UL)
14673 #define POSIF_QDC_PBLS_Pos (1UL)
14674 #define POSIF_QDC_PBLS_Msk (0x2UL)
14675 #define POSIF_QDC_PHS_Pos (2UL)
14676 #define POSIF_QDC_PHS_Msk (0x4UL)
14677 #define POSIF_QDC_ICM_Pos (4UL)
14678 #define POSIF_QDC_ICM_Msk (0x30UL)
14679 #define POSIF_QDC_DVAL_Pos (8UL)
14680 #define POSIF_QDC_DVAL_Msk (0x100UL)
14682 /* --------------------------------- POSIF_PFLG --------------------------------- */
14683 #define POSIF_PFLG_CHES_Pos (0UL)
14684 #define POSIF_PFLG_CHES_Msk (0x1UL)
14685 #define POSIF_PFLG_WHES_Pos (1UL)
14686 #define POSIF_PFLG_WHES_Msk (0x2UL)
14687 #define POSIF_PFLG_HIES_Pos (2UL)
14688 #define POSIF_PFLG_HIES_Msk (0x4UL)
14689 #define POSIF_PFLG_MSTS_Pos (4UL)
14690 #define POSIF_PFLG_MSTS_Msk (0x10UL)
14691 #define POSIF_PFLG_INDXS_Pos (8UL)
14692 #define POSIF_PFLG_INDXS_Msk (0x100UL)
14693 #define POSIF_PFLG_ERRS_Pos (9UL)
14694 #define POSIF_PFLG_ERRS_Msk (0x200UL)
14695 #define POSIF_PFLG_CNTS_Pos (10UL)
14696 #define POSIF_PFLG_CNTS_Msk (0x400UL)
14697 #define POSIF_PFLG_DIRS_Pos (11UL)
14698 #define POSIF_PFLG_DIRS_Msk (0x800UL)
14699 #define POSIF_PFLG_PCLKS_Pos (12UL)
14700 #define POSIF_PFLG_PCLKS_Msk (0x1000UL)
14702 /* --------------------------------- POSIF_PFLGE -------------------------------- */
14703 #define POSIF_PFLGE_ECHE_Pos (0UL)
14704 #define POSIF_PFLGE_ECHE_Msk (0x1UL)
14705 #define POSIF_PFLGE_EWHE_Pos (1UL)
14706 #define POSIF_PFLGE_EWHE_Msk (0x2UL)
14707 #define POSIF_PFLGE_EHIE_Pos (2UL)
14708 #define POSIF_PFLGE_EHIE_Msk (0x4UL)
14709 #define POSIF_PFLGE_EMST_Pos (4UL)
14710 #define POSIF_PFLGE_EMST_Msk (0x10UL)
14711 #define POSIF_PFLGE_EINDX_Pos (8UL)
14712 #define POSIF_PFLGE_EINDX_Msk (0x100UL)
14713 #define POSIF_PFLGE_EERR_Pos (9UL)
14714 #define POSIF_PFLGE_EERR_Msk (0x200UL)
14715 #define POSIF_PFLGE_ECNT_Pos (10UL)
14716 #define POSIF_PFLGE_ECNT_Msk (0x400UL)
14717 #define POSIF_PFLGE_EDIR_Pos (11UL)
14718 #define POSIF_PFLGE_EDIR_Msk (0x800UL)
14719 #define POSIF_PFLGE_EPCLK_Pos (12UL)
14720 #define POSIF_PFLGE_EPCLK_Msk (0x1000UL)
14721 #define POSIF_PFLGE_CHESEL_Pos (16UL)
14722 #define POSIF_PFLGE_CHESEL_Msk (0x10000UL)
14723 #define POSIF_PFLGE_WHESEL_Pos (17UL)
14724 #define POSIF_PFLGE_WHESEL_Msk (0x20000UL)
14725 #define POSIF_PFLGE_HIESEL_Pos (18UL)
14726 #define POSIF_PFLGE_HIESEL_Msk (0x40000UL)
14727 #define POSIF_PFLGE_MSTSEL_Pos (20UL)
14728 #define POSIF_PFLGE_MSTSEL_Msk (0x100000UL)
14729 #define POSIF_PFLGE_INDSEL_Pos (24UL)
14730 #define POSIF_PFLGE_INDSEL_Msk (0x1000000UL)
14731 #define POSIF_PFLGE_ERRSEL_Pos (25UL)
14732 #define POSIF_PFLGE_ERRSEL_Msk (0x2000000UL)
14733 #define POSIF_PFLGE_CNTSEL_Pos (26UL)
14734 #define POSIF_PFLGE_CNTSEL_Msk (0x4000000UL)
14735 #define POSIF_PFLGE_DIRSEL_Pos (27UL)
14736 #define POSIF_PFLGE_DIRSEL_Msk (0x8000000UL)
14737 #define POSIF_PFLGE_PCLSEL_Pos (28UL)
14738 #define POSIF_PFLGE_PCLSEL_Msk (0x10000000UL)
14740 /* --------------------------------- POSIF_SPFLG -------------------------------- */
14741 #define POSIF_SPFLG_SCHE_Pos (0UL)
14742 #define POSIF_SPFLG_SCHE_Msk (0x1UL)
14743 #define POSIF_SPFLG_SWHE_Pos (1UL)
14744 #define POSIF_SPFLG_SWHE_Msk (0x2UL)
14745 #define POSIF_SPFLG_SHIE_Pos (2UL)
14746 #define POSIF_SPFLG_SHIE_Msk (0x4UL)
14747 #define POSIF_SPFLG_SMST_Pos (4UL)
14748 #define POSIF_SPFLG_SMST_Msk (0x10UL)
14749 #define POSIF_SPFLG_SINDX_Pos (8UL)
14750 #define POSIF_SPFLG_SINDX_Msk (0x100UL)
14751 #define POSIF_SPFLG_SERR_Pos (9UL)
14752 #define POSIF_SPFLG_SERR_Msk (0x200UL)
14753 #define POSIF_SPFLG_SCNT_Pos (10UL)
14754 #define POSIF_SPFLG_SCNT_Msk (0x400UL)
14755 #define POSIF_SPFLG_SDIR_Pos (11UL)
14756 #define POSIF_SPFLG_SDIR_Msk (0x800UL)
14757 #define POSIF_SPFLG_SPCLK_Pos (12UL)
14758 #define POSIF_SPFLG_SPCLK_Msk (0x1000UL)
14760 /* --------------------------------- POSIF_RPFLG -------------------------------- */
14761 #define POSIF_RPFLG_RCHE_Pos (0UL)
14762 #define POSIF_RPFLG_RCHE_Msk (0x1UL)
14763 #define POSIF_RPFLG_RWHE_Pos (1UL)
14764 #define POSIF_RPFLG_RWHE_Msk (0x2UL)
14765 #define POSIF_RPFLG_RHIE_Pos (2UL)
14766 #define POSIF_RPFLG_RHIE_Msk (0x4UL)
14767 #define POSIF_RPFLG_RMST_Pos (4UL)
14768 #define POSIF_RPFLG_RMST_Msk (0x10UL)
14769 #define POSIF_RPFLG_RINDX_Pos (8UL)
14770 #define POSIF_RPFLG_RINDX_Msk (0x100UL)
14771 #define POSIF_RPFLG_RERR_Pos (9UL)
14772 #define POSIF_RPFLG_RERR_Msk (0x200UL)
14773 #define POSIF_RPFLG_RCNT_Pos (10UL)
14774 #define POSIF_RPFLG_RCNT_Msk (0x400UL)
14775 #define POSIF_RPFLG_RDIR_Pos (11UL)
14776 #define POSIF_RPFLG_RDIR_Msk (0x800UL)
14777 #define POSIF_RPFLG_RPCLK_Pos (12UL)
14778 #define POSIF_RPFLG_RPCLK_Msk (0x1000UL)
14780 /* --------------------------------- POSIF_PDBG --------------------------------- */
14781 #define POSIF_PDBG_QCSV_Pos (0UL)
14782 #define POSIF_PDBG_QCSV_Msk (0x3UL)
14783 #define POSIF_PDBG_QPSV_Pos (2UL)
14784 #define POSIF_PDBG_QPSV_Msk (0xcUL)
14785 #define POSIF_PDBG_IVAL_Pos (4UL)
14786 #define POSIF_PDBG_IVAL_Msk (0x10UL)
14787 #define POSIF_PDBG_HSP_Pos (5UL)
14788 #define POSIF_PDBG_HSP_Msk (0xe0UL)
14789 #define POSIF_PDBG_LPP0_Pos (8UL)
14790 #define POSIF_PDBG_LPP0_Msk (0x3f00UL)
14791 #define POSIF_PDBG_LPP1_Pos (16UL)
14792 #define POSIF_PDBG_LPP1_Msk (0x3f0000UL)
14793 #define POSIF_PDBG_LPP2_Pos (22UL)
14794 #define POSIF_PDBG_LPP2_Msk (0xfc00000UL)
14797 /* ================================================================================ */
14798 /* ================ struct 'PORT0' Position & Mask ================ */
14799 /* ================================================================================ */
14800 
14801 
14802 /* ---------------------------------- PORT0_OUT --------------------------------- */
14803 #define PORT0_OUT_P0_Pos (0UL)
14804 #define PORT0_OUT_P0_Msk (0x1UL)
14805 #define PORT0_OUT_P1_Pos (1UL)
14806 #define PORT0_OUT_P1_Msk (0x2UL)
14807 #define PORT0_OUT_P2_Pos (2UL)
14808 #define PORT0_OUT_P2_Msk (0x4UL)
14809 #define PORT0_OUT_P3_Pos (3UL)
14810 #define PORT0_OUT_P3_Msk (0x8UL)
14811 #define PORT0_OUT_P4_Pos (4UL)
14812 #define PORT0_OUT_P4_Msk (0x10UL)
14813 #define PORT0_OUT_P5_Pos (5UL)
14814 #define PORT0_OUT_P5_Msk (0x20UL)
14815 #define PORT0_OUT_P6_Pos (6UL)
14816 #define PORT0_OUT_P6_Msk (0x40UL)
14817 #define PORT0_OUT_P7_Pos (7UL)
14818 #define PORT0_OUT_P7_Msk (0x80UL)
14819 #define PORT0_OUT_P8_Pos (8UL)
14820 #define PORT0_OUT_P8_Msk (0x100UL)
14821 #define PORT0_OUT_P9_Pos (9UL)
14822 #define PORT0_OUT_P9_Msk (0x200UL)
14823 #define PORT0_OUT_P10_Pos (10UL)
14824 #define PORT0_OUT_P10_Msk (0x400UL)
14825 #define PORT0_OUT_P11_Pos (11UL)
14826 #define PORT0_OUT_P11_Msk (0x800UL)
14827 #define PORT0_OUT_P12_Pos (12UL)
14828 #define PORT0_OUT_P12_Msk (0x1000UL)
14829 #define PORT0_OUT_P13_Pos (13UL)
14830 #define PORT0_OUT_P13_Msk (0x2000UL)
14831 #define PORT0_OUT_P14_Pos (14UL)
14832 #define PORT0_OUT_P14_Msk (0x4000UL)
14833 #define PORT0_OUT_P15_Pos (15UL)
14834 #define PORT0_OUT_P15_Msk (0x8000UL)
14836 /* ---------------------------------- PORT0_OMR --------------------------------- */
14837 #define PORT0_OMR_PS0_Pos (0UL)
14838 #define PORT0_OMR_PS0_Msk (0x1UL)
14839 #define PORT0_OMR_PS1_Pos (1UL)
14840 #define PORT0_OMR_PS1_Msk (0x2UL)
14841 #define PORT0_OMR_PS2_Pos (2UL)
14842 #define PORT0_OMR_PS2_Msk (0x4UL)
14843 #define PORT0_OMR_PS3_Pos (3UL)
14844 #define PORT0_OMR_PS3_Msk (0x8UL)
14845 #define PORT0_OMR_PS4_Pos (4UL)
14846 #define PORT0_OMR_PS4_Msk (0x10UL)
14847 #define PORT0_OMR_PS5_Pos (5UL)
14848 #define PORT0_OMR_PS5_Msk (0x20UL)
14849 #define PORT0_OMR_PS6_Pos (6UL)
14850 #define PORT0_OMR_PS6_Msk (0x40UL)
14851 #define PORT0_OMR_PS7_Pos (7UL)
14852 #define PORT0_OMR_PS7_Msk (0x80UL)
14853 #define PORT0_OMR_PS8_Pos (8UL)
14854 #define PORT0_OMR_PS8_Msk (0x100UL)
14855 #define PORT0_OMR_PS9_Pos (9UL)
14856 #define PORT0_OMR_PS9_Msk (0x200UL)
14857 #define PORT0_OMR_PS10_Pos (10UL)
14858 #define PORT0_OMR_PS10_Msk (0x400UL)
14859 #define PORT0_OMR_PS11_Pos (11UL)
14860 #define PORT0_OMR_PS11_Msk (0x800UL)
14861 #define PORT0_OMR_PS12_Pos (12UL)
14862 #define PORT0_OMR_PS12_Msk (0x1000UL)
14863 #define PORT0_OMR_PS13_Pos (13UL)
14864 #define PORT0_OMR_PS13_Msk (0x2000UL)
14865 #define PORT0_OMR_PS14_Pos (14UL)
14866 #define PORT0_OMR_PS14_Msk (0x4000UL)
14867 #define PORT0_OMR_PS15_Pos (15UL)
14868 #define PORT0_OMR_PS15_Msk (0x8000UL)
14869 #define PORT0_OMR_PR0_Pos (16UL)
14870 #define PORT0_OMR_PR0_Msk (0x10000UL)
14871 #define PORT0_OMR_PR1_Pos (17UL)
14872 #define PORT0_OMR_PR1_Msk (0x20000UL)
14873 #define PORT0_OMR_PR2_Pos (18UL)
14874 #define PORT0_OMR_PR2_Msk (0x40000UL)
14875 #define PORT0_OMR_PR3_Pos (19UL)
14876 #define PORT0_OMR_PR3_Msk (0x80000UL)
14877 #define PORT0_OMR_PR4_Pos (20UL)
14878 #define PORT0_OMR_PR4_Msk (0x100000UL)
14879 #define PORT0_OMR_PR5_Pos (21UL)
14880 #define PORT0_OMR_PR5_Msk (0x200000UL)
14881 #define PORT0_OMR_PR6_Pos (22UL)
14882 #define PORT0_OMR_PR6_Msk (0x400000UL)
14883 #define PORT0_OMR_PR7_Pos (23UL)
14884 #define PORT0_OMR_PR7_Msk (0x800000UL)
14885 #define PORT0_OMR_PR8_Pos (24UL)
14886 #define PORT0_OMR_PR8_Msk (0x1000000UL)
14887 #define PORT0_OMR_PR9_Pos (25UL)
14888 #define PORT0_OMR_PR9_Msk (0x2000000UL)
14889 #define PORT0_OMR_PR10_Pos (26UL)
14890 #define PORT0_OMR_PR10_Msk (0x4000000UL)
14891 #define PORT0_OMR_PR11_Pos (27UL)
14892 #define PORT0_OMR_PR11_Msk (0x8000000UL)
14893 #define PORT0_OMR_PR12_Pos (28UL)
14894 #define PORT0_OMR_PR12_Msk (0x10000000UL)
14895 #define PORT0_OMR_PR13_Pos (29UL)
14896 #define PORT0_OMR_PR13_Msk (0x20000000UL)
14897 #define PORT0_OMR_PR14_Pos (30UL)
14898 #define PORT0_OMR_PR14_Msk (0x40000000UL)
14899 #define PORT0_OMR_PR15_Pos (31UL)
14900 #define PORT0_OMR_PR15_Msk (0x80000000UL)
14902 /* --------------------------------- PORT0_IOCR0 -------------------------------- */
14903 #define PORT0_IOCR0_PC0_Pos (3UL)
14904 #define PORT0_IOCR0_PC0_Msk (0xf8UL)
14905 #define PORT0_IOCR0_PC1_Pos (11UL)
14906 #define PORT0_IOCR0_PC1_Msk (0xf800UL)
14907 #define PORT0_IOCR0_PC2_Pos (19UL)
14908 #define PORT0_IOCR0_PC2_Msk (0xf80000UL)
14909 #define PORT0_IOCR0_PC3_Pos (27UL)
14910 #define PORT0_IOCR0_PC3_Msk (0xf8000000UL)
14912 /* --------------------------------- PORT0_IOCR4 -------------------------------- */
14913 #define PORT0_IOCR4_PC4_Pos (3UL)
14914 #define PORT0_IOCR4_PC4_Msk (0xf8UL)
14915 #define PORT0_IOCR4_PC5_Pos (11UL)
14916 #define PORT0_IOCR4_PC5_Msk (0xf800UL)
14917 #define PORT0_IOCR4_PC6_Pos (19UL)
14918 #define PORT0_IOCR4_PC6_Msk (0xf80000UL)
14919 #define PORT0_IOCR4_PC7_Pos (27UL)
14920 #define PORT0_IOCR4_PC7_Msk (0xf8000000UL)
14922 /* --------------------------------- PORT0_IOCR8 -------------------------------- */
14923 #define PORT0_IOCR8_PC8_Pos (3UL)
14924 #define PORT0_IOCR8_PC8_Msk (0xf8UL)
14925 #define PORT0_IOCR8_PC9_Pos (11UL)
14926 #define PORT0_IOCR8_PC9_Msk (0xf800UL)
14927 #define PORT0_IOCR8_PC10_Pos (19UL)
14928 #define PORT0_IOCR8_PC10_Msk (0xf80000UL)
14929 #define PORT0_IOCR8_PC11_Pos (27UL)
14930 #define PORT0_IOCR8_PC11_Msk (0xf8000000UL)
14932 /* -------------------------------- PORT0_IOCR12 -------------------------------- */
14933 #define PORT0_IOCR12_PC12_Pos (3UL)
14934 #define PORT0_IOCR12_PC12_Msk (0xf8UL)
14935 #define PORT0_IOCR12_PC13_Pos (11UL)
14936 #define PORT0_IOCR12_PC13_Msk (0xf800UL)
14937 #define PORT0_IOCR12_PC14_Pos (19UL)
14938 #define PORT0_IOCR12_PC14_Msk (0xf80000UL)
14939 #define PORT0_IOCR12_PC15_Pos (27UL)
14940 #define PORT0_IOCR12_PC15_Msk (0xf8000000UL)
14942 /* ---------------------------------- PORT0_IN ---------------------------------- */
14943 #define PORT0_IN_P0_Pos (0UL)
14944 #define PORT0_IN_P0_Msk (0x1UL)
14945 #define PORT0_IN_P1_Pos (1UL)
14946 #define PORT0_IN_P1_Msk (0x2UL)
14947 #define PORT0_IN_P2_Pos (2UL)
14948 #define PORT0_IN_P2_Msk (0x4UL)
14949 #define PORT0_IN_P3_Pos (3UL)
14950 #define PORT0_IN_P3_Msk (0x8UL)
14951 #define PORT0_IN_P4_Pos (4UL)
14952 #define PORT0_IN_P4_Msk (0x10UL)
14953 #define PORT0_IN_P5_Pos (5UL)
14954 #define PORT0_IN_P5_Msk (0x20UL)
14955 #define PORT0_IN_P6_Pos (6UL)
14956 #define PORT0_IN_P6_Msk (0x40UL)
14957 #define PORT0_IN_P7_Pos (7UL)
14958 #define PORT0_IN_P7_Msk (0x80UL)
14959 #define PORT0_IN_P8_Pos (8UL)
14960 #define PORT0_IN_P8_Msk (0x100UL)
14961 #define PORT0_IN_P9_Pos (9UL)
14962 #define PORT0_IN_P9_Msk (0x200UL)
14963 #define PORT0_IN_P10_Pos (10UL)
14964 #define PORT0_IN_P10_Msk (0x400UL)
14965 #define PORT0_IN_P11_Pos (11UL)
14966 #define PORT0_IN_P11_Msk (0x800UL)
14967 #define PORT0_IN_P12_Pos (12UL)
14968 #define PORT0_IN_P12_Msk (0x1000UL)
14969 #define PORT0_IN_P13_Pos (13UL)
14970 #define PORT0_IN_P13_Msk (0x2000UL)
14971 #define PORT0_IN_P14_Pos (14UL)
14972 #define PORT0_IN_P14_Msk (0x4000UL)
14973 #define PORT0_IN_P15_Pos (15UL)
14974 #define PORT0_IN_P15_Msk (0x8000UL)
14976 /* --------------------------------- PORT0_PDR0 --------------------------------- */
14977 #define PORT0_PDR0_PD0_Pos (0UL)
14978 #define PORT0_PDR0_PD0_Msk (0x7UL)
14979 #define PORT0_PDR0_PD1_Pos (4UL)
14980 #define PORT0_PDR0_PD1_Msk (0x70UL)
14981 #define PORT0_PDR0_PD2_Pos (8UL)
14982 #define PORT0_PDR0_PD2_Msk (0x700UL)
14983 #define PORT0_PDR0_PD3_Pos (12UL)
14984 #define PORT0_PDR0_PD3_Msk (0x7000UL)
14985 #define PORT0_PDR0_PD4_Pos (16UL)
14986 #define PORT0_PDR0_PD4_Msk (0x70000UL)
14987 #define PORT0_PDR0_PD5_Pos (20UL)
14988 #define PORT0_PDR0_PD5_Msk (0x700000UL)
14989 #define PORT0_PDR0_PD6_Pos (24UL)
14990 #define PORT0_PDR0_PD6_Msk (0x7000000UL)
14991 #define PORT0_PDR0_PD7_Pos (28UL)
14992 #define PORT0_PDR0_PD7_Msk (0x70000000UL)
14994 /* --------------------------------- PORT0_PDR1 --------------------------------- */
14995 #define PORT0_PDR1_PD8_Pos (0UL)
14996 #define PORT0_PDR1_PD8_Msk (0x7UL)
14997 #define PORT0_PDR1_PD9_Pos (4UL)
14998 #define PORT0_PDR1_PD9_Msk (0x70UL)
14999 #define PORT0_PDR1_PD10_Pos (8UL)
15000 #define PORT0_PDR1_PD10_Msk (0x700UL)
15001 #define PORT0_PDR1_PD11_Pos (12UL)
15002 #define PORT0_PDR1_PD11_Msk (0x7000UL)
15003 #define PORT0_PDR1_PD12_Pos (16UL)
15004 #define PORT0_PDR1_PD12_Msk (0x70000UL)
15005 #define PORT0_PDR1_PD13_Pos (20UL)
15006 #define PORT0_PDR1_PD13_Msk (0x700000UL)
15007 #define PORT0_PDR1_PD14_Pos (24UL)
15008 #define PORT0_PDR1_PD14_Msk (0x7000000UL)
15009 #define PORT0_PDR1_PD15_Pos (28UL)
15010 #define PORT0_PDR1_PD15_Msk (0x70000000UL)
15012 /* --------------------------------- PORT0_PDISC -------------------------------- */
15013 #define PORT0_PDISC_PDIS0_Pos (0UL)
15014 #define PORT0_PDISC_PDIS0_Msk (0x1UL)
15015 #define PORT0_PDISC_PDIS1_Pos (1UL)
15016 #define PORT0_PDISC_PDIS1_Msk (0x2UL)
15017 #define PORT0_PDISC_PDIS2_Pos (2UL)
15018 #define PORT0_PDISC_PDIS2_Msk (0x4UL)
15019 #define PORT0_PDISC_PDIS3_Pos (3UL)
15020 #define PORT0_PDISC_PDIS3_Msk (0x8UL)
15021 #define PORT0_PDISC_PDIS4_Pos (4UL)
15022 #define PORT0_PDISC_PDIS4_Msk (0x10UL)
15023 #define PORT0_PDISC_PDIS5_Pos (5UL)
15024 #define PORT0_PDISC_PDIS5_Msk (0x20UL)
15025 #define PORT0_PDISC_PDIS6_Pos (6UL)
15026 #define PORT0_PDISC_PDIS6_Msk (0x40UL)
15027 #define PORT0_PDISC_PDIS7_Pos (7UL)
15028 #define PORT0_PDISC_PDIS7_Msk (0x80UL)
15029 #define PORT0_PDISC_PDIS8_Pos (8UL)
15030 #define PORT0_PDISC_PDIS8_Msk (0x100UL)
15031 #define PORT0_PDISC_PDIS9_Pos (9UL)
15032 #define PORT0_PDISC_PDIS9_Msk (0x200UL)
15033 #define PORT0_PDISC_PDIS10_Pos (10UL)
15034 #define PORT0_PDISC_PDIS10_Msk (0x400UL)
15035 #define PORT0_PDISC_PDIS11_Pos (11UL)
15036 #define PORT0_PDISC_PDIS11_Msk (0x800UL)
15037 #define PORT0_PDISC_PDIS12_Pos (12UL)
15038 #define PORT0_PDISC_PDIS12_Msk (0x1000UL)
15039 #define PORT0_PDISC_PDIS13_Pos (13UL)
15040 #define PORT0_PDISC_PDIS13_Msk (0x2000UL)
15041 #define PORT0_PDISC_PDIS14_Pos (14UL)
15042 #define PORT0_PDISC_PDIS14_Msk (0x4000UL)
15043 #define PORT0_PDISC_PDIS15_Pos (15UL)
15044 #define PORT0_PDISC_PDIS15_Msk (0x8000UL)
15046 /* ---------------------------------- PORT0_PPS --------------------------------- */
15047 #define PORT0_PPS_PPS0_Pos (0UL)
15048 #define PORT0_PPS_PPS0_Msk (0x1UL)
15049 #define PORT0_PPS_PPS1_Pos (1UL)
15050 #define PORT0_PPS_PPS1_Msk (0x2UL)
15051 #define PORT0_PPS_PPS2_Pos (2UL)
15052 #define PORT0_PPS_PPS2_Msk (0x4UL)
15053 #define PORT0_PPS_PPS3_Pos (3UL)
15054 #define PORT0_PPS_PPS3_Msk (0x8UL)
15055 #define PORT0_PPS_PPS4_Pos (4UL)
15056 #define PORT0_PPS_PPS4_Msk (0x10UL)
15057 #define PORT0_PPS_PPS5_Pos (5UL)
15058 #define PORT0_PPS_PPS5_Msk (0x20UL)
15059 #define PORT0_PPS_PPS6_Pos (6UL)
15060 #define PORT0_PPS_PPS6_Msk (0x40UL)
15061 #define PORT0_PPS_PPS7_Pos (7UL)
15062 #define PORT0_PPS_PPS7_Msk (0x80UL)
15063 #define PORT0_PPS_PPS8_Pos (8UL)
15064 #define PORT0_PPS_PPS8_Msk (0x100UL)
15065 #define PORT0_PPS_PPS9_Pos (9UL)
15066 #define PORT0_PPS_PPS9_Msk (0x200UL)
15067 #define PORT0_PPS_PPS10_Pos (10UL)
15068 #define PORT0_PPS_PPS10_Msk (0x400UL)
15069 #define PORT0_PPS_PPS11_Pos (11UL)
15070 #define PORT0_PPS_PPS11_Msk (0x800UL)
15071 #define PORT0_PPS_PPS12_Pos (12UL)
15072 #define PORT0_PPS_PPS12_Msk (0x1000UL)
15073 #define PORT0_PPS_PPS13_Pos (13UL)
15074 #define PORT0_PPS_PPS13_Msk (0x2000UL)
15075 #define PORT0_PPS_PPS14_Pos (14UL)
15076 #define PORT0_PPS_PPS14_Msk (0x4000UL)
15077 #define PORT0_PPS_PPS15_Pos (15UL)
15078 #define PORT0_PPS_PPS15_Msk (0x8000UL)
15080 /* --------------------------------- PORT0_HWSEL -------------------------------- */
15081 #define PORT0_HWSEL_HW0_Pos (0UL)
15082 #define PORT0_HWSEL_HW0_Msk (0x3UL)
15083 #define PORT0_HWSEL_HW1_Pos (2UL)
15084 #define PORT0_HWSEL_HW1_Msk (0xcUL)
15085 #define PORT0_HWSEL_HW2_Pos (4UL)
15086 #define PORT0_HWSEL_HW2_Msk (0x30UL)
15087 #define PORT0_HWSEL_HW3_Pos (6UL)
15088 #define PORT0_HWSEL_HW3_Msk (0xc0UL)
15089 #define PORT0_HWSEL_HW4_Pos (8UL)
15090 #define PORT0_HWSEL_HW4_Msk (0x300UL)
15091 #define PORT0_HWSEL_HW5_Pos (10UL)
15092 #define PORT0_HWSEL_HW5_Msk (0xc00UL)
15093 #define PORT0_HWSEL_HW6_Pos (12UL)
15094 #define PORT0_HWSEL_HW6_Msk (0x3000UL)
15095 #define PORT0_HWSEL_HW7_Pos (14UL)
15096 #define PORT0_HWSEL_HW7_Msk (0xc000UL)
15097 #define PORT0_HWSEL_HW8_Pos (16UL)
15098 #define PORT0_HWSEL_HW8_Msk (0x30000UL)
15099 #define PORT0_HWSEL_HW9_Pos (18UL)
15100 #define PORT0_HWSEL_HW9_Msk (0xc0000UL)
15101 #define PORT0_HWSEL_HW10_Pos (20UL)
15102 #define PORT0_HWSEL_HW10_Msk (0x300000UL)
15103 #define PORT0_HWSEL_HW11_Pos (22UL)
15104 #define PORT0_HWSEL_HW11_Msk (0xc00000UL)
15105 #define PORT0_HWSEL_HW12_Pos (24UL)
15106 #define PORT0_HWSEL_HW12_Msk (0x3000000UL)
15107 #define PORT0_HWSEL_HW13_Pos (26UL)
15108 #define PORT0_HWSEL_HW13_Msk (0xc000000UL)
15109 #define PORT0_HWSEL_HW14_Pos (28UL)
15110 #define PORT0_HWSEL_HW14_Msk (0x30000000UL)
15111 #define PORT0_HWSEL_HW15_Pos (30UL)
15112 #define PORT0_HWSEL_HW15_Msk (0xc0000000UL)
15115 /* ================================================================================ */
15116 /* ================ struct 'PORT1' Position & Mask ================ */
15117 /* ================================================================================ */
15118 
15119 
15120 /* ---------------------------------- PORT1_OUT --------------------------------- */
15121 #define PORT1_OUT_P0_Pos (0UL)
15122 #define PORT1_OUT_P0_Msk (0x1UL)
15123 #define PORT1_OUT_P1_Pos (1UL)
15124 #define PORT1_OUT_P1_Msk (0x2UL)
15125 #define PORT1_OUT_P2_Pos (2UL)
15126 #define PORT1_OUT_P2_Msk (0x4UL)
15127 #define PORT1_OUT_P3_Pos (3UL)
15128 #define PORT1_OUT_P3_Msk (0x8UL)
15129 #define PORT1_OUT_P4_Pos (4UL)
15130 #define PORT1_OUT_P4_Msk (0x10UL)
15131 #define PORT1_OUT_P5_Pos (5UL)
15132 #define PORT1_OUT_P5_Msk (0x20UL)
15133 #define PORT1_OUT_P6_Pos (6UL)
15134 #define PORT1_OUT_P6_Msk (0x40UL)
15135 #define PORT1_OUT_P7_Pos (7UL)
15136 #define PORT1_OUT_P7_Msk (0x80UL)
15137 #define PORT1_OUT_P8_Pos (8UL)
15138 #define PORT1_OUT_P8_Msk (0x100UL)
15139 #define PORT1_OUT_P9_Pos (9UL)
15140 #define PORT1_OUT_P9_Msk (0x200UL)
15141 #define PORT1_OUT_P10_Pos (10UL)
15142 #define PORT1_OUT_P10_Msk (0x400UL)
15143 #define PORT1_OUT_P11_Pos (11UL)
15144 #define PORT1_OUT_P11_Msk (0x800UL)
15145 #define PORT1_OUT_P12_Pos (12UL)
15146 #define PORT1_OUT_P12_Msk (0x1000UL)
15147 #define PORT1_OUT_P13_Pos (13UL)
15148 #define PORT1_OUT_P13_Msk (0x2000UL)
15149 #define PORT1_OUT_P14_Pos (14UL)
15150 #define PORT1_OUT_P14_Msk (0x4000UL)
15151 #define PORT1_OUT_P15_Pos (15UL)
15152 #define PORT1_OUT_P15_Msk (0x8000UL)
15154 /* ---------------------------------- PORT1_OMR --------------------------------- */
15155 #define PORT1_OMR_PS0_Pos (0UL)
15156 #define PORT1_OMR_PS0_Msk (0x1UL)
15157 #define PORT1_OMR_PS1_Pos (1UL)
15158 #define PORT1_OMR_PS1_Msk (0x2UL)
15159 #define PORT1_OMR_PS2_Pos (2UL)
15160 #define PORT1_OMR_PS2_Msk (0x4UL)
15161 #define PORT1_OMR_PS3_Pos (3UL)
15162 #define PORT1_OMR_PS3_Msk (0x8UL)
15163 #define PORT1_OMR_PS4_Pos (4UL)
15164 #define PORT1_OMR_PS4_Msk (0x10UL)
15165 #define PORT1_OMR_PS5_Pos (5UL)
15166 #define PORT1_OMR_PS5_Msk (0x20UL)
15167 #define PORT1_OMR_PS6_Pos (6UL)
15168 #define PORT1_OMR_PS6_Msk (0x40UL)
15169 #define PORT1_OMR_PS7_Pos (7UL)
15170 #define PORT1_OMR_PS7_Msk (0x80UL)
15171 #define PORT1_OMR_PS8_Pos (8UL)
15172 #define PORT1_OMR_PS8_Msk (0x100UL)
15173 #define PORT1_OMR_PS9_Pos (9UL)
15174 #define PORT1_OMR_PS9_Msk (0x200UL)
15175 #define PORT1_OMR_PS10_Pos (10UL)
15176 #define PORT1_OMR_PS10_Msk (0x400UL)
15177 #define PORT1_OMR_PS11_Pos (11UL)
15178 #define PORT1_OMR_PS11_Msk (0x800UL)
15179 #define PORT1_OMR_PS12_Pos (12UL)
15180 #define PORT1_OMR_PS12_Msk (0x1000UL)
15181 #define PORT1_OMR_PS13_Pos (13UL)
15182 #define PORT1_OMR_PS13_Msk (0x2000UL)
15183 #define PORT1_OMR_PS14_Pos (14UL)
15184 #define PORT1_OMR_PS14_Msk (0x4000UL)
15185 #define PORT1_OMR_PS15_Pos (15UL)
15186 #define PORT1_OMR_PS15_Msk (0x8000UL)
15187 #define PORT1_OMR_PR0_Pos (16UL)
15188 #define PORT1_OMR_PR0_Msk (0x10000UL)
15189 #define PORT1_OMR_PR1_Pos (17UL)
15190 #define PORT1_OMR_PR1_Msk (0x20000UL)
15191 #define PORT1_OMR_PR2_Pos (18UL)
15192 #define PORT1_OMR_PR2_Msk (0x40000UL)
15193 #define PORT1_OMR_PR3_Pos (19UL)
15194 #define PORT1_OMR_PR3_Msk (0x80000UL)
15195 #define PORT1_OMR_PR4_Pos (20UL)
15196 #define PORT1_OMR_PR4_Msk (0x100000UL)
15197 #define PORT1_OMR_PR5_Pos (21UL)
15198 #define PORT1_OMR_PR5_Msk (0x200000UL)
15199 #define PORT1_OMR_PR6_Pos (22UL)
15200 #define PORT1_OMR_PR6_Msk (0x400000UL)
15201 #define PORT1_OMR_PR7_Pos (23UL)
15202 #define PORT1_OMR_PR7_Msk (0x800000UL)
15203 #define PORT1_OMR_PR8_Pos (24UL)
15204 #define PORT1_OMR_PR8_Msk (0x1000000UL)
15205 #define PORT1_OMR_PR9_Pos (25UL)
15206 #define PORT1_OMR_PR9_Msk (0x2000000UL)
15207 #define PORT1_OMR_PR10_Pos (26UL)
15208 #define PORT1_OMR_PR10_Msk (0x4000000UL)
15209 #define PORT1_OMR_PR11_Pos (27UL)
15210 #define PORT1_OMR_PR11_Msk (0x8000000UL)
15211 #define PORT1_OMR_PR12_Pos (28UL)
15212 #define PORT1_OMR_PR12_Msk (0x10000000UL)
15213 #define PORT1_OMR_PR13_Pos (29UL)
15214 #define PORT1_OMR_PR13_Msk (0x20000000UL)
15215 #define PORT1_OMR_PR14_Pos (30UL)
15216 #define PORT1_OMR_PR14_Msk (0x40000000UL)
15217 #define PORT1_OMR_PR15_Pos (31UL)
15218 #define PORT1_OMR_PR15_Msk (0x80000000UL)
15220 /* --------------------------------- PORT1_IOCR0 -------------------------------- */
15221 #define PORT1_IOCR0_PC0_Pos (3UL)
15222 #define PORT1_IOCR0_PC0_Msk (0xf8UL)
15223 #define PORT1_IOCR0_PC1_Pos (11UL)
15224 #define PORT1_IOCR0_PC1_Msk (0xf800UL)
15225 #define PORT1_IOCR0_PC2_Pos (19UL)
15226 #define PORT1_IOCR0_PC2_Msk (0xf80000UL)
15227 #define PORT1_IOCR0_PC3_Pos (27UL)
15228 #define PORT1_IOCR0_PC3_Msk (0xf8000000UL)
15230 /* --------------------------------- PORT1_IOCR4 -------------------------------- */
15231 #define PORT1_IOCR4_PC4_Pos (3UL)
15232 #define PORT1_IOCR4_PC4_Msk (0xf8UL)
15233 #define PORT1_IOCR4_PC5_Pos (11UL)
15234 #define PORT1_IOCR4_PC5_Msk (0xf800UL)
15235 #define PORT1_IOCR4_PC6_Pos (19UL)
15236 #define PORT1_IOCR4_PC6_Msk (0xf80000UL)
15237 #define PORT1_IOCR4_PC7_Pos (27UL)
15238 #define PORT1_IOCR4_PC7_Msk (0xf8000000UL)
15240 /* --------------------------------- PORT1_IOCR8 -------------------------------- */
15241 #define PORT1_IOCR8_PC8_Pos (3UL)
15242 #define PORT1_IOCR8_PC8_Msk (0xf8UL)
15243 #define PORT1_IOCR8_PC9_Pos (11UL)
15244 #define PORT1_IOCR8_PC9_Msk (0xf800UL)
15245 #define PORT1_IOCR8_PC10_Pos (19UL)
15246 #define PORT1_IOCR8_PC10_Msk (0xf80000UL)
15247 #define PORT1_IOCR8_PC11_Pos (27UL)
15248 #define PORT1_IOCR8_PC11_Msk (0xf8000000UL)
15250 /* -------------------------------- PORT1_IOCR12 -------------------------------- */
15251 #define PORT1_IOCR12_PC12_Pos (3UL)
15252 #define PORT1_IOCR12_PC12_Msk (0xf8UL)
15253 #define PORT1_IOCR12_PC13_Pos (11UL)
15254 #define PORT1_IOCR12_PC13_Msk (0xf800UL)
15255 #define PORT1_IOCR12_PC14_Pos (19UL)
15256 #define PORT1_IOCR12_PC14_Msk (0xf80000UL)
15257 #define PORT1_IOCR12_PC15_Pos (27UL)
15258 #define PORT1_IOCR12_PC15_Msk (0xf8000000UL)
15260 /* ---------------------------------- PORT1_IN ---------------------------------- */
15261 #define PORT1_IN_P0_Pos (0UL)
15262 #define PORT1_IN_P0_Msk (0x1UL)
15263 #define PORT1_IN_P1_Pos (1UL)
15264 #define PORT1_IN_P1_Msk (0x2UL)
15265 #define PORT1_IN_P2_Pos (2UL)
15266 #define PORT1_IN_P2_Msk (0x4UL)
15267 #define PORT1_IN_P3_Pos (3UL)
15268 #define PORT1_IN_P3_Msk (0x8UL)
15269 #define PORT1_IN_P4_Pos (4UL)
15270 #define PORT1_IN_P4_Msk (0x10UL)
15271 #define PORT1_IN_P5_Pos (5UL)
15272 #define PORT1_IN_P5_Msk (0x20UL)
15273 #define PORT1_IN_P6_Pos (6UL)
15274 #define PORT1_IN_P6_Msk (0x40UL)
15275 #define PORT1_IN_P7_Pos (7UL)
15276 #define PORT1_IN_P7_Msk (0x80UL)
15277 #define PORT1_IN_P8_Pos (8UL)
15278 #define PORT1_IN_P8_Msk (0x100UL)
15279 #define PORT1_IN_P9_Pos (9UL)
15280 #define PORT1_IN_P9_Msk (0x200UL)
15281 #define PORT1_IN_P10_Pos (10UL)
15282 #define PORT1_IN_P10_Msk (0x400UL)
15283 #define PORT1_IN_P11_Pos (11UL)
15284 #define PORT1_IN_P11_Msk (0x800UL)
15285 #define PORT1_IN_P12_Pos (12UL)
15286 #define PORT1_IN_P12_Msk (0x1000UL)
15287 #define PORT1_IN_P13_Pos (13UL)
15288 #define PORT1_IN_P13_Msk (0x2000UL)
15289 #define PORT1_IN_P14_Pos (14UL)
15290 #define PORT1_IN_P14_Msk (0x4000UL)
15291 #define PORT1_IN_P15_Pos (15UL)
15292 #define PORT1_IN_P15_Msk (0x8000UL)
15294 /* --------------------------------- PORT1_PDR0 --------------------------------- */
15295 #define PORT1_PDR0_PD0_Pos (0UL)
15296 #define PORT1_PDR0_PD0_Msk (0x7UL)
15297 #define PORT1_PDR0_PD1_Pos (4UL)
15298 #define PORT1_PDR0_PD1_Msk (0x70UL)
15299 #define PORT1_PDR0_PD2_Pos (8UL)
15300 #define PORT1_PDR0_PD2_Msk (0x700UL)
15301 #define PORT1_PDR0_PD3_Pos (12UL)
15302 #define PORT1_PDR0_PD3_Msk (0x7000UL)
15303 #define PORT1_PDR0_PD4_Pos (16UL)
15304 #define PORT1_PDR0_PD4_Msk (0x70000UL)
15305 #define PORT1_PDR0_PD5_Pos (20UL)
15306 #define PORT1_PDR0_PD5_Msk (0x700000UL)
15307 #define PORT1_PDR0_PD6_Pos (24UL)
15308 #define PORT1_PDR0_PD6_Msk (0x7000000UL)
15309 #define PORT1_PDR0_PD7_Pos (28UL)
15310 #define PORT1_PDR0_PD7_Msk (0x70000000UL)
15312 /* --------------------------------- PORT1_PDR1 --------------------------------- */
15313 #define PORT1_PDR1_PD8_Pos (0UL)
15314 #define PORT1_PDR1_PD8_Msk (0x7UL)
15315 #define PORT1_PDR1_PD9_Pos (4UL)
15316 #define PORT1_PDR1_PD9_Msk (0x70UL)
15317 #define PORT1_PDR1_PD10_Pos (8UL)
15318 #define PORT1_PDR1_PD10_Msk (0x700UL)
15319 #define PORT1_PDR1_PD11_Pos (12UL)
15320 #define PORT1_PDR1_PD11_Msk (0x7000UL)
15321 #define PORT1_PDR1_PD12_Pos (16UL)
15322 #define PORT1_PDR1_PD12_Msk (0x70000UL)
15323 #define PORT1_PDR1_PD13_Pos (20UL)
15324 #define PORT1_PDR1_PD13_Msk (0x700000UL)
15325 #define PORT1_PDR1_PD14_Pos (24UL)
15326 #define PORT1_PDR1_PD14_Msk (0x7000000UL)
15327 #define PORT1_PDR1_PD15_Pos (28UL)
15328 #define PORT1_PDR1_PD15_Msk (0x70000000UL)
15330 /* --------------------------------- PORT1_PDISC -------------------------------- */
15331 #define PORT1_PDISC_PDIS0_Pos (0UL)
15332 #define PORT1_PDISC_PDIS0_Msk (0x1UL)
15333 #define PORT1_PDISC_PDIS1_Pos (1UL)
15334 #define PORT1_PDISC_PDIS1_Msk (0x2UL)
15335 #define PORT1_PDISC_PDIS2_Pos (2UL)
15336 #define PORT1_PDISC_PDIS2_Msk (0x4UL)
15337 #define PORT1_PDISC_PDIS3_Pos (3UL)
15338 #define PORT1_PDISC_PDIS3_Msk (0x8UL)
15339 #define PORT1_PDISC_PDIS4_Pos (4UL)
15340 #define PORT1_PDISC_PDIS4_Msk (0x10UL)
15341 #define PORT1_PDISC_PDIS5_Pos (5UL)
15342 #define PORT1_PDISC_PDIS5_Msk (0x20UL)
15343 #define PORT1_PDISC_PDIS6_Pos (6UL)
15344 #define PORT1_PDISC_PDIS6_Msk (0x40UL)
15345 #define PORT1_PDISC_PDIS7_Pos (7UL)
15346 #define PORT1_PDISC_PDIS7_Msk (0x80UL)
15347 #define PORT1_PDISC_PDIS8_Pos (8UL)
15348 #define PORT1_PDISC_PDIS8_Msk (0x100UL)
15349 #define PORT1_PDISC_PDIS9_Pos (9UL)
15350 #define PORT1_PDISC_PDIS9_Msk (0x200UL)
15351 #define PORT1_PDISC_PDIS10_Pos (10UL)
15352 #define PORT1_PDISC_PDIS10_Msk (0x400UL)
15353 #define PORT1_PDISC_PDIS11_Pos (11UL)
15354 #define PORT1_PDISC_PDIS11_Msk (0x800UL)
15355 #define PORT1_PDISC_PDIS12_Pos (12UL)
15356 #define PORT1_PDISC_PDIS12_Msk (0x1000UL)
15357 #define PORT1_PDISC_PDIS13_Pos (13UL)
15358 #define PORT1_PDISC_PDIS13_Msk (0x2000UL)
15359 #define PORT1_PDISC_PDIS14_Pos (14UL)
15360 #define PORT1_PDISC_PDIS14_Msk (0x4000UL)
15361 #define PORT1_PDISC_PDIS15_Pos (15UL)
15362 #define PORT1_PDISC_PDIS15_Msk (0x8000UL)
15364 /* ---------------------------------- PORT1_PPS --------------------------------- */
15365 #define PORT1_PPS_PPS0_Pos (0UL)
15366 #define PORT1_PPS_PPS0_Msk (0x1UL)
15367 #define PORT1_PPS_PPS1_Pos (1UL)
15368 #define PORT1_PPS_PPS1_Msk (0x2UL)
15369 #define PORT1_PPS_PPS2_Pos (2UL)
15370 #define PORT1_PPS_PPS2_Msk (0x4UL)
15371 #define PORT1_PPS_PPS3_Pos (3UL)
15372 #define PORT1_PPS_PPS3_Msk (0x8UL)
15373 #define PORT1_PPS_PPS4_Pos (4UL)
15374 #define PORT1_PPS_PPS4_Msk (0x10UL)
15375 #define PORT1_PPS_PPS5_Pos (5UL)
15376 #define PORT1_PPS_PPS5_Msk (0x20UL)
15377 #define PORT1_PPS_PPS6_Pos (6UL)
15378 #define PORT1_PPS_PPS6_Msk (0x40UL)
15379 #define PORT1_PPS_PPS7_Pos (7UL)
15380 #define PORT1_PPS_PPS7_Msk (0x80UL)
15381 #define PORT1_PPS_PPS8_Pos (8UL)
15382 #define PORT1_PPS_PPS8_Msk (0x100UL)
15383 #define PORT1_PPS_PPS9_Pos (9UL)
15384 #define PORT1_PPS_PPS9_Msk (0x200UL)
15385 #define PORT1_PPS_PPS10_Pos (10UL)
15386 #define PORT1_PPS_PPS10_Msk (0x400UL)
15387 #define PORT1_PPS_PPS11_Pos (11UL)
15388 #define PORT1_PPS_PPS11_Msk (0x800UL)
15389 #define PORT1_PPS_PPS12_Pos (12UL)
15390 #define PORT1_PPS_PPS12_Msk (0x1000UL)
15391 #define PORT1_PPS_PPS13_Pos (13UL)
15392 #define PORT1_PPS_PPS13_Msk (0x2000UL)
15393 #define PORT1_PPS_PPS14_Pos (14UL)
15394 #define PORT1_PPS_PPS14_Msk (0x4000UL)
15395 #define PORT1_PPS_PPS15_Pos (15UL)
15396 #define PORT1_PPS_PPS15_Msk (0x8000UL)
15398 /* --------------------------------- PORT1_HWSEL -------------------------------- */
15399 #define PORT1_HWSEL_HW0_Pos (0UL)
15400 #define PORT1_HWSEL_HW0_Msk (0x3UL)
15401 #define PORT1_HWSEL_HW1_Pos (2UL)
15402 #define PORT1_HWSEL_HW1_Msk (0xcUL)
15403 #define PORT1_HWSEL_HW2_Pos (4UL)
15404 #define PORT1_HWSEL_HW2_Msk (0x30UL)
15405 #define PORT1_HWSEL_HW3_Pos (6UL)
15406 #define PORT1_HWSEL_HW3_Msk (0xc0UL)
15407 #define PORT1_HWSEL_HW4_Pos (8UL)
15408 #define PORT1_HWSEL_HW4_Msk (0x300UL)
15409 #define PORT1_HWSEL_HW5_Pos (10UL)
15410 #define PORT1_HWSEL_HW5_Msk (0xc00UL)
15411 #define PORT1_HWSEL_HW6_Pos (12UL)
15412 #define PORT1_HWSEL_HW6_Msk (0x3000UL)
15413 #define PORT1_HWSEL_HW7_Pos (14UL)
15414 #define PORT1_HWSEL_HW7_Msk (0xc000UL)
15415 #define PORT1_HWSEL_HW8_Pos (16UL)
15416 #define PORT1_HWSEL_HW8_Msk (0x30000UL)
15417 #define PORT1_HWSEL_HW9_Pos (18UL)
15418 #define PORT1_HWSEL_HW9_Msk (0xc0000UL)
15419 #define PORT1_HWSEL_HW10_Pos (20UL)
15420 #define PORT1_HWSEL_HW10_Msk (0x300000UL)
15421 #define PORT1_HWSEL_HW11_Pos (22UL)
15422 #define PORT1_HWSEL_HW11_Msk (0xc00000UL)
15423 #define PORT1_HWSEL_HW12_Pos (24UL)
15424 #define PORT1_HWSEL_HW12_Msk (0x3000000UL)
15425 #define PORT1_HWSEL_HW13_Pos (26UL)
15426 #define PORT1_HWSEL_HW13_Msk (0xc000000UL)
15427 #define PORT1_HWSEL_HW14_Pos (28UL)
15428 #define PORT1_HWSEL_HW14_Msk (0x30000000UL)
15429 #define PORT1_HWSEL_HW15_Pos (30UL)
15430 #define PORT1_HWSEL_HW15_Msk (0xc0000000UL)
15433 /* ================================================================================ */
15434 /* ================ struct 'PORT2' Position & Mask ================ */
15435 /* ================================================================================ */
15436 
15437 
15438 /* ---------------------------------- PORT2_OUT --------------------------------- */
15439 #define PORT2_OUT_P0_Pos (0UL)
15440 #define PORT2_OUT_P0_Msk (0x1UL)
15441 #define PORT2_OUT_P1_Pos (1UL)
15442 #define PORT2_OUT_P1_Msk (0x2UL)
15443 #define PORT2_OUT_P2_Pos (2UL)
15444 #define PORT2_OUT_P2_Msk (0x4UL)
15445 #define PORT2_OUT_P3_Pos (3UL)
15446 #define PORT2_OUT_P3_Msk (0x8UL)
15447 #define PORT2_OUT_P4_Pos (4UL)
15448 #define PORT2_OUT_P4_Msk (0x10UL)
15449 #define PORT2_OUT_P5_Pos (5UL)
15450 #define PORT2_OUT_P5_Msk (0x20UL)
15451 #define PORT2_OUT_P6_Pos (6UL)
15452 #define PORT2_OUT_P6_Msk (0x40UL)
15453 #define PORT2_OUT_P7_Pos (7UL)
15454 #define PORT2_OUT_P7_Msk (0x80UL)
15455 #define PORT2_OUT_P8_Pos (8UL)
15456 #define PORT2_OUT_P8_Msk (0x100UL)
15457 #define PORT2_OUT_P9_Pos (9UL)
15458 #define PORT2_OUT_P9_Msk (0x200UL)
15459 #define PORT2_OUT_P10_Pos (10UL)
15460 #define PORT2_OUT_P10_Msk (0x400UL)
15461 #define PORT2_OUT_P11_Pos (11UL)
15462 #define PORT2_OUT_P11_Msk (0x800UL)
15463 #define PORT2_OUT_P12_Pos (12UL)
15464 #define PORT2_OUT_P12_Msk (0x1000UL)
15465 #define PORT2_OUT_P13_Pos (13UL)
15466 #define PORT2_OUT_P13_Msk (0x2000UL)
15467 #define PORT2_OUT_P14_Pos (14UL)
15468 #define PORT2_OUT_P14_Msk (0x4000UL)
15469 #define PORT2_OUT_P15_Pos (15UL)
15470 #define PORT2_OUT_P15_Msk (0x8000UL)
15472 /* ---------------------------------- PORT2_OMR --------------------------------- */
15473 #define PORT2_OMR_PS0_Pos (0UL)
15474 #define PORT2_OMR_PS0_Msk (0x1UL)
15475 #define PORT2_OMR_PS1_Pos (1UL)
15476 #define PORT2_OMR_PS1_Msk (0x2UL)
15477 #define PORT2_OMR_PS2_Pos (2UL)
15478 #define PORT2_OMR_PS2_Msk (0x4UL)
15479 #define PORT2_OMR_PS3_Pos (3UL)
15480 #define PORT2_OMR_PS3_Msk (0x8UL)
15481 #define PORT2_OMR_PS4_Pos (4UL)
15482 #define PORT2_OMR_PS4_Msk (0x10UL)
15483 #define PORT2_OMR_PS5_Pos (5UL)
15484 #define PORT2_OMR_PS5_Msk (0x20UL)
15485 #define PORT2_OMR_PS6_Pos (6UL)
15486 #define PORT2_OMR_PS6_Msk (0x40UL)
15487 #define PORT2_OMR_PS7_Pos (7UL)
15488 #define PORT2_OMR_PS7_Msk (0x80UL)
15489 #define PORT2_OMR_PS8_Pos (8UL)
15490 #define PORT2_OMR_PS8_Msk (0x100UL)
15491 #define PORT2_OMR_PS9_Pos (9UL)
15492 #define PORT2_OMR_PS9_Msk (0x200UL)
15493 #define PORT2_OMR_PS10_Pos (10UL)
15494 #define PORT2_OMR_PS10_Msk (0x400UL)
15495 #define PORT2_OMR_PS11_Pos (11UL)
15496 #define PORT2_OMR_PS11_Msk (0x800UL)
15497 #define PORT2_OMR_PS12_Pos (12UL)
15498 #define PORT2_OMR_PS12_Msk (0x1000UL)
15499 #define PORT2_OMR_PS13_Pos (13UL)
15500 #define PORT2_OMR_PS13_Msk (0x2000UL)
15501 #define PORT2_OMR_PS14_Pos (14UL)
15502 #define PORT2_OMR_PS14_Msk (0x4000UL)
15503 #define PORT2_OMR_PS15_Pos (15UL)
15504 #define PORT2_OMR_PS15_Msk (0x8000UL)
15505 #define PORT2_OMR_PR0_Pos (16UL)
15506 #define PORT2_OMR_PR0_Msk (0x10000UL)
15507 #define PORT2_OMR_PR1_Pos (17UL)
15508 #define PORT2_OMR_PR1_Msk (0x20000UL)
15509 #define PORT2_OMR_PR2_Pos (18UL)
15510 #define PORT2_OMR_PR2_Msk (0x40000UL)
15511 #define PORT2_OMR_PR3_Pos (19UL)
15512 #define PORT2_OMR_PR3_Msk (0x80000UL)
15513 #define PORT2_OMR_PR4_Pos (20UL)
15514 #define PORT2_OMR_PR4_Msk (0x100000UL)
15515 #define PORT2_OMR_PR5_Pos (21UL)
15516 #define PORT2_OMR_PR5_Msk (0x200000UL)
15517 #define PORT2_OMR_PR6_Pos (22UL)
15518 #define PORT2_OMR_PR6_Msk (0x400000UL)
15519 #define PORT2_OMR_PR7_Pos (23UL)
15520 #define PORT2_OMR_PR7_Msk (0x800000UL)
15521 #define PORT2_OMR_PR8_Pos (24UL)
15522 #define PORT2_OMR_PR8_Msk (0x1000000UL)
15523 #define PORT2_OMR_PR9_Pos (25UL)
15524 #define PORT2_OMR_PR9_Msk (0x2000000UL)
15525 #define PORT2_OMR_PR10_Pos (26UL)
15526 #define PORT2_OMR_PR10_Msk (0x4000000UL)
15527 #define PORT2_OMR_PR11_Pos (27UL)
15528 #define PORT2_OMR_PR11_Msk (0x8000000UL)
15529 #define PORT2_OMR_PR12_Pos (28UL)
15530 #define PORT2_OMR_PR12_Msk (0x10000000UL)
15531 #define PORT2_OMR_PR13_Pos (29UL)
15532 #define PORT2_OMR_PR13_Msk (0x20000000UL)
15533 #define PORT2_OMR_PR14_Pos (30UL)
15534 #define PORT2_OMR_PR14_Msk (0x40000000UL)
15535 #define PORT2_OMR_PR15_Pos (31UL)
15536 #define PORT2_OMR_PR15_Msk (0x80000000UL)
15538 /* --------------------------------- PORT2_IOCR0 -------------------------------- */
15539 #define PORT2_IOCR0_PC0_Pos (3UL)
15540 #define PORT2_IOCR0_PC0_Msk (0xf8UL)
15541 #define PORT2_IOCR0_PC1_Pos (11UL)
15542 #define PORT2_IOCR0_PC1_Msk (0xf800UL)
15543 #define PORT2_IOCR0_PC2_Pos (19UL)
15544 #define PORT2_IOCR0_PC2_Msk (0xf80000UL)
15545 #define PORT2_IOCR0_PC3_Pos (27UL)
15546 #define PORT2_IOCR0_PC3_Msk (0xf8000000UL)
15548 /* --------------------------------- PORT2_IOCR4 -------------------------------- */
15549 #define PORT2_IOCR4_PC4_Pos (3UL)
15550 #define PORT2_IOCR4_PC4_Msk (0xf8UL)
15551 #define PORT2_IOCR4_PC5_Pos (11UL)
15552 #define PORT2_IOCR4_PC5_Msk (0xf800UL)
15553 #define PORT2_IOCR4_PC6_Pos (19UL)
15554 #define PORT2_IOCR4_PC6_Msk (0xf80000UL)
15555 #define PORT2_IOCR4_PC7_Pos (27UL)
15556 #define PORT2_IOCR4_PC7_Msk (0xf8000000UL)
15558 /* --------------------------------- PORT2_IOCR8 -------------------------------- */
15559 #define PORT2_IOCR8_PC8_Pos (3UL)
15560 #define PORT2_IOCR8_PC8_Msk (0xf8UL)
15561 #define PORT2_IOCR8_PC9_Pos (11UL)
15562 #define PORT2_IOCR8_PC9_Msk (0xf800UL)
15563 #define PORT2_IOCR8_PC10_Pos (19UL)
15564 #define PORT2_IOCR8_PC10_Msk (0xf80000UL)
15565 #define PORT2_IOCR8_PC11_Pos (27UL)
15566 #define PORT2_IOCR8_PC11_Msk (0xf8000000UL)
15568 /* -------------------------------- PORT2_IOCR12 -------------------------------- */
15569 #define PORT2_IOCR12_PC12_Pos (3UL)
15570 #define PORT2_IOCR12_PC12_Msk (0xf8UL)
15571 #define PORT2_IOCR12_PC13_Pos (11UL)
15572 #define PORT2_IOCR12_PC13_Msk (0xf800UL)
15573 #define PORT2_IOCR12_PC14_Pos (19UL)
15574 #define PORT2_IOCR12_PC14_Msk (0xf80000UL)
15575 #define PORT2_IOCR12_PC15_Pos (27UL)
15576 #define PORT2_IOCR12_PC15_Msk (0xf8000000UL)
15578 /* ---------------------------------- PORT2_IN ---------------------------------- */
15579 #define PORT2_IN_P0_Pos (0UL)
15580 #define PORT2_IN_P0_Msk (0x1UL)
15581 #define PORT2_IN_P1_Pos (1UL)
15582 #define PORT2_IN_P1_Msk (0x2UL)
15583 #define PORT2_IN_P2_Pos (2UL)
15584 #define PORT2_IN_P2_Msk (0x4UL)
15585 #define PORT2_IN_P3_Pos (3UL)
15586 #define PORT2_IN_P3_Msk (0x8UL)
15587 #define PORT2_IN_P4_Pos (4UL)
15588 #define PORT2_IN_P4_Msk (0x10UL)
15589 #define PORT2_IN_P5_Pos (5UL)
15590 #define PORT2_IN_P5_Msk (0x20UL)
15591 #define PORT2_IN_P6_Pos (6UL)
15592 #define PORT2_IN_P6_Msk (0x40UL)
15593 #define PORT2_IN_P7_Pos (7UL)
15594 #define PORT2_IN_P7_Msk (0x80UL)
15595 #define PORT2_IN_P8_Pos (8UL)
15596 #define PORT2_IN_P8_Msk (0x100UL)
15597 #define PORT2_IN_P9_Pos (9UL)
15598 #define PORT2_IN_P9_Msk (0x200UL)
15599 #define PORT2_IN_P10_Pos (10UL)
15600 #define PORT2_IN_P10_Msk (0x400UL)
15601 #define PORT2_IN_P11_Pos (11UL)
15602 #define PORT2_IN_P11_Msk (0x800UL)
15603 #define PORT2_IN_P12_Pos (12UL)
15604 #define PORT2_IN_P12_Msk (0x1000UL)
15605 #define PORT2_IN_P13_Pos (13UL)
15606 #define PORT2_IN_P13_Msk (0x2000UL)
15607 #define PORT2_IN_P14_Pos (14UL)
15608 #define PORT2_IN_P14_Msk (0x4000UL)
15609 #define PORT2_IN_P15_Pos (15UL)
15610 #define PORT2_IN_P15_Msk (0x8000UL)
15612 /* --------------------------------- PORT2_PDR0 --------------------------------- */
15613 #define PORT2_PDR0_PD0_Pos (0UL)
15614 #define PORT2_PDR0_PD0_Msk (0x7UL)
15615 #define PORT2_PDR0_PD1_Pos (4UL)
15616 #define PORT2_PDR0_PD1_Msk (0x70UL)
15617 #define PORT2_PDR0_PD2_Pos (8UL)
15618 #define PORT2_PDR0_PD2_Msk (0x700UL)
15619 #define PORT2_PDR0_PD3_Pos (12UL)
15620 #define PORT2_PDR0_PD3_Msk (0x7000UL)
15621 #define PORT2_PDR0_PD4_Pos (16UL)
15622 #define PORT2_PDR0_PD4_Msk (0x70000UL)
15623 #define PORT2_PDR0_PD5_Pos (20UL)
15624 #define PORT2_PDR0_PD5_Msk (0x700000UL)
15625 #define PORT2_PDR0_PD6_Pos (24UL)
15626 #define PORT2_PDR0_PD6_Msk (0x7000000UL)
15627 #define PORT2_PDR0_PD7_Pos (28UL)
15628 #define PORT2_PDR0_PD7_Msk (0x70000000UL)
15630 /* --------------------------------- PORT2_PDR1 --------------------------------- */
15631 #define PORT2_PDR1_PD8_Pos (0UL)
15632 #define PORT2_PDR1_PD8_Msk (0x7UL)
15633 #define PORT2_PDR1_PD9_Pos (4UL)
15634 #define PORT2_PDR1_PD9_Msk (0x70UL)
15635 #define PORT2_PDR1_PD10_Pos (8UL)
15636 #define PORT2_PDR1_PD10_Msk (0x700UL)
15637 #define PORT2_PDR1_PD11_Pos (12UL)
15638 #define PORT2_PDR1_PD11_Msk (0x7000UL)
15639 #define PORT2_PDR1_PD12_Pos (16UL)
15640 #define PORT2_PDR1_PD12_Msk (0x70000UL)
15641 #define PORT2_PDR1_PD13_Pos (20UL)
15642 #define PORT2_PDR1_PD13_Msk (0x700000UL)
15643 #define PORT2_PDR1_PD14_Pos (24UL)
15644 #define PORT2_PDR1_PD14_Msk (0x7000000UL)
15645 #define PORT2_PDR1_PD15_Pos (28UL)
15646 #define PORT2_PDR1_PD15_Msk (0x70000000UL)
15648 /* --------------------------------- PORT2_PDISC -------------------------------- */
15649 #define PORT2_PDISC_PDIS0_Pos (0UL)
15650 #define PORT2_PDISC_PDIS0_Msk (0x1UL)
15651 #define PORT2_PDISC_PDIS1_Pos (1UL)
15652 #define PORT2_PDISC_PDIS1_Msk (0x2UL)
15653 #define PORT2_PDISC_PDIS2_Pos (2UL)
15654 #define PORT2_PDISC_PDIS2_Msk (0x4UL)
15655 #define PORT2_PDISC_PDIS3_Pos (3UL)
15656 #define PORT2_PDISC_PDIS3_Msk (0x8UL)
15657 #define PORT2_PDISC_PDIS4_Pos (4UL)
15658 #define PORT2_PDISC_PDIS4_Msk (0x10UL)
15659 #define PORT2_PDISC_PDIS5_Pos (5UL)
15660 #define PORT2_PDISC_PDIS5_Msk (0x20UL)
15661 #define PORT2_PDISC_PDIS6_Pos (6UL)
15662 #define PORT2_PDISC_PDIS6_Msk (0x40UL)
15663 #define PORT2_PDISC_PDIS7_Pos (7UL)
15664 #define PORT2_PDISC_PDIS7_Msk (0x80UL)
15665 #define PORT2_PDISC_PDIS8_Pos (8UL)
15666 #define PORT2_PDISC_PDIS8_Msk (0x100UL)
15667 #define PORT2_PDISC_PDIS9_Pos (9UL)
15668 #define PORT2_PDISC_PDIS9_Msk (0x200UL)
15669 #define PORT2_PDISC_PDIS10_Pos (10UL)
15670 #define PORT2_PDISC_PDIS10_Msk (0x400UL)
15671 #define PORT2_PDISC_PDIS11_Pos (11UL)
15672 #define PORT2_PDISC_PDIS11_Msk (0x800UL)
15673 #define PORT2_PDISC_PDIS12_Pos (12UL)
15674 #define PORT2_PDISC_PDIS12_Msk (0x1000UL)
15675 #define PORT2_PDISC_PDIS13_Pos (13UL)
15676 #define PORT2_PDISC_PDIS13_Msk (0x2000UL)
15677 #define PORT2_PDISC_PDIS14_Pos (14UL)
15678 #define PORT2_PDISC_PDIS14_Msk (0x4000UL)
15679 #define PORT2_PDISC_PDIS15_Pos (15UL)
15680 #define PORT2_PDISC_PDIS15_Msk (0x8000UL)
15682 /* ---------------------------------- PORT2_PPS --------------------------------- */
15683 #define PORT2_PPS_PPS0_Pos (0UL)
15684 #define PORT2_PPS_PPS0_Msk (0x1UL)
15685 #define PORT2_PPS_PPS1_Pos (1UL)
15686 #define PORT2_PPS_PPS1_Msk (0x2UL)
15687 #define PORT2_PPS_PPS2_Pos (2UL)
15688 #define PORT2_PPS_PPS2_Msk (0x4UL)
15689 #define PORT2_PPS_PPS3_Pos (3UL)
15690 #define PORT2_PPS_PPS3_Msk (0x8UL)
15691 #define PORT2_PPS_PPS4_Pos (4UL)
15692 #define PORT2_PPS_PPS4_Msk (0x10UL)
15693 #define PORT2_PPS_PPS5_Pos (5UL)
15694 #define PORT2_PPS_PPS5_Msk (0x20UL)
15695 #define PORT2_PPS_PPS6_Pos (6UL)
15696 #define PORT2_PPS_PPS6_Msk (0x40UL)
15697 #define PORT2_PPS_PPS7_Pos (7UL)
15698 #define PORT2_PPS_PPS7_Msk (0x80UL)
15699 #define PORT2_PPS_PPS8_Pos (8UL)
15700 #define PORT2_PPS_PPS8_Msk (0x100UL)
15701 #define PORT2_PPS_PPS9_Pos (9UL)
15702 #define PORT2_PPS_PPS9_Msk (0x200UL)
15703 #define PORT2_PPS_PPS10_Pos (10UL)
15704 #define PORT2_PPS_PPS10_Msk (0x400UL)
15705 #define PORT2_PPS_PPS11_Pos (11UL)
15706 #define PORT2_PPS_PPS11_Msk (0x800UL)
15707 #define PORT2_PPS_PPS12_Pos (12UL)
15708 #define PORT2_PPS_PPS12_Msk (0x1000UL)
15709 #define PORT2_PPS_PPS13_Pos (13UL)
15710 #define PORT2_PPS_PPS13_Msk (0x2000UL)
15711 #define PORT2_PPS_PPS14_Pos (14UL)
15712 #define PORT2_PPS_PPS14_Msk (0x4000UL)
15713 #define PORT2_PPS_PPS15_Pos (15UL)
15714 #define PORT2_PPS_PPS15_Msk (0x8000UL)
15716 /* --------------------------------- PORT2_HWSEL -------------------------------- */
15717 #define PORT2_HWSEL_HW0_Pos (0UL)
15718 #define PORT2_HWSEL_HW0_Msk (0x3UL)
15719 #define PORT2_HWSEL_HW1_Pos (2UL)
15720 #define PORT2_HWSEL_HW1_Msk (0xcUL)
15721 #define PORT2_HWSEL_HW2_Pos (4UL)
15722 #define PORT2_HWSEL_HW2_Msk (0x30UL)
15723 #define PORT2_HWSEL_HW3_Pos (6UL)
15724 #define PORT2_HWSEL_HW3_Msk (0xc0UL)
15725 #define PORT2_HWSEL_HW4_Pos (8UL)
15726 #define PORT2_HWSEL_HW4_Msk (0x300UL)
15727 #define PORT2_HWSEL_HW5_Pos (10UL)
15728 #define PORT2_HWSEL_HW5_Msk (0xc00UL)
15729 #define PORT2_HWSEL_HW6_Pos (12UL)
15730 #define PORT2_HWSEL_HW6_Msk (0x3000UL)
15731 #define PORT2_HWSEL_HW7_Pos (14UL)
15732 #define PORT2_HWSEL_HW7_Msk (0xc000UL)
15733 #define PORT2_HWSEL_HW8_Pos (16UL)
15734 #define PORT2_HWSEL_HW8_Msk (0x30000UL)
15735 #define PORT2_HWSEL_HW9_Pos (18UL)
15736 #define PORT2_HWSEL_HW9_Msk (0xc0000UL)
15737 #define PORT2_HWSEL_HW10_Pos (20UL)
15738 #define PORT2_HWSEL_HW10_Msk (0x300000UL)
15739 #define PORT2_HWSEL_HW11_Pos (22UL)
15740 #define PORT2_HWSEL_HW11_Msk (0xc00000UL)
15741 #define PORT2_HWSEL_HW12_Pos (24UL)
15742 #define PORT2_HWSEL_HW12_Msk (0x3000000UL)
15743 #define PORT2_HWSEL_HW13_Pos (26UL)
15744 #define PORT2_HWSEL_HW13_Msk (0xc000000UL)
15745 #define PORT2_HWSEL_HW14_Pos (28UL)
15746 #define PORT2_HWSEL_HW14_Msk (0x30000000UL)
15747 #define PORT2_HWSEL_HW15_Pos (30UL)
15748 #define PORT2_HWSEL_HW15_Msk (0xc0000000UL)
15751 /* ================================================================================ */
15752 /* ================ struct 'PORT3' Position & Mask ================ */
15753 /* ================================================================================ */
15754 
15755 
15756 /* ---------------------------------- PORT3_OUT --------------------------------- */
15757 #define PORT3_OUT_P0_Pos (0UL)
15758 #define PORT3_OUT_P0_Msk (0x1UL)
15759 #define PORT3_OUT_P1_Pos (1UL)
15760 #define PORT3_OUT_P1_Msk (0x2UL)
15761 #define PORT3_OUT_P2_Pos (2UL)
15762 #define PORT3_OUT_P2_Msk (0x4UL)
15763 #define PORT3_OUT_P3_Pos (3UL)
15764 #define PORT3_OUT_P3_Msk (0x8UL)
15765 #define PORT3_OUT_P4_Pos (4UL)
15766 #define PORT3_OUT_P4_Msk (0x10UL)
15767 #define PORT3_OUT_P5_Pos (5UL)
15768 #define PORT3_OUT_P5_Msk (0x20UL)
15769 #define PORT3_OUT_P6_Pos (6UL)
15770 #define PORT3_OUT_P6_Msk (0x40UL)
15771 #define PORT3_OUT_P7_Pos (7UL)
15772 #define PORT3_OUT_P7_Msk (0x80UL)
15773 #define PORT3_OUT_P8_Pos (8UL)
15774 #define PORT3_OUT_P8_Msk (0x100UL)
15775 #define PORT3_OUT_P9_Pos (9UL)
15776 #define PORT3_OUT_P9_Msk (0x200UL)
15777 #define PORT3_OUT_P10_Pos (10UL)
15778 #define PORT3_OUT_P10_Msk (0x400UL)
15779 #define PORT3_OUT_P11_Pos (11UL)
15780 #define PORT3_OUT_P11_Msk (0x800UL)
15781 #define PORT3_OUT_P12_Pos (12UL)
15782 #define PORT3_OUT_P12_Msk (0x1000UL)
15783 #define PORT3_OUT_P13_Pos (13UL)
15784 #define PORT3_OUT_P13_Msk (0x2000UL)
15785 #define PORT3_OUT_P14_Pos (14UL)
15786 #define PORT3_OUT_P14_Msk (0x4000UL)
15787 #define PORT3_OUT_P15_Pos (15UL)
15788 #define PORT3_OUT_P15_Msk (0x8000UL)
15790 /* ---------------------------------- PORT3_OMR --------------------------------- */
15791 #define PORT3_OMR_PS0_Pos (0UL)
15792 #define PORT3_OMR_PS0_Msk (0x1UL)
15793 #define PORT3_OMR_PS1_Pos (1UL)
15794 #define PORT3_OMR_PS1_Msk (0x2UL)
15795 #define PORT3_OMR_PS2_Pos (2UL)
15796 #define PORT3_OMR_PS2_Msk (0x4UL)
15797 #define PORT3_OMR_PS3_Pos (3UL)
15798 #define PORT3_OMR_PS3_Msk (0x8UL)
15799 #define PORT3_OMR_PS4_Pos (4UL)
15800 #define PORT3_OMR_PS4_Msk (0x10UL)
15801 #define PORT3_OMR_PS5_Pos (5UL)
15802 #define PORT3_OMR_PS5_Msk (0x20UL)
15803 #define PORT3_OMR_PS6_Pos (6UL)
15804 #define PORT3_OMR_PS6_Msk (0x40UL)
15805 #define PORT3_OMR_PS7_Pos (7UL)
15806 #define PORT3_OMR_PS7_Msk (0x80UL)
15807 #define PORT3_OMR_PS8_Pos (8UL)
15808 #define PORT3_OMR_PS8_Msk (0x100UL)
15809 #define PORT3_OMR_PS9_Pos (9UL)
15810 #define PORT3_OMR_PS9_Msk (0x200UL)
15811 #define PORT3_OMR_PS10_Pos (10UL)
15812 #define PORT3_OMR_PS10_Msk (0x400UL)
15813 #define PORT3_OMR_PS11_Pos (11UL)
15814 #define PORT3_OMR_PS11_Msk (0x800UL)
15815 #define PORT3_OMR_PS12_Pos (12UL)
15816 #define PORT3_OMR_PS12_Msk (0x1000UL)
15817 #define PORT3_OMR_PS13_Pos (13UL)
15818 #define PORT3_OMR_PS13_Msk (0x2000UL)
15819 #define PORT3_OMR_PS14_Pos (14UL)
15820 #define PORT3_OMR_PS14_Msk (0x4000UL)
15821 #define PORT3_OMR_PS15_Pos (15UL)
15822 #define PORT3_OMR_PS15_Msk (0x8000UL)
15823 #define PORT3_OMR_PR0_Pos (16UL)
15824 #define PORT3_OMR_PR0_Msk (0x10000UL)
15825 #define PORT3_OMR_PR1_Pos (17UL)
15826 #define PORT3_OMR_PR1_Msk (0x20000UL)
15827 #define PORT3_OMR_PR2_Pos (18UL)
15828 #define PORT3_OMR_PR2_Msk (0x40000UL)
15829 #define PORT3_OMR_PR3_Pos (19UL)
15830 #define PORT3_OMR_PR3_Msk (0x80000UL)
15831 #define PORT3_OMR_PR4_Pos (20UL)
15832 #define PORT3_OMR_PR4_Msk (0x100000UL)
15833 #define PORT3_OMR_PR5_Pos (21UL)
15834 #define PORT3_OMR_PR5_Msk (0x200000UL)
15835 #define PORT3_OMR_PR6_Pos (22UL)
15836 #define PORT3_OMR_PR6_Msk (0x400000UL)
15837 #define PORT3_OMR_PR7_Pos (23UL)
15838 #define PORT3_OMR_PR7_Msk (0x800000UL)
15839 #define PORT3_OMR_PR8_Pos (24UL)
15840 #define PORT3_OMR_PR8_Msk (0x1000000UL)
15841 #define PORT3_OMR_PR9_Pos (25UL)
15842 #define PORT3_OMR_PR9_Msk (0x2000000UL)
15843 #define PORT3_OMR_PR10_Pos (26UL)
15844 #define PORT3_OMR_PR10_Msk (0x4000000UL)
15845 #define PORT3_OMR_PR11_Pos (27UL)
15846 #define PORT3_OMR_PR11_Msk (0x8000000UL)
15847 #define PORT3_OMR_PR12_Pos (28UL)
15848 #define PORT3_OMR_PR12_Msk (0x10000000UL)
15849 #define PORT3_OMR_PR13_Pos (29UL)
15850 #define PORT3_OMR_PR13_Msk (0x20000000UL)
15851 #define PORT3_OMR_PR14_Pos (30UL)
15852 #define PORT3_OMR_PR14_Msk (0x40000000UL)
15853 #define PORT3_OMR_PR15_Pos (31UL)
15854 #define PORT3_OMR_PR15_Msk (0x80000000UL)
15856 /* --------------------------------- PORT3_IOCR0 -------------------------------- */
15857 #define PORT3_IOCR0_PC0_Pos (3UL)
15858 #define PORT3_IOCR0_PC0_Msk (0xf8UL)
15859 #define PORT3_IOCR0_PC1_Pos (11UL)
15860 #define PORT3_IOCR0_PC1_Msk (0xf800UL)
15861 #define PORT3_IOCR0_PC2_Pos (19UL)
15862 #define PORT3_IOCR0_PC2_Msk (0xf80000UL)
15863 #define PORT3_IOCR0_PC3_Pos (27UL)
15864 #define PORT3_IOCR0_PC3_Msk (0xf8000000UL)
15866 /* --------------------------------- PORT3_IOCR4 -------------------------------- */
15867 #define PORT3_IOCR4_PC4_Pos (3UL)
15868 #define PORT3_IOCR4_PC4_Msk (0xf8UL)
15869 #define PORT3_IOCR4_PC5_Pos (11UL)
15870 #define PORT3_IOCR4_PC5_Msk (0xf800UL)
15871 #define PORT3_IOCR4_PC6_Pos (19UL)
15872 #define PORT3_IOCR4_PC6_Msk (0xf80000UL)
15873 #define PORT3_IOCR4_PC7_Pos (27UL)
15874 #define PORT3_IOCR4_PC7_Msk (0xf8000000UL)
15876 /* --------------------------------- PORT3_IOCR8 -------------------------------- */
15877 #define PORT3_IOCR8_PC8_Pos (3UL)
15878 #define PORT3_IOCR8_PC8_Msk (0xf8UL)
15879 #define PORT3_IOCR8_PC9_Pos (11UL)
15880 #define PORT3_IOCR8_PC9_Msk (0xf800UL)
15881 #define PORT3_IOCR8_PC10_Pos (19UL)
15882 #define PORT3_IOCR8_PC10_Msk (0xf80000UL)
15883 #define PORT3_IOCR8_PC11_Pos (27UL)
15884 #define PORT3_IOCR8_PC11_Msk (0xf8000000UL)
15886 /* -------------------------------- PORT3_IOCR12 -------------------------------- */
15887 #define PORT3_IOCR12_PC12_Pos (3UL)
15888 #define PORT3_IOCR12_PC12_Msk (0xf8UL)
15889 #define PORT3_IOCR12_PC13_Pos (11UL)
15890 #define PORT3_IOCR12_PC13_Msk (0xf800UL)
15891 #define PORT3_IOCR12_PC14_Pos (19UL)
15892 #define PORT3_IOCR12_PC14_Msk (0xf80000UL)
15893 #define PORT3_IOCR12_PC15_Pos (27UL)
15894 #define PORT3_IOCR12_PC15_Msk (0xf8000000UL)
15896 /* ---------------------------------- PORT3_IN ---------------------------------- */
15897 #define PORT3_IN_P0_Pos (0UL)
15898 #define PORT3_IN_P0_Msk (0x1UL)
15899 #define PORT3_IN_P1_Pos (1UL)
15900 #define PORT3_IN_P1_Msk (0x2UL)
15901 #define PORT3_IN_P2_Pos (2UL)
15902 #define PORT3_IN_P2_Msk (0x4UL)
15903 #define PORT3_IN_P3_Pos (3UL)
15904 #define PORT3_IN_P3_Msk (0x8UL)
15905 #define PORT3_IN_P4_Pos (4UL)
15906 #define PORT3_IN_P4_Msk (0x10UL)
15907 #define PORT3_IN_P5_Pos (5UL)
15908 #define PORT3_IN_P5_Msk (0x20UL)
15909 #define PORT3_IN_P6_Pos (6UL)
15910 #define PORT3_IN_P6_Msk (0x40UL)
15911 #define PORT3_IN_P7_Pos (7UL)
15912 #define PORT3_IN_P7_Msk (0x80UL)
15913 #define PORT3_IN_P8_Pos (8UL)
15914 #define PORT3_IN_P8_Msk (0x100UL)
15915 #define PORT3_IN_P9_Pos (9UL)
15916 #define PORT3_IN_P9_Msk (0x200UL)
15917 #define PORT3_IN_P10_Pos (10UL)
15918 #define PORT3_IN_P10_Msk (0x400UL)
15919 #define PORT3_IN_P11_Pos (11UL)
15920 #define PORT3_IN_P11_Msk (0x800UL)
15921 #define PORT3_IN_P12_Pos (12UL)
15922 #define PORT3_IN_P12_Msk (0x1000UL)
15923 #define PORT3_IN_P13_Pos (13UL)
15924 #define PORT3_IN_P13_Msk (0x2000UL)
15925 #define PORT3_IN_P14_Pos (14UL)
15926 #define PORT3_IN_P14_Msk (0x4000UL)
15927 #define PORT3_IN_P15_Pos (15UL)
15928 #define PORT3_IN_P15_Msk (0x8000UL)
15930 /* --------------------------------- PORT3_PDR0 --------------------------------- */
15931 #define PORT3_PDR0_PD0_Pos (0UL)
15932 #define PORT3_PDR0_PD0_Msk (0x7UL)
15933 #define PORT3_PDR0_PD1_Pos (4UL)
15934 #define PORT3_PDR0_PD1_Msk (0x70UL)
15935 #define PORT3_PDR0_PD2_Pos (8UL)
15936 #define PORT3_PDR0_PD2_Msk (0x700UL)
15937 #define PORT3_PDR0_PD3_Pos (12UL)
15938 #define PORT3_PDR0_PD3_Msk (0x7000UL)
15939 #define PORT3_PDR0_PD4_Pos (16UL)
15940 #define PORT3_PDR0_PD4_Msk (0x70000UL)
15941 #define PORT3_PDR0_PD5_Pos (20UL)
15942 #define PORT3_PDR0_PD5_Msk (0x700000UL)
15943 #define PORT3_PDR0_PD6_Pos (24UL)
15944 #define PORT3_PDR0_PD6_Msk (0x7000000UL)
15945 #define PORT3_PDR0_PD7_Pos (28UL)
15946 #define PORT3_PDR0_PD7_Msk (0x70000000UL)
15948 /* --------------------------------- PORT3_PDR1 --------------------------------- */
15949 #define PORT3_PDR1_PD8_Pos (0UL)
15950 #define PORT3_PDR1_PD8_Msk (0x7UL)
15951 #define PORT3_PDR1_PD9_Pos (4UL)
15952 #define PORT3_PDR1_PD9_Msk (0x70UL)
15953 #define PORT3_PDR1_PD10_Pos (8UL)
15954 #define PORT3_PDR1_PD10_Msk (0x700UL)
15955 #define PORT3_PDR1_PD11_Pos (12UL)
15956 #define PORT3_PDR1_PD11_Msk (0x7000UL)
15957 #define PORT3_PDR1_PD12_Pos (16UL)
15958 #define PORT3_PDR1_PD12_Msk (0x70000UL)
15959 #define PORT3_PDR1_PD13_Pos (20UL)
15960 #define PORT3_PDR1_PD13_Msk (0x700000UL)
15961 #define PORT3_PDR1_PD14_Pos (24UL)
15962 #define PORT3_PDR1_PD14_Msk (0x7000000UL)
15963 #define PORT3_PDR1_PD15_Pos (28UL)
15964 #define PORT3_PDR1_PD15_Msk (0x70000000UL)
15966 /* --------------------------------- PORT3_PDISC -------------------------------- */
15967 #define PORT3_PDISC_PDIS0_Pos (0UL)
15968 #define PORT3_PDISC_PDIS0_Msk (0x1UL)
15969 #define PORT3_PDISC_PDIS1_Pos (1UL)
15970 #define PORT3_PDISC_PDIS1_Msk (0x2UL)
15971 #define PORT3_PDISC_PDIS2_Pos (2UL)
15972 #define PORT3_PDISC_PDIS2_Msk (0x4UL)
15973 #define PORT3_PDISC_PDIS3_Pos (3UL)
15974 #define PORT3_PDISC_PDIS3_Msk (0x8UL)
15975 #define PORT3_PDISC_PDIS4_Pos (4UL)
15976 #define PORT3_PDISC_PDIS4_Msk (0x10UL)
15977 #define PORT3_PDISC_PDIS5_Pos (5UL)
15978 #define PORT3_PDISC_PDIS5_Msk (0x20UL)
15979 #define PORT3_PDISC_PDIS6_Pos (6UL)
15980 #define PORT3_PDISC_PDIS6_Msk (0x40UL)
15981 #define PORT3_PDISC_PDIS7_Pos (7UL)
15982 #define PORT3_PDISC_PDIS7_Msk (0x80UL)
15983 #define PORT3_PDISC_PDIS8_Pos (8UL)
15984 #define PORT3_PDISC_PDIS8_Msk (0x100UL)
15985 #define PORT3_PDISC_PDIS9_Pos (9UL)
15986 #define PORT3_PDISC_PDIS9_Msk (0x200UL)
15987 #define PORT3_PDISC_PDIS10_Pos (10UL)
15988 #define PORT3_PDISC_PDIS10_Msk (0x400UL)
15989 #define PORT3_PDISC_PDIS11_Pos (11UL)
15990 #define PORT3_PDISC_PDIS11_Msk (0x800UL)
15991 #define PORT3_PDISC_PDIS12_Pos (12UL)
15992 #define PORT3_PDISC_PDIS12_Msk (0x1000UL)
15993 #define PORT3_PDISC_PDIS13_Pos (13UL)
15994 #define PORT3_PDISC_PDIS13_Msk (0x2000UL)
15995 #define PORT3_PDISC_PDIS14_Pos (14UL)
15996 #define PORT3_PDISC_PDIS14_Msk (0x4000UL)
15997 #define PORT3_PDISC_PDIS15_Pos (15UL)
15998 #define PORT3_PDISC_PDIS15_Msk (0x8000UL)
16000 /* ---------------------------------- PORT3_PPS --------------------------------- */
16001 #define PORT3_PPS_PPS0_Pos (0UL)
16002 #define PORT3_PPS_PPS0_Msk (0x1UL)
16003 #define PORT3_PPS_PPS1_Pos (1UL)
16004 #define PORT3_PPS_PPS1_Msk (0x2UL)
16005 #define PORT3_PPS_PPS2_Pos (2UL)
16006 #define PORT3_PPS_PPS2_Msk (0x4UL)
16007 #define PORT3_PPS_PPS3_Pos (3UL)
16008 #define PORT3_PPS_PPS3_Msk (0x8UL)
16009 #define PORT3_PPS_PPS4_Pos (4UL)
16010 #define PORT3_PPS_PPS4_Msk (0x10UL)
16011 #define PORT3_PPS_PPS5_Pos (5UL)
16012 #define PORT3_PPS_PPS5_Msk (0x20UL)
16013 #define PORT3_PPS_PPS6_Pos (6UL)
16014 #define PORT3_PPS_PPS6_Msk (0x40UL)
16015 #define PORT3_PPS_PPS7_Pos (7UL)
16016 #define PORT3_PPS_PPS7_Msk (0x80UL)
16017 #define PORT3_PPS_PPS8_Pos (8UL)
16018 #define PORT3_PPS_PPS8_Msk (0x100UL)
16019 #define PORT3_PPS_PPS9_Pos (9UL)
16020 #define PORT3_PPS_PPS9_Msk (0x200UL)
16021 #define PORT3_PPS_PPS10_Pos (10UL)
16022 #define PORT3_PPS_PPS10_Msk (0x400UL)
16023 #define PORT3_PPS_PPS11_Pos (11UL)
16024 #define PORT3_PPS_PPS11_Msk (0x800UL)
16025 #define PORT3_PPS_PPS12_Pos (12UL)
16026 #define PORT3_PPS_PPS12_Msk (0x1000UL)
16027 #define PORT3_PPS_PPS13_Pos (13UL)
16028 #define PORT3_PPS_PPS13_Msk (0x2000UL)
16029 #define PORT3_PPS_PPS14_Pos (14UL)
16030 #define PORT3_PPS_PPS14_Msk (0x4000UL)
16031 #define PORT3_PPS_PPS15_Pos (15UL)
16032 #define PORT3_PPS_PPS15_Msk (0x8000UL)
16034 /* --------------------------------- PORT3_HWSEL -------------------------------- */
16035 #define PORT3_HWSEL_HW0_Pos (0UL)
16036 #define PORT3_HWSEL_HW0_Msk (0x3UL)
16037 #define PORT3_HWSEL_HW1_Pos (2UL)
16038 #define PORT3_HWSEL_HW1_Msk (0xcUL)
16039 #define PORT3_HWSEL_HW2_Pos (4UL)
16040 #define PORT3_HWSEL_HW2_Msk (0x30UL)
16041 #define PORT3_HWSEL_HW3_Pos (6UL)
16042 #define PORT3_HWSEL_HW3_Msk (0xc0UL)
16043 #define PORT3_HWSEL_HW4_Pos (8UL)
16044 #define PORT3_HWSEL_HW4_Msk (0x300UL)
16045 #define PORT3_HWSEL_HW5_Pos (10UL)
16046 #define PORT3_HWSEL_HW5_Msk (0xc00UL)
16047 #define PORT3_HWSEL_HW6_Pos (12UL)
16048 #define PORT3_HWSEL_HW6_Msk (0x3000UL)
16049 #define PORT3_HWSEL_HW7_Pos (14UL)
16050 #define PORT3_HWSEL_HW7_Msk (0xc000UL)
16051 #define PORT3_HWSEL_HW8_Pos (16UL)
16052 #define PORT3_HWSEL_HW8_Msk (0x30000UL)
16053 #define PORT3_HWSEL_HW9_Pos (18UL)
16054 #define PORT3_HWSEL_HW9_Msk (0xc0000UL)
16055 #define PORT3_HWSEL_HW10_Pos (20UL)
16056 #define PORT3_HWSEL_HW10_Msk (0x300000UL)
16057 #define PORT3_HWSEL_HW11_Pos (22UL)
16058 #define PORT3_HWSEL_HW11_Msk (0xc00000UL)
16059 #define PORT3_HWSEL_HW12_Pos (24UL)
16060 #define PORT3_HWSEL_HW12_Msk (0x3000000UL)
16061 #define PORT3_HWSEL_HW13_Pos (26UL)
16062 #define PORT3_HWSEL_HW13_Msk (0xc000000UL)
16063 #define PORT3_HWSEL_HW14_Pos (28UL)
16064 #define PORT3_HWSEL_HW14_Msk (0x30000000UL)
16065 #define PORT3_HWSEL_HW15_Pos (30UL)
16066 #define PORT3_HWSEL_HW15_Msk (0xc0000000UL)
16069 /* ================================================================================ */
16070 /* ================ struct 'PORT4' Position & Mask ================ */
16071 /* ================================================================================ */
16072 
16073 
16074 /* ---------------------------------- PORT4_OUT --------------------------------- */
16075 #define PORT4_OUT_P0_Pos (0UL)
16076 #define PORT4_OUT_P0_Msk (0x1UL)
16077 #define PORT4_OUT_P1_Pos (1UL)
16078 #define PORT4_OUT_P1_Msk (0x2UL)
16079 #define PORT4_OUT_P2_Pos (2UL)
16080 #define PORT4_OUT_P2_Msk (0x4UL)
16081 #define PORT4_OUT_P3_Pos (3UL)
16082 #define PORT4_OUT_P3_Msk (0x8UL)
16083 #define PORT4_OUT_P4_Pos (4UL)
16084 #define PORT4_OUT_P4_Msk (0x10UL)
16085 #define PORT4_OUT_P5_Pos (5UL)
16086 #define PORT4_OUT_P5_Msk (0x20UL)
16087 #define PORT4_OUT_P6_Pos (6UL)
16088 #define PORT4_OUT_P6_Msk (0x40UL)
16089 #define PORT4_OUT_P7_Pos (7UL)
16090 #define PORT4_OUT_P7_Msk (0x80UL)
16091 #define PORT4_OUT_P8_Pos (8UL)
16092 #define PORT4_OUT_P8_Msk (0x100UL)
16093 #define PORT4_OUT_P9_Pos (9UL)
16094 #define PORT4_OUT_P9_Msk (0x200UL)
16095 #define PORT4_OUT_P10_Pos (10UL)
16096 #define PORT4_OUT_P10_Msk (0x400UL)
16097 #define PORT4_OUT_P11_Pos (11UL)
16098 #define PORT4_OUT_P11_Msk (0x800UL)
16099 #define PORT4_OUT_P12_Pos (12UL)
16100 #define PORT4_OUT_P12_Msk (0x1000UL)
16101 #define PORT4_OUT_P13_Pos (13UL)
16102 #define PORT4_OUT_P13_Msk (0x2000UL)
16103 #define PORT4_OUT_P14_Pos (14UL)
16104 #define PORT4_OUT_P14_Msk (0x4000UL)
16105 #define PORT4_OUT_P15_Pos (15UL)
16106 #define PORT4_OUT_P15_Msk (0x8000UL)
16108 /* ---------------------------------- PORT4_OMR --------------------------------- */
16109 #define PORT4_OMR_PS0_Pos (0UL)
16110 #define PORT4_OMR_PS0_Msk (0x1UL)
16111 #define PORT4_OMR_PS1_Pos (1UL)
16112 #define PORT4_OMR_PS1_Msk (0x2UL)
16113 #define PORT4_OMR_PS2_Pos (2UL)
16114 #define PORT4_OMR_PS2_Msk (0x4UL)
16115 #define PORT4_OMR_PS3_Pos (3UL)
16116 #define PORT4_OMR_PS3_Msk (0x8UL)
16117 #define PORT4_OMR_PS4_Pos (4UL)
16118 #define PORT4_OMR_PS4_Msk (0x10UL)
16119 #define PORT4_OMR_PS5_Pos (5UL)
16120 #define PORT4_OMR_PS5_Msk (0x20UL)
16121 #define PORT4_OMR_PS6_Pos (6UL)
16122 #define PORT4_OMR_PS6_Msk (0x40UL)
16123 #define PORT4_OMR_PS7_Pos (7UL)
16124 #define PORT4_OMR_PS7_Msk (0x80UL)
16125 #define PORT4_OMR_PS8_Pos (8UL)
16126 #define PORT4_OMR_PS8_Msk (0x100UL)
16127 #define PORT4_OMR_PS9_Pos (9UL)
16128 #define PORT4_OMR_PS9_Msk (0x200UL)
16129 #define PORT4_OMR_PS10_Pos (10UL)
16130 #define PORT4_OMR_PS10_Msk (0x400UL)
16131 #define PORT4_OMR_PS11_Pos (11UL)
16132 #define PORT4_OMR_PS11_Msk (0x800UL)
16133 #define PORT4_OMR_PS12_Pos (12UL)
16134 #define PORT4_OMR_PS12_Msk (0x1000UL)
16135 #define PORT4_OMR_PS13_Pos (13UL)
16136 #define PORT4_OMR_PS13_Msk (0x2000UL)
16137 #define PORT4_OMR_PS14_Pos (14UL)
16138 #define PORT4_OMR_PS14_Msk (0x4000UL)
16139 #define PORT4_OMR_PS15_Pos (15UL)
16140 #define PORT4_OMR_PS15_Msk (0x8000UL)
16141 #define PORT4_OMR_PR0_Pos (16UL)
16142 #define PORT4_OMR_PR0_Msk (0x10000UL)
16143 #define PORT4_OMR_PR1_Pos (17UL)
16144 #define PORT4_OMR_PR1_Msk (0x20000UL)
16145 #define PORT4_OMR_PR2_Pos (18UL)
16146 #define PORT4_OMR_PR2_Msk (0x40000UL)
16147 #define PORT4_OMR_PR3_Pos (19UL)
16148 #define PORT4_OMR_PR3_Msk (0x80000UL)
16149 #define PORT4_OMR_PR4_Pos (20UL)
16150 #define PORT4_OMR_PR4_Msk (0x100000UL)
16151 #define PORT4_OMR_PR5_Pos (21UL)
16152 #define PORT4_OMR_PR5_Msk (0x200000UL)
16153 #define PORT4_OMR_PR6_Pos (22UL)
16154 #define PORT4_OMR_PR6_Msk (0x400000UL)
16155 #define PORT4_OMR_PR7_Pos (23UL)
16156 #define PORT4_OMR_PR7_Msk (0x800000UL)
16157 #define PORT4_OMR_PR8_Pos (24UL)
16158 #define PORT4_OMR_PR8_Msk (0x1000000UL)
16159 #define PORT4_OMR_PR9_Pos (25UL)
16160 #define PORT4_OMR_PR9_Msk (0x2000000UL)
16161 #define PORT4_OMR_PR10_Pos (26UL)
16162 #define PORT4_OMR_PR10_Msk (0x4000000UL)
16163 #define PORT4_OMR_PR11_Pos (27UL)
16164 #define PORT4_OMR_PR11_Msk (0x8000000UL)
16165 #define PORT4_OMR_PR12_Pos (28UL)
16166 #define PORT4_OMR_PR12_Msk (0x10000000UL)
16167 #define PORT4_OMR_PR13_Pos (29UL)
16168 #define PORT4_OMR_PR13_Msk (0x20000000UL)
16169 #define PORT4_OMR_PR14_Pos (30UL)
16170 #define PORT4_OMR_PR14_Msk (0x40000000UL)
16171 #define PORT4_OMR_PR15_Pos (31UL)
16172 #define PORT4_OMR_PR15_Msk (0x80000000UL)
16174 /* --------------------------------- PORT4_IOCR0 -------------------------------- */
16175 #define PORT4_IOCR0_PC0_Pos (3UL)
16176 #define PORT4_IOCR0_PC0_Msk (0xf8UL)
16177 #define PORT4_IOCR0_PC1_Pos (11UL)
16178 #define PORT4_IOCR0_PC1_Msk (0xf800UL)
16179 #define PORT4_IOCR0_PC2_Pos (19UL)
16180 #define PORT4_IOCR0_PC2_Msk (0xf80000UL)
16181 #define PORT4_IOCR0_PC3_Pos (27UL)
16182 #define PORT4_IOCR0_PC3_Msk (0xf8000000UL)
16184 /* --------------------------------- PORT4_IOCR4 -------------------------------- */
16185 #define PORT4_IOCR4_PC4_Pos (3UL)
16186 #define PORT4_IOCR4_PC4_Msk (0xf8UL)
16187 #define PORT4_IOCR4_PC5_Pos (11UL)
16188 #define PORT4_IOCR4_PC5_Msk (0xf800UL)
16189 #define PORT4_IOCR4_PC6_Pos (19UL)
16190 #define PORT4_IOCR4_PC6_Msk (0xf80000UL)
16191 #define PORT4_IOCR4_PC7_Pos (27UL)
16192 #define PORT4_IOCR4_PC7_Msk (0xf8000000UL)
16194 /* ---------------------------------- PORT4_IN ---------------------------------- */
16195 #define PORT4_IN_P0_Pos (0UL)
16196 #define PORT4_IN_P0_Msk (0x1UL)
16197 #define PORT4_IN_P1_Pos (1UL)
16198 #define PORT4_IN_P1_Msk (0x2UL)
16199 #define PORT4_IN_P2_Pos (2UL)
16200 #define PORT4_IN_P2_Msk (0x4UL)
16201 #define PORT4_IN_P3_Pos (3UL)
16202 #define PORT4_IN_P3_Msk (0x8UL)
16203 #define PORT4_IN_P4_Pos (4UL)
16204 #define PORT4_IN_P4_Msk (0x10UL)
16205 #define PORT4_IN_P5_Pos (5UL)
16206 #define PORT4_IN_P5_Msk (0x20UL)
16207 #define PORT4_IN_P6_Pos (6UL)
16208 #define PORT4_IN_P6_Msk (0x40UL)
16209 #define PORT4_IN_P7_Pos (7UL)
16210 #define PORT4_IN_P7_Msk (0x80UL)
16211 #define PORT4_IN_P8_Pos (8UL)
16212 #define PORT4_IN_P8_Msk (0x100UL)
16213 #define PORT4_IN_P9_Pos (9UL)
16214 #define PORT4_IN_P9_Msk (0x200UL)
16215 #define PORT4_IN_P10_Pos (10UL)
16216 #define PORT4_IN_P10_Msk (0x400UL)
16217 #define PORT4_IN_P11_Pos (11UL)
16218 #define PORT4_IN_P11_Msk (0x800UL)
16219 #define PORT4_IN_P12_Pos (12UL)
16220 #define PORT4_IN_P12_Msk (0x1000UL)
16221 #define PORT4_IN_P13_Pos (13UL)
16222 #define PORT4_IN_P13_Msk (0x2000UL)
16223 #define PORT4_IN_P14_Pos (14UL)
16224 #define PORT4_IN_P14_Msk (0x4000UL)
16225 #define PORT4_IN_P15_Pos (15UL)
16226 #define PORT4_IN_P15_Msk (0x8000UL)
16228 /* --------------------------------- PORT4_PDR0 --------------------------------- */
16229 #define PORT4_PDR0_PD0_Pos (0UL)
16230 #define PORT4_PDR0_PD0_Msk (0x7UL)
16231 #define PORT4_PDR0_PD1_Pos (4UL)
16232 #define PORT4_PDR0_PD1_Msk (0x70UL)
16233 #define PORT4_PDR0_PD2_Pos (8UL)
16234 #define PORT4_PDR0_PD2_Msk (0x700UL)
16235 #define PORT4_PDR0_PD3_Pos (12UL)
16236 #define PORT4_PDR0_PD3_Msk (0x7000UL)
16237 #define PORT4_PDR0_PD4_Pos (16UL)
16238 #define PORT4_PDR0_PD4_Msk (0x70000UL)
16239 #define PORT4_PDR0_PD5_Pos (20UL)
16240 #define PORT4_PDR0_PD5_Msk (0x700000UL)
16241 #define PORT4_PDR0_PD6_Pos (24UL)
16242 #define PORT4_PDR0_PD6_Msk (0x7000000UL)
16243 #define PORT4_PDR0_PD7_Pos (28UL)
16244 #define PORT4_PDR0_PD7_Msk (0x70000000UL)
16246 /* --------------------------------- PORT4_PDISC -------------------------------- */
16247 #define PORT4_PDISC_PDIS0_Pos (0UL)
16248 #define PORT4_PDISC_PDIS0_Msk (0x1UL)
16249 #define PORT4_PDISC_PDIS1_Pos (1UL)
16250 #define PORT4_PDISC_PDIS1_Msk (0x2UL)
16251 #define PORT4_PDISC_PDIS2_Pos (2UL)
16252 #define PORT4_PDISC_PDIS2_Msk (0x4UL)
16253 #define PORT4_PDISC_PDIS3_Pos (3UL)
16254 #define PORT4_PDISC_PDIS3_Msk (0x8UL)
16255 #define PORT4_PDISC_PDIS4_Pos (4UL)
16256 #define PORT4_PDISC_PDIS4_Msk (0x10UL)
16257 #define PORT4_PDISC_PDIS5_Pos (5UL)
16258 #define PORT4_PDISC_PDIS5_Msk (0x20UL)
16259 #define PORT4_PDISC_PDIS6_Pos (6UL)
16260 #define PORT4_PDISC_PDIS6_Msk (0x40UL)
16261 #define PORT4_PDISC_PDIS7_Pos (7UL)
16262 #define PORT4_PDISC_PDIS7_Msk (0x80UL)
16263 #define PORT4_PDISC_PDIS8_Pos (8UL)
16264 #define PORT4_PDISC_PDIS8_Msk (0x100UL)
16265 #define PORT4_PDISC_PDIS9_Pos (9UL)
16266 #define PORT4_PDISC_PDIS9_Msk (0x200UL)
16267 #define PORT4_PDISC_PDIS10_Pos (10UL)
16268 #define PORT4_PDISC_PDIS10_Msk (0x400UL)
16269 #define PORT4_PDISC_PDIS11_Pos (11UL)
16270 #define PORT4_PDISC_PDIS11_Msk (0x800UL)
16271 #define PORT4_PDISC_PDIS12_Pos (12UL)
16272 #define PORT4_PDISC_PDIS12_Msk (0x1000UL)
16273 #define PORT4_PDISC_PDIS13_Pos (13UL)
16274 #define PORT4_PDISC_PDIS13_Msk (0x2000UL)
16275 #define PORT4_PDISC_PDIS14_Pos (14UL)
16276 #define PORT4_PDISC_PDIS14_Msk (0x4000UL)
16277 #define PORT4_PDISC_PDIS15_Pos (15UL)
16278 #define PORT4_PDISC_PDIS15_Msk (0x8000UL)
16280 /* ---------------------------------- PORT4_PPS --------------------------------- */
16281 #define PORT4_PPS_PPS0_Pos (0UL)
16282 #define PORT4_PPS_PPS0_Msk (0x1UL)
16283 #define PORT4_PPS_PPS1_Pos (1UL)
16284 #define PORT4_PPS_PPS1_Msk (0x2UL)
16285 #define PORT4_PPS_PPS2_Pos (2UL)
16286 #define PORT4_PPS_PPS2_Msk (0x4UL)
16287 #define PORT4_PPS_PPS3_Pos (3UL)
16288 #define PORT4_PPS_PPS3_Msk (0x8UL)
16289 #define PORT4_PPS_PPS4_Pos (4UL)
16290 #define PORT4_PPS_PPS4_Msk (0x10UL)
16291 #define PORT4_PPS_PPS5_Pos (5UL)
16292 #define PORT4_PPS_PPS5_Msk (0x20UL)
16293 #define PORT4_PPS_PPS6_Pos (6UL)
16294 #define PORT4_PPS_PPS6_Msk (0x40UL)
16295 #define PORT4_PPS_PPS7_Pos (7UL)
16296 #define PORT4_PPS_PPS7_Msk (0x80UL)
16297 #define PORT4_PPS_PPS8_Pos (8UL)
16298 #define PORT4_PPS_PPS8_Msk (0x100UL)
16299 #define PORT4_PPS_PPS9_Pos (9UL)
16300 #define PORT4_PPS_PPS9_Msk (0x200UL)
16301 #define PORT4_PPS_PPS10_Pos (10UL)
16302 #define PORT4_PPS_PPS10_Msk (0x400UL)
16303 #define PORT4_PPS_PPS11_Pos (11UL)
16304 #define PORT4_PPS_PPS11_Msk (0x800UL)
16305 #define PORT4_PPS_PPS12_Pos (12UL)
16306 #define PORT4_PPS_PPS12_Msk (0x1000UL)
16307 #define PORT4_PPS_PPS13_Pos (13UL)
16308 #define PORT4_PPS_PPS13_Msk (0x2000UL)
16309 #define PORT4_PPS_PPS14_Pos (14UL)
16310 #define PORT4_PPS_PPS14_Msk (0x4000UL)
16311 #define PORT4_PPS_PPS15_Pos (15UL)
16312 #define PORT4_PPS_PPS15_Msk (0x8000UL)
16314 /* --------------------------------- PORT4_HWSEL -------------------------------- */
16315 #define PORT4_HWSEL_HW0_Pos (0UL)
16316 #define PORT4_HWSEL_HW0_Msk (0x3UL)
16317 #define PORT4_HWSEL_HW1_Pos (2UL)
16318 #define PORT4_HWSEL_HW1_Msk (0xcUL)
16319 #define PORT4_HWSEL_HW2_Pos (4UL)
16320 #define PORT4_HWSEL_HW2_Msk (0x30UL)
16321 #define PORT4_HWSEL_HW3_Pos (6UL)
16322 #define PORT4_HWSEL_HW3_Msk (0xc0UL)
16323 #define PORT4_HWSEL_HW4_Pos (8UL)
16324 #define PORT4_HWSEL_HW4_Msk (0x300UL)
16325 #define PORT4_HWSEL_HW5_Pos (10UL)
16326 #define PORT4_HWSEL_HW5_Msk (0xc00UL)
16327 #define PORT4_HWSEL_HW6_Pos (12UL)
16328 #define PORT4_HWSEL_HW6_Msk (0x3000UL)
16329 #define PORT4_HWSEL_HW7_Pos (14UL)
16330 #define PORT4_HWSEL_HW7_Msk (0xc000UL)
16331 #define PORT4_HWSEL_HW8_Pos (16UL)
16332 #define PORT4_HWSEL_HW8_Msk (0x30000UL)
16333 #define PORT4_HWSEL_HW9_Pos (18UL)
16334 #define PORT4_HWSEL_HW9_Msk (0xc0000UL)
16335 #define PORT4_HWSEL_HW10_Pos (20UL)
16336 #define PORT4_HWSEL_HW10_Msk (0x300000UL)
16337 #define PORT4_HWSEL_HW11_Pos (22UL)
16338 #define PORT4_HWSEL_HW11_Msk (0xc00000UL)
16339 #define PORT4_HWSEL_HW12_Pos (24UL)
16340 #define PORT4_HWSEL_HW12_Msk (0x3000000UL)
16341 #define PORT4_HWSEL_HW13_Pos (26UL)
16342 #define PORT4_HWSEL_HW13_Msk (0xc000000UL)
16343 #define PORT4_HWSEL_HW14_Pos (28UL)
16344 #define PORT4_HWSEL_HW14_Msk (0x30000000UL)
16345 #define PORT4_HWSEL_HW15_Pos (30UL)
16346 #define PORT4_HWSEL_HW15_Msk (0xc0000000UL)
16349 /* ================================================================================ */
16350 /* ================ struct 'PORT5' Position & Mask ================ */
16351 /* ================================================================================ */
16352 
16353 
16354 /* ---------------------------------- PORT5_OUT --------------------------------- */
16355 #define PORT5_OUT_P0_Pos (0UL)
16356 #define PORT5_OUT_P0_Msk (0x1UL)
16357 #define PORT5_OUT_P1_Pos (1UL)
16358 #define PORT5_OUT_P1_Msk (0x2UL)
16359 #define PORT5_OUT_P2_Pos (2UL)
16360 #define PORT5_OUT_P2_Msk (0x4UL)
16361 #define PORT5_OUT_P3_Pos (3UL)
16362 #define PORT5_OUT_P3_Msk (0x8UL)
16363 #define PORT5_OUT_P4_Pos (4UL)
16364 #define PORT5_OUT_P4_Msk (0x10UL)
16365 #define PORT5_OUT_P5_Pos (5UL)
16366 #define PORT5_OUT_P5_Msk (0x20UL)
16367 #define PORT5_OUT_P6_Pos (6UL)
16368 #define PORT5_OUT_P6_Msk (0x40UL)
16369 #define PORT5_OUT_P7_Pos (7UL)
16370 #define PORT5_OUT_P7_Msk (0x80UL)
16371 #define PORT5_OUT_P8_Pos (8UL)
16372 #define PORT5_OUT_P8_Msk (0x100UL)
16373 #define PORT5_OUT_P9_Pos (9UL)
16374 #define PORT5_OUT_P9_Msk (0x200UL)
16375 #define PORT5_OUT_P10_Pos (10UL)
16376 #define PORT5_OUT_P10_Msk (0x400UL)
16377 #define PORT5_OUT_P11_Pos (11UL)
16378 #define PORT5_OUT_P11_Msk (0x800UL)
16379 #define PORT5_OUT_P12_Pos (12UL)
16380 #define PORT5_OUT_P12_Msk (0x1000UL)
16381 #define PORT5_OUT_P13_Pos (13UL)
16382 #define PORT5_OUT_P13_Msk (0x2000UL)
16383 #define PORT5_OUT_P14_Pos (14UL)
16384 #define PORT5_OUT_P14_Msk (0x4000UL)
16385 #define PORT5_OUT_P15_Pos (15UL)
16386 #define PORT5_OUT_P15_Msk (0x8000UL)
16388 /* ---------------------------------- PORT5_OMR --------------------------------- */
16389 #define PORT5_OMR_PS0_Pos (0UL)
16390 #define PORT5_OMR_PS0_Msk (0x1UL)
16391 #define PORT5_OMR_PS1_Pos (1UL)
16392 #define PORT5_OMR_PS1_Msk (0x2UL)
16393 #define PORT5_OMR_PS2_Pos (2UL)
16394 #define PORT5_OMR_PS2_Msk (0x4UL)
16395 #define PORT5_OMR_PS3_Pos (3UL)
16396 #define PORT5_OMR_PS3_Msk (0x8UL)
16397 #define PORT5_OMR_PS4_Pos (4UL)
16398 #define PORT5_OMR_PS4_Msk (0x10UL)
16399 #define PORT5_OMR_PS5_Pos (5UL)
16400 #define PORT5_OMR_PS5_Msk (0x20UL)
16401 #define PORT5_OMR_PS6_Pos (6UL)
16402 #define PORT5_OMR_PS6_Msk (0x40UL)
16403 #define PORT5_OMR_PS7_Pos (7UL)
16404 #define PORT5_OMR_PS7_Msk (0x80UL)
16405 #define PORT5_OMR_PS8_Pos (8UL)
16406 #define PORT5_OMR_PS8_Msk (0x100UL)
16407 #define PORT5_OMR_PS9_Pos (9UL)
16408 #define PORT5_OMR_PS9_Msk (0x200UL)
16409 #define PORT5_OMR_PS10_Pos (10UL)
16410 #define PORT5_OMR_PS10_Msk (0x400UL)
16411 #define PORT5_OMR_PS11_Pos (11UL)
16412 #define PORT5_OMR_PS11_Msk (0x800UL)
16413 #define PORT5_OMR_PS12_Pos (12UL)
16414 #define PORT5_OMR_PS12_Msk (0x1000UL)
16415 #define PORT5_OMR_PS13_Pos (13UL)
16416 #define PORT5_OMR_PS13_Msk (0x2000UL)
16417 #define PORT5_OMR_PS14_Pos (14UL)
16418 #define PORT5_OMR_PS14_Msk (0x4000UL)
16419 #define PORT5_OMR_PS15_Pos (15UL)
16420 #define PORT5_OMR_PS15_Msk (0x8000UL)
16421 #define PORT5_OMR_PR0_Pos (16UL)
16422 #define PORT5_OMR_PR0_Msk (0x10000UL)
16423 #define PORT5_OMR_PR1_Pos (17UL)
16424 #define PORT5_OMR_PR1_Msk (0x20000UL)
16425 #define PORT5_OMR_PR2_Pos (18UL)
16426 #define PORT5_OMR_PR2_Msk (0x40000UL)
16427 #define PORT5_OMR_PR3_Pos (19UL)
16428 #define PORT5_OMR_PR3_Msk (0x80000UL)
16429 #define PORT5_OMR_PR4_Pos (20UL)
16430 #define PORT5_OMR_PR4_Msk (0x100000UL)
16431 #define PORT5_OMR_PR5_Pos (21UL)
16432 #define PORT5_OMR_PR5_Msk (0x200000UL)
16433 #define PORT5_OMR_PR6_Pos (22UL)
16434 #define PORT5_OMR_PR6_Msk (0x400000UL)
16435 #define PORT5_OMR_PR7_Pos (23UL)
16436 #define PORT5_OMR_PR7_Msk (0x800000UL)
16437 #define PORT5_OMR_PR8_Pos (24UL)
16438 #define PORT5_OMR_PR8_Msk (0x1000000UL)
16439 #define PORT5_OMR_PR9_Pos (25UL)
16440 #define PORT5_OMR_PR9_Msk (0x2000000UL)
16441 #define PORT5_OMR_PR10_Pos (26UL)
16442 #define PORT5_OMR_PR10_Msk (0x4000000UL)
16443 #define PORT5_OMR_PR11_Pos (27UL)
16444 #define PORT5_OMR_PR11_Msk (0x8000000UL)
16445 #define PORT5_OMR_PR12_Pos (28UL)
16446 #define PORT5_OMR_PR12_Msk (0x10000000UL)
16447 #define PORT5_OMR_PR13_Pos (29UL)
16448 #define PORT5_OMR_PR13_Msk (0x20000000UL)
16449 #define PORT5_OMR_PR14_Pos (30UL)
16450 #define PORT5_OMR_PR14_Msk (0x40000000UL)
16451 #define PORT5_OMR_PR15_Pos (31UL)
16452 #define PORT5_OMR_PR15_Msk (0x80000000UL)
16454 /* --------------------------------- PORT5_IOCR0 -------------------------------- */
16455 #define PORT5_IOCR0_PC0_Pos (3UL)
16456 #define PORT5_IOCR0_PC0_Msk (0xf8UL)
16457 #define PORT5_IOCR0_PC1_Pos (11UL)
16458 #define PORT5_IOCR0_PC1_Msk (0xf800UL)
16459 #define PORT5_IOCR0_PC2_Pos (19UL)
16460 #define PORT5_IOCR0_PC2_Msk (0xf80000UL)
16461 #define PORT5_IOCR0_PC3_Pos (27UL)
16462 #define PORT5_IOCR0_PC3_Msk (0xf8000000UL)
16464 /* --------------------------------- PORT5_IOCR4 -------------------------------- */
16465 #define PORT5_IOCR4_PC4_Pos (3UL)
16466 #define PORT5_IOCR4_PC4_Msk (0xf8UL)
16467 #define PORT5_IOCR4_PC5_Pos (11UL)
16468 #define PORT5_IOCR4_PC5_Msk (0xf800UL)
16469 #define PORT5_IOCR4_PC6_Pos (19UL)
16470 #define PORT5_IOCR4_PC6_Msk (0xf80000UL)
16471 #define PORT5_IOCR4_PC7_Pos (27UL)
16472 #define PORT5_IOCR4_PC7_Msk (0xf8000000UL)
16474 /* --------------------------------- PORT5_IOCR8 -------------------------------- */
16475 #define PORT5_IOCR8_PC8_Pos (3UL)
16476 #define PORT5_IOCR8_PC8_Msk (0xf8UL)
16477 #define PORT5_IOCR8_PC9_Pos (11UL)
16478 #define PORT5_IOCR8_PC9_Msk (0xf800UL)
16479 #define PORT5_IOCR8_PC10_Pos (19UL)
16480 #define PORT5_IOCR8_PC10_Msk (0xf80000UL)
16481 #define PORT5_IOCR8_PC11_Pos (27UL)
16482 #define PORT5_IOCR8_PC11_Msk (0xf8000000UL)
16484 /* ---------------------------------- PORT5_IN ---------------------------------- */
16485 #define PORT5_IN_P0_Pos (0UL)
16486 #define PORT5_IN_P0_Msk (0x1UL)
16487 #define PORT5_IN_P1_Pos (1UL)
16488 #define PORT5_IN_P1_Msk (0x2UL)
16489 #define PORT5_IN_P2_Pos (2UL)
16490 #define PORT5_IN_P2_Msk (0x4UL)
16491 #define PORT5_IN_P3_Pos (3UL)
16492 #define PORT5_IN_P3_Msk (0x8UL)
16493 #define PORT5_IN_P4_Pos (4UL)
16494 #define PORT5_IN_P4_Msk (0x10UL)
16495 #define PORT5_IN_P5_Pos (5UL)
16496 #define PORT5_IN_P5_Msk (0x20UL)
16497 #define PORT5_IN_P6_Pos (6UL)
16498 #define PORT5_IN_P6_Msk (0x40UL)
16499 #define PORT5_IN_P7_Pos (7UL)
16500 #define PORT5_IN_P7_Msk (0x80UL)
16501 #define PORT5_IN_P8_Pos (8UL)
16502 #define PORT5_IN_P8_Msk (0x100UL)
16503 #define PORT5_IN_P9_Pos (9UL)
16504 #define PORT5_IN_P9_Msk (0x200UL)
16505 #define PORT5_IN_P10_Pos (10UL)
16506 #define PORT5_IN_P10_Msk (0x400UL)
16507 #define PORT5_IN_P11_Pos (11UL)
16508 #define PORT5_IN_P11_Msk (0x800UL)
16509 #define PORT5_IN_P12_Pos (12UL)
16510 #define PORT5_IN_P12_Msk (0x1000UL)
16511 #define PORT5_IN_P13_Pos (13UL)
16512 #define PORT5_IN_P13_Msk (0x2000UL)
16513 #define PORT5_IN_P14_Pos (14UL)
16514 #define PORT5_IN_P14_Msk (0x4000UL)
16515 #define PORT5_IN_P15_Pos (15UL)
16516 #define PORT5_IN_P15_Msk (0x8000UL)
16518 /* --------------------------------- PORT5_PDR0 --------------------------------- */
16519 #define PORT5_PDR0_PD0_Pos (0UL)
16520 #define PORT5_PDR0_PD0_Msk (0x7UL)
16521 #define PORT5_PDR0_PD1_Pos (4UL)
16522 #define PORT5_PDR0_PD1_Msk (0x70UL)
16523 #define PORT5_PDR0_PD2_Pos (8UL)
16524 #define PORT5_PDR0_PD2_Msk (0x700UL)
16525 #define PORT5_PDR0_PD3_Pos (12UL)
16526 #define PORT5_PDR0_PD3_Msk (0x7000UL)
16527 #define PORT5_PDR0_PD4_Pos (16UL)
16528 #define PORT5_PDR0_PD4_Msk (0x70000UL)
16529 #define PORT5_PDR0_PD5_Pos (20UL)
16530 #define PORT5_PDR0_PD5_Msk (0x700000UL)
16531 #define PORT5_PDR0_PD6_Pos (24UL)
16532 #define PORT5_PDR0_PD6_Msk (0x7000000UL)
16533 #define PORT5_PDR0_PD7_Pos (28UL)
16534 #define PORT5_PDR0_PD7_Msk (0x70000000UL)
16536 /* --------------------------------- PORT5_PDR1 --------------------------------- */
16537 #define PORT5_PDR1_PD8_Pos (0UL)
16538 #define PORT5_PDR1_PD8_Msk (0x7UL)
16539 #define PORT5_PDR1_PD9_Pos (4UL)
16540 #define PORT5_PDR1_PD9_Msk (0x70UL)
16541 #define PORT5_PDR1_PD10_Pos (8UL)
16542 #define PORT5_PDR1_PD10_Msk (0x700UL)
16543 #define PORT5_PDR1_PD11_Pos (12UL)
16544 #define PORT5_PDR1_PD11_Msk (0x7000UL)
16545 #define PORT5_PDR1_PD12_Pos (16UL)
16546 #define PORT5_PDR1_PD12_Msk (0x70000UL)
16547 #define PORT5_PDR1_PD13_Pos (20UL)
16548 #define PORT5_PDR1_PD13_Msk (0x700000UL)
16549 #define PORT5_PDR1_PD14_Pos (24UL)
16550 #define PORT5_PDR1_PD14_Msk (0x7000000UL)
16551 #define PORT5_PDR1_PD15_Pos (28UL)
16552 #define PORT5_PDR1_PD15_Msk (0x70000000UL)
16554 /* --------------------------------- PORT5_PDISC -------------------------------- */
16555 #define PORT5_PDISC_PDIS0_Pos (0UL)
16556 #define PORT5_PDISC_PDIS0_Msk (0x1UL)
16557 #define PORT5_PDISC_PDIS1_Pos (1UL)
16558 #define PORT5_PDISC_PDIS1_Msk (0x2UL)
16559 #define PORT5_PDISC_PDIS2_Pos (2UL)
16560 #define PORT5_PDISC_PDIS2_Msk (0x4UL)
16561 #define PORT5_PDISC_PDIS3_Pos (3UL)
16562 #define PORT5_PDISC_PDIS3_Msk (0x8UL)
16563 #define PORT5_PDISC_PDIS4_Pos (4UL)
16564 #define PORT5_PDISC_PDIS4_Msk (0x10UL)
16565 #define PORT5_PDISC_PDIS5_Pos (5UL)
16566 #define PORT5_PDISC_PDIS5_Msk (0x20UL)
16567 #define PORT5_PDISC_PDIS6_Pos (6UL)
16568 #define PORT5_PDISC_PDIS6_Msk (0x40UL)
16569 #define PORT5_PDISC_PDIS7_Pos (7UL)
16570 #define PORT5_PDISC_PDIS7_Msk (0x80UL)
16571 #define PORT5_PDISC_PDIS8_Pos (8UL)
16572 #define PORT5_PDISC_PDIS8_Msk (0x100UL)
16573 #define PORT5_PDISC_PDIS9_Pos (9UL)
16574 #define PORT5_PDISC_PDIS9_Msk (0x200UL)
16575 #define PORT5_PDISC_PDIS10_Pos (10UL)
16576 #define PORT5_PDISC_PDIS10_Msk (0x400UL)
16577 #define PORT5_PDISC_PDIS11_Pos (11UL)
16578 #define PORT5_PDISC_PDIS11_Msk (0x800UL)
16579 #define PORT5_PDISC_PDIS12_Pos (12UL)
16580 #define PORT5_PDISC_PDIS12_Msk (0x1000UL)
16581 #define PORT5_PDISC_PDIS13_Pos (13UL)
16582 #define PORT5_PDISC_PDIS13_Msk (0x2000UL)
16583 #define PORT5_PDISC_PDIS14_Pos (14UL)
16584 #define PORT5_PDISC_PDIS14_Msk (0x4000UL)
16585 #define PORT5_PDISC_PDIS15_Pos (15UL)
16586 #define PORT5_PDISC_PDIS15_Msk (0x8000UL)
16588 /* ---------------------------------- PORT5_PPS --------------------------------- */
16589 #define PORT5_PPS_PPS0_Pos (0UL)
16590 #define PORT5_PPS_PPS0_Msk (0x1UL)
16591 #define PORT5_PPS_PPS1_Pos (1UL)
16592 #define PORT5_PPS_PPS1_Msk (0x2UL)
16593 #define PORT5_PPS_PPS2_Pos (2UL)
16594 #define PORT5_PPS_PPS2_Msk (0x4UL)
16595 #define PORT5_PPS_PPS3_Pos (3UL)
16596 #define PORT5_PPS_PPS3_Msk (0x8UL)
16597 #define PORT5_PPS_PPS4_Pos (4UL)
16598 #define PORT5_PPS_PPS4_Msk (0x10UL)
16599 #define PORT5_PPS_PPS5_Pos (5UL)
16600 #define PORT5_PPS_PPS5_Msk (0x20UL)
16601 #define PORT5_PPS_PPS6_Pos (6UL)
16602 #define PORT5_PPS_PPS6_Msk (0x40UL)
16603 #define PORT5_PPS_PPS7_Pos (7UL)
16604 #define PORT5_PPS_PPS7_Msk (0x80UL)
16605 #define PORT5_PPS_PPS8_Pos (8UL)
16606 #define PORT5_PPS_PPS8_Msk (0x100UL)
16607 #define PORT5_PPS_PPS9_Pos (9UL)
16608 #define PORT5_PPS_PPS9_Msk (0x200UL)
16609 #define PORT5_PPS_PPS10_Pos (10UL)
16610 #define PORT5_PPS_PPS10_Msk (0x400UL)
16611 #define PORT5_PPS_PPS11_Pos (11UL)
16612 #define PORT5_PPS_PPS11_Msk (0x800UL)
16613 #define PORT5_PPS_PPS12_Pos (12UL)
16614 #define PORT5_PPS_PPS12_Msk (0x1000UL)
16615 #define PORT5_PPS_PPS13_Pos (13UL)
16616 #define PORT5_PPS_PPS13_Msk (0x2000UL)
16617 #define PORT5_PPS_PPS14_Pos (14UL)
16618 #define PORT5_PPS_PPS14_Msk (0x4000UL)
16619 #define PORT5_PPS_PPS15_Pos (15UL)
16620 #define PORT5_PPS_PPS15_Msk (0x8000UL)
16622 /* --------------------------------- PORT5_HWSEL -------------------------------- */
16623 #define PORT5_HWSEL_HW0_Pos (0UL)
16624 #define PORT5_HWSEL_HW0_Msk (0x3UL)
16625 #define PORT5_HWSEL_HW1_Pos (2UL)
16626 #define PORT5_HWSEL_HW1_Msk (0xcUL)
16627 #define PORT5_HWSEL_HW2_Pos (4UL)
16628 #define PORT5_HWSEL_HW2_Msk (0x30UL)
16629 #define PORT5_HWSEL_HW3_Pos (6UL)
16630 #define PORT5_HWSEL_HW3_Msk (0xc0UL)
16631 #define PORT5_HWSEL_HW4_Pos (8UL)
16632 #define PORT5_HWSEL_HW4_Msk (0x300UL)
16633 #define PORT5_HWSEL_HW5_Pos (10UL)
16634 #define PORT5_HWSEL_HW5_Msk (0xc00UL)
16635 #define PORT5_HWSEL_HW6_Pos (12UL)
16636 #define PORT5_HWSEL_HW6_Msk (0x3000UL)
16637 #define PORT5_HWSEL_HW7_Pos (14UL)
16638 #define PORT5_HWSEL_HW7_Msk (0xc000UL)
16639 #define PORT5_HWSEL_HW8_Pos (16UL)
16640 #define PORT5_HWSEL_HW8_Msk (0x30000UL)
16641 #define PORT5_HWSEL_HW9_Pos (18UL)
16642 #define PORT5_HWSEL_HW9_Msk (0xc0000UL)
16643 #define PORT5_HWSEL_HW10_Pos (20UL)
16644 #define PORT5_HWSEL_HW10_Msk (0x300000UL)
16645 #define PORT5_HWSEL_HW11_Pos (22UL)
16646 #define PORT5_HWSEL_HW11_Msk (0xc00000UL)
16647 #define PORT5_HWSEL_HW12_Pos (24UL)
16648 #define PORT5_HWSEL_HW12_Msk (0x3000000UL)
16649 #define PORT5_HWSEL_HW13_Pos (26UL)
16650 #define PORT5_HWSEL_HW13_Msk (0xc000000UL)
16651 #define PORT5_HWSEL_HW14_Pos (28UL)
16652 #define PORT5_HWSEL_HW14_Msk (0x30000000UL)
16653 #define PORT5_HWSEL_HW15_Pos (30UL)
16654 #define PORT5_HWSEL_HW15_Msk (0xc0000000UL)
16657 /* ================================================================================ */
16658 /* ================ struct 'PORT6' Position & Mask ================ */
16659 /* ================================================================================ */
16660 
16661 
16662 /* ---------------------------------- PORT6_OUT --------------------------------- */
16663 #define PORT6_OUT_P0_Pos (0UL)
16664 #define PORT6_OUT_P0_Msk (0x1UL)
16665 #define PORT6_OUT_P1_Pos (1UL)
16666 #define PORT6_OUT_P1_Msk (0x2UL)
16667 #define PORT6_OUT_P2_Pos (2UL)
16668 #define PORT6_OUT_P2_Msk (0x4UL)
16669 #define PORT6_OUT_P3_Pos (3UL)
16670 #define PORT6_OUT_P3_Msk (0x8UL)
16671 #define PORT6_OUT_P4_Pos (4UL)
16672 #define PORT6_OUT_P4_Msk (0x10UL)
16673 #define PORT6_OUT_P5_Pos (5UL)
16674 #define PORT6_OUT_P5_Msk (0x20UL)
16675 #define PORT6_OUT_P6_Pos (6UL)
16676 #define PORT6_OUT_P6_Msk (0x40UL)
16677 #define PORT6_OUT_P7_Pos (7UL)
16678 #define PORT6_OUT_P7_Msk (0x80UL)
16679 #define PORT6_OUT_P8_Pos (8UL)
16680 #define PORT6_OUT_P8_Msk (0x100UL)
16681 #define PORT6_OUT_P9_Pos (9UL)
16682 #define PORT6_OUT_P9_Msk (0x200UL)
16683 #define PORT6_OUT_P10_Pos (10UL)
16684 #define PORT6_OUT_P10_Msk (0x400UL)
16685 #define PORT6_OUT_P11_Pos (11UL)
16686 #define PORT6_OUT_P11_Msk (0x800UL)
16687 #define PORT6_OUT_P12_Pos (12UL)
16688 #define PORT6_OUT_P12_Msk (0x1000UL)
16689 #define PORT6_OUT_P13_Pos (13UL)
16690 #define PORT6_OUT_P13_Msk (0x2000UL)
16691 #define PORT6_OUT_P14_Pos (14UL)
16692 #define PORT6_OUT_P14_Msk (0x4000UL)
16693 #define PORT6_OUT_P15_Pos (15UL)
16694 #define PORT6_OUT_P15_Msk (0x8000UL)
16696 /* ---------------------------------- PORT6_OMR --------------------------------- */
16697 #define PORT6_OMR_PS0_Pos (0UL)
16698 #define PORT6_OMR_PS0_Msk (0x1UL)
16699 #define PORT6_OMR_PS1_Pos (1UL)
16700 #define PORT6_OMR_PS1_Msk (0x2UL)
16701 #define PORT6_OMR_PS2_Pos (2UL)
16702 #define PORT6_OMR_PS2_Msk (0x4UL)
16703 #define PORT6_OMR_PS3_Pos (3UL)
16704 #define PORT6_OMR_PS3_Msk (0x8UL)
16705 #define PORT6_OMR_PS4_Pos (4UL)
16706 #define PORT6_OMR_PS4_Msk (0x10UL)
16707 #define PORT6_OMR_PS5_Pos (5UL)
16708 #define PORT6_OMR_PS5_Msk (0x20UL)
16709 #define PORT6_OMR_PS6_Pos (6UL)
16710 #define PORT6_OMR_PS6_Msk (0x40UL)
16711 #define PORT6_OMR_PS7_Pos (7UL)
16712 #define PORT6_OMR_PS7_Msk (0x80UL)
16713 #define PORT6_OMR_PS8_Pos (8UL)
16714 #define PORT6_OMR_PS8_Msk (0x100UL)
16715 #define PORT6_OMR_PS9_Pos (9UL)
16716 #define PORT6_OMR_PS9_Msk (0x200UL)
16717 #define PORT6_OMR_PS10_Pos (10UL)
16718 #define PORT6_OMR_PS10_Msk (0x400UL)
16719 #define PORT6_OMR_PS11_Pos (11UL)
16720 #define PORT6_OMR_PS11_Msk (0x800UL)
16721 #define PORT6_OMR_PS12_Pos (12UL)
16722 #define PORT6_OMR_PS12_Msk (0x1000UL)
16723 #define PORT6_OMR_PS13_Pos (13UL)
16724 #define PORT6_OMR_PS13_Msk (0x2000UL)
16725 #define PORT6_OMR_PS14_Pos (14UL)
16726 #define PORT6_OMR_PS14_Msk (0x4000UL)
16727 #define PORT6_OMR_PS15_Pos (15UL)
16728 #define PORT6_OMR_PS15_Msk (0x8000UL)
16729 #define PORT6_OMR_PR0_Pos (16UL)
16730 #define PORT6_OMR_PR0_Msk (0x10000UL)
16731 #define PORT6_OMR_PR1_Pos (17UL)
16732 #define PORT6_OMR_PR1_Msk (0x20000UL)
16733 #define PORT6_OMR_PR2_Pos (18UL)
16734 #define PORT6_OMR_PR2_Msk (0x40000UL)
16735 #define PORT6_OMR_PR3_Pos (19UL)
16736 #define PORT6_OMR_PR3_Msk (0x80000UL)
16737 #define PORT6_OMR_PR4_Pos (20UL)
16738 #define PORT6_OMR_PR4_Msk (0x100000UL)
16739 #define PORT6_OMR_PR5_Pos (21UL)
16740 #define PORT6_OMR_PR5_Msk (0x200000UL)
16741 #define PORT6_OMR_PR6_Pos (22UL)
16742 #define PORT6_OMR_PR6_Msk (0x400000UL)
16743 #define PORT6_OMR_PR7_Pos (23UL)
16744 #define PORT6_OMR_PR7_Msk (0x800000UL)
16745 #define PORT6_OMR_PR8_Pos (24UL)
16746 #define PORT6_OMR_PR8_Msk (0x1000000UL)
16747 #define PORT6_OMR_PR9_Pos (25UL)
16748 #define PORT6_OMR_PR9_Msk (0x2000000UL)
16749 #define PORT6_OMR_PR10_Pos (26UL)
16750 #define PORT6_OMR_PR10_Msk (0x4000000UL)
16751 #define PORT6_OMR_PR11_Pos (27UL)
16752 #define PORT6_OMR_PR11_Msk (0x8000000UL)
16753 #define PORT6_OMR_PR12_Pos (28UL)
16754 #define PORT6_OMR_PR12_Msk (0x10000000UL)
16755 #define PORT6_OMR_PR13_Pos (29UL)
16756 #define PORT6_OMR_PR13_Msk (0x20000000UL)
16757 #define PORT6_OMR_PR14_Pos (30UL)
16758 #define PORT6_OMR_PR14_Msk (0x40000000UL)
16759 #define PORT6_OMR_PR15_Pos (31UL)
16760 #define PORT6_OMR_PR15_Msk (0x80000000UL)
16762 /* --------------------------------- PORT6_IOCR0 -------------------------------- */
16763 #define PORT6_IOCR0_PC0_Pos (3UL)
16764 #define PORT6_IOCR0_PC0_Msk (0xf8UL)
16765 #define PORT6_IOCR0_PC1_Pos (11UL)
16766 #define PORT6_IOCR0_PC1_Msk (0xf800UL)
16767 #define PORT6_IOCR0_PC2_Pos (19UL)
16768 #define PORT6_IOCR0_PC2_Msk (0xf80000UL)
16769 #define PORT6_IOCR0_PC3_Pos (27UL)
16770 #define PORT6_IOCR0_PC3_Msk (0xf8000000UL)
16772 /* --------------------------------- PORT6_IOCR4 -------------------------------- */
16773 #define PORT6_IOCR4_PC4_Pos (3UL)
16774 #define PORT6_IOCR4_PC4_Msk (0xf8UL)
16775 #define PORT6_IOCR4_PC5_Pos (11UL)
16776 #define PORT6_IOCR4_PC5_Msk (0xf800UL)
16777 #define PORT6_IOCR4_PC6_Pos (19UL)
16778 #define PORT6_IOCR4_PC6_Msk (0xf80000UL)
16779 #define PORT6_IOCR4_PC7_Pos (27UL)
16780 #define PORT6_IOCR4_PC7_Msk (0xf8000000UL)
16782 /* ---------------------------------- PORT6_IN ---------------------------------- */
16783 #define PORT6_IN_P0_Pos (0UL)
16784 #define PORT6_IN_P0_Msk (0x1UL)
16785 #define PORT6_IN_P1_Pos (1UL)
16786 #define PORT6_IN_P1_Msk (0x2UL)
16787 #define PORT6_IN_P2_Pos (2UL)
16788 #define PORT6_IN_P2_Msk (0x4UL)
16789 #define PORT6_IN_P3_Pos (3UL)
16790 #define PORT6_IN_P3_Msk (0x8UL)
16791 #define PORT6_IN_P4_Pos (4UL)
16792 #define PORT6_IN_P4_Msk (0x10UL)
16793 #define PORT6_IN_P5_Pos (5UL)
16794 #define PORT6_IN_P5_Msk (0x20UL)
16795 #define PORT6_IN_P6_Pos (6UL)
16796 #define PORT6_IN_P6_Msk (0x40UL)
16797 #define PORT6_IN_P7_Pos (7UL)
16798 #define PORT6_IN_P7_Msk (0x80UL)
16799 #define PORT6_IN_P8_Pos (8UL)
16800 #define PORT6_IN_P8_Msk (0x100UL)
16801 #define PORT6_IN_P9_Pos (9UL)
16802 #define PORT6_IN_P9_Msk (0x200UL)
16803 #define PORT6_IN_P10_Pos (10UL)
16804 #define PORT6_IN_P10_Msk (0x400UL)
16805 #define PORT6_IN_P11_Pos (11UL)
16806 #define PORT6_IN_P11_Msk (0x800UL)
16807 #define PORT6_IN_P12_Pos (12UL)
16808 #define PORT6_IN_P12_Msk (0x1000UL)
16809 #define PORT6_IN_P13_Pos (13UL)
16810 #define PORT6_IN_P13_Msk (0x2000UL)
16811 #define PORT6_IN_P14_Pos (14UL)
16812 #define PORT6_IN_P14_Msk (0x4000UL)
16813 #define PORT6_IN_P15_Pos (15UL)
16814 #define PORT6_IN_P15_Msk (0x8000UL)
16816 /* --------------------------------- PORT6_PDR0 --------------------------------- */
16817 #define PORT6_PDR0_PD0_Pos (0UL)
16818 #define PORT6_PDR0_PD0_Msk (0x7UL)
16819 #define PORT6_PDR0_PD1_Pos (4UL)
16820 #define PORT6_PDR0_PD1_Msk (0x70UL)
16821 #define PORT6_PDR0_PD2_Pos (8UL)
16822 #define PORT6_PDR0_PD2_Msk (0x700UL)
16823 #define PORT6_PDR0_PD3_Pos (12UL)
16824 #define PORT6_PDR0_PD3_Msk (0x7000UL)
16825 #define PORT6_PDR0_PD4_Pos (16UL)
16826 #define PORT6_PDR0_PD4_Msk (0x70000UL)
16827 #define PORT6_PDR0_PD5_Pos (20UL)
16828 #define PORT6_PDR0_PD5_Msk (0x700000UL)
16829 #define PORT6_PDR0_PD6_Pos (24UL)
16830 #define PORT6_PDR0_PD6_Msk (0x7000000UL)
16831 #define PORT6_PDR0_PD7_Pos (28UL)
16832 #define PORT6_PDR0_PD7_Msk (0x70000000UL)
16834 /* --------------------------------- PORT6_PDISC -------------------------------- */
16835 #define PORT6_PDISC_PDIS0_Pos (0UL)
16836 #define PORT6_PDISC_PDIS0_Msk (0x1UL)
16837 #define PORT6_PDISC_PDIS1_Pos (1UL)
16838 #define PORT6_PDISC_PDIS1_Msk (0x2UL)
16839 #define PORT6_PDISC_PDIS2_Pos (2UL)
16840 #define PORT6_PDISC_PDIS2_Msk (0x4UL)
16841 #define PORT6_PDISC_PDIS3_Pos (3UL)
16842 #define PORT6_PDISC_PDIS3_Msk (0x8UL)
16843 #define PORT6_PDISC_PDIS4_Pos (4UL)
16844 #define PORT6_PDISC_PDIS4_Msk (0x10UL)
16845 #define PORT6_PDISC_PDIS5_Pos (5UL)
16846 #define PORT6_PDISC_PDIS5_Msk (0x20UL)
16847 #define PORT6_PDISC_PDIS6_Pos (6UL)
16848 #define PORT6_PDISC_PDIS6_Msk (0x40UL)
16849 #define PORT6_PDISC_PDIS7_Pos (7UL)
16850 #define PORT6_PDISC_PDIS7_Msk (0x80UL)
16851 #define PORT6_PDISC_PDIS8_Pos (8UL)
16852 #define PORT6_PDISC_PDIS8_Msk (0x100UL)
16853 #define PORT6_PDISC_PDIS9_Pos (9UL)
16854 #define PORT6_PDISC_PDIS9_Msk (0x200UL)
16855 #define PORT6_PDISC_PDIS10_Pos (10UL)
16856 #define PORT6_PDISC_PDIS10_Msk (0x400UL)
16857 #define PORT6_PDISC_PDIS11_Pos (11UL)
16858 #define PORT6_PDISC_PDIS11_Msk (0x800UL)
16859 #define PORT6_PDISC_PDIS12_Pos (12UL)
16860 #define PORT6_PDISC_PDIS12_Msk (0x1000UL)
16861 #define PORT6_PDISC_PDIS13_Pos (13UL)
16862 #define PORT6_PDISC_PDIS13_Msk (0x2000UL)
16863 #define PORT6_PDISC_PDIS14_Pos (14UL)
16864 #define PORT6_PDISC_PDIS14_Msk (0x4000UL)
16865 #define PORT6_PDISC_PDIS15_Pos (15UL)
16866 #define PORT6_PDISC_PDIS15_Msk (0x8000UL)
16868 /* ---------------------------------- PORT6_PPS --------------------------------- */
16869 #define PORT6_PPS_PPS0_Pos (0UL)
16870 #define PORT6_PPS_PPS0_Msk (0x1UL)
16871 #define PORT6_PPS_PPS1_Pos (1UL)
16872 #define PORT6_PPS_PPS1_Msk (0x2UL)
16873 #define PORT6_PPS_PPS2_Pos (2UL)
16874 #define PORT6_PPS_PPS2_Msk (0x4UL)
16875 #define PORT6_PPS_PPS3_Pos (3UL)
16876 #define PORT6_PPS_PPS3_Msk (0x8UL)
16877 #define PORT6_PPS_PPS4_Pos (4UL)
16878 #define PORT6_PPS_PPS4_Msk (0x10UL)
16879 #define PORT6_PPS_PPS5_Pos (5UL)
16880 #define PORT6_PPS_PPS5_Msk (0x20UL)
16881 #define PORT6_PPS_PPS6_Pos (6UL)
16882 #define PORT6_PPS_PPS6_Msk (0x40UL)
16883 #define PORT6_PPS_PPS7_Pos (7UL)
16884 #define PORT6_PPS_PPS7_Msk (0x80UL)
16885 #define PORT6_PPS_PPS8_Pos (8UL)
16886 #define PORT6_PPS_PPS8_Msk (0x100UL)
16887 #define PORT6_PPS_PPS9_Pos (9UL)
16888 #define PORT6_PPS_PPS9_Msk (0x200UL)
16889 #define PORT6_PPS_PPS10_Pos (10UL)
16890 #define PORT6_PPS_PPS10_Msk (0x400UL)
16891 #define PORT6_PPS_PPS11_Pos (11UL)
16892 #define PORT6_PPS_PPS11_Msk (0x800UL)
16893 #define PORT6_PPS_PPS12_Pos (12UL)
16894 #define PORT6_PPS_PPS12_Msk (0x1000UL)
16895 #define PORT6_PPS_PPS13_Pos (13UL)
16896 #define PORT6_PPS_PPS13_Msk (0x2000UL)
16897 #define PORT6_PPS_PPS14_Pos (14UL)
16898 #define PORT6_PPS_PPS14_Msk (0x4000UL)
16899 #define PORT6_PPS_PPS15_Pos (15UL)
16900 #define PORT6_PPS_PPS15_Msk (0x8000UL)
16902 /* --------------------------------- PORT6_HWSEL -------------------------------- */
16903 #define PORT6_HWSEL_HW0_Pos (0UL)
16904 #define PORT6_HWSEL_HW0_Msk (0x3UL)
16905 #define PORT6_HWSEL_HW1_Pos (2UL)
16906 #define PORT6_HWSEL_HW1_Msk (0xcUL)
16907 #define PORT6_HWSEL_HW2_Pos (4UL)
16908 #define PORT6_HWSEL_HW2_Msk (0x30UL)
16909 #define PORT6_HWSEL_HW3_Pos (6UL)
16910 #define PORT6_HWSEL_HW3_Msk (0xc0UL)
16911 #define PORT6_HWSEL_HW4_Pos (8UL)
16912 #define PORT6_HWSEL_HW4_Msk (0x300UL)
16913 #define PORT6_HWSEL_HW5_Pos (10UL)
16914 #define PORT6_HWSEL_HW5_Msk (0xc00UL)
16915 #define PORT6_HWSEL_HW6_Pos (12UL)
16916 #define PORT6_HWSEL_HW6_Msk (0x3000UL)
16917 #define PORT6_HWSEL_HW7_Pos (14UL)
16918 #define PORT6_HWSEL_HW7_Msk (0xc000UL)
16919 #define PORT6_HWSEL_HW8_Pos (16UL)
16920 #define PORT6_HWSEL_HW8_Msk (0x30000UL)
16921 #define PORT6_HWSEL_HW9_Pos (18UL)
16922 #define PORT6_HWSEL_HW9_Msk (0xc0000UL)
16923 #define PORT6_HWSEL_HW10_Pos (20UL)
16924 #define PORT6_HWSEL_HW10_Msk (0x300000UL)
16925 #define PORT6_HWSEL_HW11_Pos (22UL)
16926 #define PORT6_HWSEL_HW11_Msk (0xc00000UL)
16927 #define PORT6_HWSEL_HW12_Pos (24UL)
16928 #define PORT6_HWSEL_HW12_Msk (0x3000000UL)
16929 #define PORT6_HWSEL_HW13_Pos (26UL)
16930 #define PORT6_HWSEL_HW13_Msk (0xc000000UL)
16931 #define PORT6_HWSEL_HW14_Pos (28UL)
16932 #define PORT6_HWSEL_HW14_Msk (0x30000000UL)
16933 #define PORT6_HWSEL_HW15_Pos (30UL)
16934 #define PORT6_HWSEL_HW15_Msk (0xc0000000UL)
16937 /* ================================================================================ */
16938 /* ================ struct 'PORT7' Position & Mask ================ */
16939 /* ================================================================================ */
16940 
16941 
16942 /* ---------------------------------- PORT7_OUT --------------------------------- */
16943 #define PORT7_OUT_P0_Pos (0UL)
16944 #define PORT7_OUT_P0_Msk (0x1UL)
16945 #define PORT7_OUT_P1_Pos (1UL)
16946 #define PORT7_OUT_P1_Msk (0x2UL)
16947 #define PORT7_OUT_P2_Pos (2UL)
16948 #define PORT7_OUT_P2_Msk (0x4UL)
16949 #define PORT7_OUT_P3_Pos (3UL)
16950 #define PORT7_OUT_P3_Msk (0x8UL)
16951 #define PORT7_OUT_P4_Pos (4UL)
16952 #define PORT7_OUT_P4_Msk (0x10UL)
16953 #define PORT7_OUT_P5_Pos (5UL)
16954 #define PORT7_OUT_P5_Msk (0x20UL)
16955 #define PORT7_OUT_P6_Pos (6UL)
16956 #define PORT7_OUT_P6_Msk (0x40UL)
16957 #define PORT7_OUT_P7_Pos (7UL)
16958 #define PORT7_OUT_P7_Msk (0x80UL)
16959 #define PORT7_OUT_P8_Pos (8UL)
16960 #define PORT7_OUT_P8_Msk (0x100UL)
16961 #define PORT7_OUT_P9_Pos (9UL)
16962 #define PORT7_OUT_P9_Msk (0x200UL)
16963 #define PORT7_OUT_P10_Pos (10UL)
16964 #define PORT7_OUT_P10_Msk (0x400UL)
16965 #define PORT7_OUT_P11_Pos (11UL)
16966 #define PORT7_OUT_P11_Msk (0x800UL)
16967 #define PORT7_OUT_P12_Pos (12UL)
16968 #define PORT7_OUT_P12_Msk (0x1000UL)
16969 #define PORT7_OUT_P13_Pos (13UL)
16970 #define PORT7_OUT_P13_Msk (0x2000UL)
16971 #define PORT7_OUT_P14_Pos (14UL)
16972 #define PORT7_OUT_P14_Msk (0x4000UL)
16973 #define PORT7_OUT_P15_Pos (15UL)
16974 #define PORT7_OUT_P15_Msk (0x8000UL)
16976 /* ---------------------------------- PORT7_OMR --------------------------------- */
16977 #define PORT7_OMR_PS0_Pos (0UL)
16978 #define PORT7_OMR_PS0_Msk (0x1UL)
16979 #define PORT7_OMR_PS1_Pos (1UL)
16980 #define PORT7_OMR_PS1_Msk (0x2UL)
16981 #define PORT7_OMR_PS2_Pos (2UL)
16982 #define PORT7_OMR_PS2_Msk (0x4UL)
16983 #define PORT7_OMR_PS3_Pos (3UL)
16984 #define PORT7_OMR_PS3_Msk (0x8UL)
16985 #define PORT7_OMR_PS4_Pos (4UL)
16986 #define PORT7_OMR_PS4_Msk (0x10UL)
16987 #define PORT7_OMR_PS5_Pos (5UL)
16988 #define PORT7_OMR_PS5_Msk (0x20UL)
16989 #define PORT7_OMR_PS6_Pos (6UL)
16990 #define PORT7_OMR_PS6_Msk (0x40UL)
16991 #define PORT7_OMR_PS7_Pos (7UL)
16992 #define PORT7_OMR_PS7_Msk (0x80UL)
16993 #define PORT7_OMR_PS8_Pos (8UL)
16994 #define PORT7_OMR_PS8_Msk (0x100UL)
16995 #define PORT7_OMR_PS9_Pos (9UL)
16996 #define PORT7_OMR_PS9_Msk (0x200UL)
16997 #define PORT7_OMR_PS10_Pos (10UL)
16998 #define PORT7_OMR_PS10_Msk (0x400UL)
16999 #define PORT7_OMR_PS11_Pos (11UL)
17000 #define PORT7_OMR_PS11_Msk (0x800UL)
17001 #define PORT7_OMR_PS12_Pos (12UL)
17002 #define PORT7_OMR_PS12_Msk (0x1000UL)
17003 #define PORT7_OMR_PS13_Pos (13UL)
17004 #define PORT7_OMR_PS13_Msk (0x2000UL)
17005 #define PORT7_OMR_PS14_Pos (14UL)
17006 #define PORT7_OMR_PS14_Msk (0x4000UL)
17007 #define PORT7_OMR_PS15_Pos (15UL)
17008 #define PORT7_OMR_PS15_Msk (0x8000UL)
17009 #define PORT7_OMR_PR0_Pos (16UL)
17010 #define PORT7_OMR_PR0_Msk (0x10000UL)
17011 #define PORT7_OMR_PR1_Pos (17UL)
17012 #define PORT7_OMR_PR1_Msk (0x20000UL)
17013 #define PORT7_OMR_PR2_Pos (18UL)
17014 #define PORT7_OMR_PR2_Msk (0x40000UL)
17015 #define PORT7_OMR_PR3_Pos (19UL)
17016 #define PORT7_OMR_PR3_Msk (0x80000UL)
17017 #define PORT7_OMR_PR4_Pos (20UL)
17018 #define PORT7_OMR_PR4_Msk (0x100000UL)
17019 #define PORT7_OMR_PR5_Pos (21UL)
17020 #define PORT7_OMR_PR5_Msk (0x200000UL)
17021 #define PORT7_OMR_PR6_Pos (22UL)
17022 #define PORT7_OMR_PR6_Msk (0x400000UL)
17023 #define PORT7_OMR_PR7_Pos (23UL)
17024 #define PORT7_OMR_PR7_Msk (0x800000UL)
17025 #define PORT7_OMR_PR8_Pos (24UL)
17026 #define PORT7_OMR_PR8_Msk (0x1000000UL)
17027 #define PORT7_OMR_PR9_Pos (25UL)
17028 #define PORT7_OMR_PR9_Msk (0x2000000UL)
17029 #define PORT7_OMR_PR10_Pos (26UL)
17030 #define PORT7_OMR_PR10_Msk (0x4000000UL)
17031 #define PORT7_OMR_PR11_Pos (27UL)
17032 #define PORT7_OMR_PR11_Msk (0x8000000UL)
17033 #define PORT7_OMR_PR12_Pos (28UL)
17034 #define PORT7_OMR_PR12_Msk (0x10000000UL)
17035 #define PORT7_OMR_PR13_Pos (29UL)
17036 #define PORT7_OMR_PR13_Msk (0x20000000UL)
17037 #define PORT7_OMR_PR14_Pos (30UL)
17038 #define PORT7_OMR_PR14_Msk (0x40000000UL)
17039 #define PORT7_OMR_PR15_Pos (31UL)
17040 #define PORT7_OMR_PR15_Msk (0x80000000UL)
17042 /* --------------------------------- PORT7_IOCR0 -------------------------------- */
17043 #define PORT7_IOCR0_PC0_Pos (3UL)
17044 #define PORT7_IOCR0_PC0_Msk (0xf8UL)
17045 #define PORT7_IOCR0_PC1_Pos (11UL)
17046 #define PORT7_IOCR0_PC1_Msk (0xf800UL)
17047 #define PORT7_IOCR0_PC2_Pos (19UL)
17048 #define PORT7_IOCR0_PC2_Msk (0xf80000UL)
17049 #define PORT7_IOCR0_PC3_Pos (27UL)
17050 #define PORT7_IOCR0_PC3_Msk (0xf8000000UL)
17052 /* --------------------------------- PORT7_IOCR4 -------------------------------- */
17053 #define PORT7_IOCR4_PC4_Pos (3UL)
17054 #define PORT7_IOCR4_PC4_Msk (0xf8UL)
17055 #define PORT7_IOCR4_PC5_Pos (11UL)
17056 #define PORT7_IOCR4_PC5_Msk (0xf800UL)
17057 #define PORT7_IOCR4_PC6_Pos (19UL)
17058 #define PORT7_IOCR4_PC6_Msk (0xf80000UL)
17059 #define PORT7_IOCR4_PC7_Pos (27UL)
17060 #define PORT7_IOCR4_PC7_Msk (0xf8000000UL)
17062 /* --------------------------------- PORT7_IOCR8 -------------------------------- */
17063 #define PORT7_IOCR8_PC8_Pos (3UL)
17064 #define PORT7_IOCR8_PC8_Msk (0xf8UL)
17065 #define PORT7_IOCR8_PC9_Pos (11UL)
17066 #define PORT7_IOCR8_PC9_Msk (0xf800UL)
17067 #define PORT7_IOCR8_PC10_Pos (19UL)
17068 #define PORT7_IOCR8_PC10_Msk (0xf80000UL)
17069 #define PORT7_IOCR8_PC11_Pos (27UL)
17070 #define PORT7_IOCR8_PC11_Msk (0xf8000000UL)
17072 /* ---------------------------------- PORT7_IN ---------------------------------- */
17073 #define PORT7_IN_P0_Pos (0UL)
17074 #define PORT7_IN_P0_Msk (0x1UL)
17075 #define PORT7_IN_P1_Pos (1UL)
17076 #define PORT7_IN_P1_Msk (0x2UL)
17077 #define PORT7_IN_P2_Pos (2UL)
17078 #define PORT7_IN_P2_Msk (0x4UL)
17079 #define PORT7_IN_P3_Pos (3UL)
17080 #define PORT7_IN_P3_Msk (0x8UL)
17081 #define PORT7_IN_P4_Pos (4UL)
17082 #define PORT7_IN_P4_Msk (0x10UL)
17083 #define PORT7_IN_P5_Pos (5UL)
17084 #define PORT7_IN_P5_Msk (0x20UL)
17085 #define PORT7_IN_P6_Pos (6UL)
17086 #define PORT7_IN_P6_Msk (0x40UL)
17087 #define PORT7_IN_P7_Pos (7UL)
17088 #define PORT7_IN_P7_Msk (0x80UL)
17089 #define PORT7_IN_P8_Pos (8UL)
17090 #define PORT7_IN_P8_Msk (0x100UL)
17091 #define PORT7_IN_P9_Pos (9UL)
17092 #define PORT7_IN_P9_Msk (0x200UL)
17093 #define PORT7_IN_P10_Pos (10UL)
17094 #define PORT7_IN_P10_Msk (0x400UL)
17095 #define PORT7_IN_P11_Pos (11UL)
17096 #define PORT7_IN_P11_Msk (0x800UL)
17097 #define PORT7_IN_P12_Pos (12UL)
17098 #define PORT7_IN_P12_Msk (0x1000UL)
17099 #define PORT7_IN_P13_Pos (13UL)
17100 #define PORT7_IN_P13_Msk (0x2000UL)
17101 #define PORT7_IN_P14_Pos (14UL)
17102 #define PORT7_IN_P14_Msk (0x4000UL)
17103 #define PORT7_IN_P15_Pos (15UL)
17104 #define PORT7_IN_P15_Msk (0x8000UL)
17106 /* --------------------------------- PORT7_PDR0 --------------------------------- */
17107 #define PORT7_PDR0_PD0_Pos (0UL)
17108 #define PORT7_PDR0_PD0_Msk (0x7UL)
17109 #define PORT7_PDR0_PD1_Pos (4UL)
17110 #define PORT7_PDR0_PD1_Msk (0x70UL)
17111 #define PORT7_PDR0_PD2_Pos (8UL)
17112 #define PORT7_PDR0_PD2_Msk (0x700UL)
17113 #define PORT7_PDR0_PD3_Pos (12UL)
17114 #define PORT7_PDR0_PD3_Msk (0x7000UL)
17115 #define PORT7_PDR0_PD4_Pos (16UL)
17116 #define PORT7_PDR0_PD4_Msk (0x70000UL)
17117 #define PORT7_PDR0_PD5_Pos (20UL)
17118 #define PORT7_PDR0_PD5_Msk (0x700000UL)
17119 #define PORT7_PDR0_PD6_Pos (24UL)
17120 #define PORT7_PDR0_PD6_Msk (0x7000000UL)
17121 #define PORT7_PDR0_PD7_Pos (28UL)
17122 #define PORT7_PDR0_PD7_Msk (0x70000000UL)
17124 /* --------------------------------- PORT7_PDR1 --------------------------------- */
17125 #define PORT7_PDR1_PD8_Pos (0UL)
17126 #define PORT7_PDR1_PD8_Msk (0x7UL)
17127 #define PORT7_PDR1_PD9_Pos (4UL)
17128 #define PORT7_PDR1_PD9_Msk (0x70UL)
17129 #define PORT7_PDR1_PD10_Pos (8UL)
17130 #define PORT7_PDR1_PD10_Msk (0x700UL)
17131 #define PORT7_PDR1_PD11_Pos (12UL)
17132 #define PORT7_PDR1_PD11_Msk (0x7000UL)
17133 #define PORT7_PDR1_PD12_Pos (16UL)
17134 #define PORT7_PDR1_PD12_Msk (0x70000UL)
17135 #define PORT7_PDR1_PD13_Pos (20UL)
17136 #define PORT7_PDR1_PD13_Msk (0x700000UL)
17137 #define PORT7_PDR1_PD14_Pos (24UL)
17138 #define PORT7_PDR1_PD14_Msk (0x7000000UL)
17139 #define PORT7_PDR1_PD15_Pos (28UL)
17140 #define PORT7_PDR1_PD15_Msk (0x70000000UL)
17142 /* --------------------------------- PORT7_PDISC -------------------------------- */
17143 #define PORT7_PDISC_PDIS0_Pos (0UL)
17144 #define PORT7_PDISC_PDIS0_Msk (0x1UL)
17145 #define PORT7_PDISC_PDIS1_Pos (1UL)
17146 #define PORT7_PDISC_PDIS1_Msk (0x2UL)
17147 #define PORT7_PDISC_PDIS2_Pos (2UL)
17148 #define PORT7_PDISC_PDIS2_Msk (0x4UL)
17149 #define PORT7_PDISC_PDIS3_Pos (3UL)
17150 #define PORT7_PDISC_PDIS3_Msk (0x8UL)
17151 #define PORT7_PDISC_PDIS4_Pos (4UL)
17152 #define PORT7_PDISC_PDIS4_Msk (0x10UL)
17153 #define PORT7_PDISC_PDIS5_Pos (5UL)
17154 #define PORT7_PDISC_PDIS5_Msk (0x20UL)
17155 #define PORT7_PDISC_PDIS6_Pos (6UL)
17156 #define PORT7_PDISC_PDIS6_Msk (0x40UL)
17157 #define PORT7_PDISC_PDIS7_Pos (7UL)
17158 #define PORT7_PDISC_PDIS7_Msk (0x80UL)
17159 #define PORT7_PDISC_PDIS8_Pos (8UL)
17160 #define PORT7_PDISC_PDIS8_Msk (0x100UL)
17161 #define PORT7_PDISC_PDIS9_Pos (9UL)
17162 #define PORT7_PDISC_PDIS9_Msk (0x200UL)
17163 #define PORT7_PDISC_PDIS10_Pos (10UL)
17164 #define PORT7_PDISC_PDIS10_Msk (0x400UL)
17165 #define PORT7_PDISC_PDIS11_Pos (11UL)
17166 #define PORT7_PDISC_PDIS11_Msk (0x800UL)
17167 #define PORT7_PDISC_PDIS12_Pos (12UL)
17168 #define PORT7_PDISC_PDIS12_Msk (0x1000UL)
17169 #define PORT7_PDISC_PDIS13_Pos (13UL)
17170 #define PORT7_PDISC_PDIS13_Msk (0x2000UL)
17171 #define PORT7_PDISC_PDIS14_Pos (14UL)
17172 #define PORT7_PDISC_PDIS14_Msk (0x4000UL)
17173 #define PORT7_PDISC_PDIS15_Pos (15UL)
17174 #define PORT7_PDISC_PDIS15_Msk (0x8000UL)
17176 /* ---------------------------------- PORT7_PPS --------------------------------- */
17177 #define PORT7_PPS_PPS0_Pos (0UL)
17178 #define PORT7_PPS_PPS0_Msk (0x1UL)
17179 #define PORT7_PPS_PPS1_Pos (1UL)
17180 #define PORT7_PPS_PPS1_Msk (0x2UL)
17181 #define PORT7_PPS_PPS2_Pos (2UL)
17182 #define PORT7_PPS_PPS2_Msk (0x4UL)
17183 #define PORT7_PPS_PPS3_Pos (3UL)
17184 #define PORT7_PPS_PPS3_Msk (0x8UL)
17185 #define PORT7_PPS_PPS4_Pos (4UL)
17186 #define PORT7_PPS_PPS4_Msk (0x10UL)
17187 #define PORT7_PPS_PPS5_Pos (5UL)
17188 #define PORT7_PPS_PPS5_Msk (0x20UL)
17189 #define PORT7_PPS_PPS6_Pos (6UL)
17190 #define PORT7_PPS_PPS6_Msk (0x40UL)
17191 #define PORT7_PPS_PPS7_Pos (7UL)
17192 #define PORT7_PPS_PPS7_Msk (0x80UL)
17193 #define PORT7_PPS_PPS8_Pos (8UL)
17194 #define PORT7_PPS_PPS8_Msk (0x100UL)
17195 #define PORT7_PPS_PPS9_Pos (9UL)
17196 #define PORT7_PPS_PPS9_Msk (0x200UL)
17197 #define PORT7_PPS_PPS10_Pos (10UL)
17198 #define PORT7_PPS_PPS10_Msk (0x400UL)
17199 #define PORT7_PPS_PPS11_Pos (11UL)
17200 #define PORT7_PPS_PPS11_Msk (0x800UL)
17201 #define PORT7_PPS_PPS12_Pos (12UL)
17202 #define PORT7_PPS_PPS12_Msk (0x1000UL)
17203 #define PORT7_PPS_PPS13_Pos (13UL)
17204 #define PORT7_PPS_PPS13_Msk (0x2000UL)
17205 #define PORT7_PPS_PPS14_Pos (14UL)
17206 #define PORT7_PPS_PPS14_Msk (0x4000UL)
17207 #define PORT7_PPS_PPS15_Pos (15UL)
17208 #define PORT7_PPS_PPS15_Msk (0x8000UL)
17210 /* --------------------------------- PORT7_HWSEL -------------------------------- */
17211 #define PORT7_HWSEL_HW0_Pos (0UL)
17212 #define PORT7_HWSEL_HW0_Msk (0x3UL)
17213 #define PORT7_HWSEL_HW1_Pos (2UL)
17214 #define PORT7_HWSEL_HW1_Msk (0xcUL)
17215 #define PORT7_HWSEL_HW2_Pos (4UL)
17216 #define PORT7_HWSEL_HW2_Msk (0x30UL)
17217 #define PORT7_HWSEL_HW3_Pos (6UL)
17218 #define PORT7_HWSEL_HW3_Msk (0xc0UL)
17219 #define PORT7_HWSEL_HW4_Pos (8UL)
17220 #define PORT7_HWSEL_HW4_Msk (0x300UL)
17221 #define PORT7_HWSEL_HW5_Pos (10UL)
17222 #define PORT7_HWSEL_HW5_Msk (0xc00UL)
17223 #define PORT7_HWSEL_HW6_Pos (12UL)
17224 #define PORT7_HWSEL_HW6_Msk (0x3000UL)
17225 #define PORT7_HWSEL_HW7_Pos (14UL)
17226 #define PORT7_HWSEL_HW7_Msk (0xc000UL)
17227 #define PORT7_HWSEL_HW8_Pos (16UL)
17228 #define PORT7_HWSEL_HW8_Msk (0x30000UL)
17229 #define PORT7_HWSEL_HW9_Pos (18UL)
17230 #define PORT7_HWSEL_HW9_Msk (0xc0000UL)
17231 #define PORT7_HWSEL_HW10_Pos (20UL)
17232 #define PORT7_HWSEL_HW10_Msk (0x300000UL)
17233 #define PORT7_HWSEL_HW11_Pos (22UL)
17234 #define PORT7_HWSEL_HW11_Msk (0xc00000UL)
17235 #define PORT7_HWSEL_HW12_Pos (24UL)
17236 #define PORT7_HWSEL_HW12_Msk (0x3000000UL)
17237 #define PORT7_HWSEL_HW13_Pos (26UL)
17238 #define PORT7_HWSEL_HW13_Msk (0xc000000UL)
17239 #define PORT7_HWSEL_HW14_Pos (28UL)
17240 #define PORT7_HWSEL_HW14_Msk (0x30000000UL)
17241 #define PORT7_HWSEL_HW15_Pos (30UL)
17242 #define PORT7_HWSEL_HW15_Msk (0xc0000000UL)
17245 /* ================================================================================ */
17246 /* ================ struct 'PORT8' Position & Mask ================ */
17247 /* ================================================================================ */
17248 
17249 
17250 /* ---------------------------------- PORT8_OUT --------------------------------- */
17251 #define PORT8_OUT_P0_Pos (0UL)
17252 #define PORT8_OUT_P0_Msk (0x1UL)
17253 #define PORT8_OUT_P1_Pos (1UL)
17254 #define PORT8_OUT_P1_Msk (0x2UL)
17255 #define PORT8_OUT_P2_Pos (2UL)
17256 #define PORT8_OUT_P2_Msk (0x4UL)
17257 #define PORT8_OUT_P3_Pos (3UL)
17258 #define PORT8_OUT_P3_Msk (0x8UL)
17259 #define PORT8_OUT_P4_Pos (4UL)
17260 #define PORT8_OUT_P4_Msk (0x10UL)
17261 #define PORT8_OUT_P5_Pos (5UL)
17262 #define PORT8_OUT_P5_Msk (0x20UL)
17263 #define PORT8_OUT_P6_Pos (6UL)
17264 #define PORT8_OUT_P6_Msk (0x40UL)
17265 #define PORT8_OUT_P7_Pos (7UL)
17266 #define PORT8_OUT_P7_Msk (0x80UL)
17267 #define PORT8_OUT_P8_Pos (8UL)
17268 #define PORT8_OUT_P8_Msk (0x100UL)
17269 #define PORT8_OUT_P9_Pos (9UL)
17270 #define PORT8_OUT_P9_Msk (0x200UL)
17271 #define PORT8_OUT_P10_Pos (10UL)
17272 #define PORT8_OUT_P10_Msk (0x400UL)
17273 #define PORT8_OUT_P11_Pos (11UL)
17274 #define PORT8_OUT_P11_Msk (0x800UL)
17275 #define PORT8_OUT_P12_Pos (12UL)
17276 #define PORT8_OUT_P12_Msk (0x1000UL)
17277 #define PORT8_OUT_P13_Pos (13UL)
17278 #define PORT8_OUT_P13_Msk (0x2000UL)
17279 #define PORT8_OUT_P14_Pos (14UL)
17280 #define PORT8_OUT_P14_Msk (0x4000UL)
17281 #define PORT8_OUT_P15_Pos (15UL)
17282 #define PORT8_OUT_P15_Msk (0x8000UL)
17284 /* ---------------------------------- PORT8_OMR --------------------------------- */
17285 #define PORT8_OMR_PS0_Pos (0UL)
17286 #define PORT8_OMR_PS0_Msk (0x1UL)
17287 #define PORT8_OMR_PS1_Pos (1UL)
17288 #define PORT8_OMR_PS1_Msk (0x2UL)
17289 #define PORT8_OMR_PS2_Pos (2UL)
17290 #define PORT8_OMR_PS2_Msk (0x4UL)
17291 #define PORT8_OMR_PS3_Pos (3UL)
17292 #define PORT8_OMR_PS3_Msk (0x8UL)
17293 #define PORT8_OMR_PS4_Pos (4UL)
17294 #define PORT8_OMR_PS4_Msk (0x10UL)
17295 #define PORT8_OMR_PS5_Pos (5UL)
17296 #define PORT8_OMR_PS5_Msk (0x20UL)
17297 #define PORT8_OMR_PS6_Pos (6UL)
17298 #define PORT8_OMR_PS6_Msk (0x40UL)
17299 #define PORT8_OMR_PS7_Pos (7UL)
17300 #define PORT8_OMR_PS7_Msk (0x80UL)
17301 #define PORT8_OMR_PS8_Pos (8UL)
17302 #define PORT8_OMR_PS8_Msk (0x100UL)
17303 #define PORT8_OMR_PS9_Pos (9UL)
17304 #define PORT8_OMR_PS9_Msk (0x200UL)
17305 #define PORT8_OMR_PS10_Pos (10UL)
17306 #define PORT8_OMR_PS10_Msk (0x400UL)
17307 #define PORT8_OMR_PS11_Pos (11UL)
17308 #define PORT8_OMR_PS11_Msk (0x800UL)
17309 #define PORT8_OMR_PS12_Pos (12UL)
17310 #define PORT8_OMR_PS12_Msk (0x1000UL)
17311 #define PORT8_OMR_PS13_Pos (13UL)
17312 #define PORT8_OMR_PS13_Msk (0x2000UL)
17313 #define PORT8_OMR_PS14_Pos (14UL)
17314 #define PORT8_OMR_PS14_Msk (0x4000UL)
17315 #define PORT8_OMR_PS15_Pos (15UL)
17316 #define PORT8_OMR_PS15_Msk (0x8000UL)
17317 #define PORT8_OMR_PR0_Pos (16UL)
17318 #define PORT8_OMR_PR0_Msk (0x10000UL)
17319 #define PORT8_OMR_PR1_Pos (17UL)
17320 #define PORT8_OMR_PR1_Msk (0x20000UL)
17321 #define PORT8_OMR_PR2_Pos (18UL)
17322 #define PORT8_OMR_PR2_Msk (0x40000UL)
17323 #define PORT8_OMR_PR3_Pos (19UL)
17324 #define PORT8_OMR_PR3_Msk (0x80000UL)
17325 #define PORT8_OMR_PR4_Pos (20UL)
17326 #define PORT8_OMR_PR4_Msk (0x100000UL)
17327 #define PORT8_OMR_PR5_Pos (21UL)
17328 #define PORT8_OMR_PR5_Msk (0x200000UL)
17329 #define PORT8_OMR_PR6_Pos (22UL)
17330 #define PORT8_OMR_PR6_Msk (0x400000UL)
17331 #define PORT8_OMR_PR7_Pos (23UL)
17332 #define PORT8_OMR_PR7_Msk (0x800000UL)
17333 #define PORT8_OMR_PR8_Pos (24UL)
17334 #define PORT8_OMR_PR8_Msk (0x1000000UL)
17335 #define PORT8_OMR_PR9_Pos (25UL)
17336 #define PORT8_OMR_PR9_Msk (0x2000000UL)
17337 #define PORT8_OMR_PR10_Pos (26UL)
17338 #define PORT8_OMR_PR10_Msk (0x4000000UL)
17339 #define PORT8_OMR_PR11_Pos (27UL)
17340 #define PORT8_OMR_PR11_Msk (0x8000000UL)
17341 #define PORT8_OMR_PR12_Pos (28UL)
17342 #define PORT8_OMR_PR12_Msk (0x10000000UL)
17343 #define PORT8_OMR_PR13_Pos (29UL)
17344 #define PORT8_OMR_PR13_Msk (0x20000000UL)
17345 #define PORT8_OMR_PR14_Pos (30UL)
17346 #define PORT8_OMR_PR14_Msk (0x40000000UL)
17347 #define PORT8_OMR_PR15_Pos (31UL)
17348 #define PORT8_OMR_PR15_Msk (0x80000000UL)
17350 /* --------------------------------- PORT8_IOCR0 -------------------------------- */
17351 #define PORT8_IOCR0_PC0_Pos (3UL)
17352 #define PORT8_IOCR0_PC0_Msk (0xf8UL)
17353 #define PORT8_IOCR0_PC1_Pos (11UL)
17354 #define PORT8_IOCR0_PC1_Msk (0xf800UL)
17355 #define PORT8_IOCR0_PC2_Pos (19UL)
17356 #define PORT8_IOCR0_PC2_Msk (0xf80000UL)
17357 #define PORT8_IOCR0_PC3_Pos (27UL)
17358 #define PORT8_IOCR0_PC3_Msk (0xf8000000UL)
17360 /* --------------------------------- PORT8_IOCR4 -------------------------------- */
17361 #define PORT8_IOCR4_PC4_Pos (3UL)
17362 #define PORT8_IOCR4_PC4_Msk (0xf8UL)
17363 #define PORT8_IOCR4_PC5_Pos (11UL)
17364 #define PORT8_IOCR4_PC5_Msk (0xf800UL)
17365 #define PORT8_IOCR4_PC6_Pos (19UL)
17366 #define PORT8_IOCR4_PC6_Msk (0xf80000UL)
17367 #define PORT8_IOCR4_PC7_Pos (27UL)
17368 #define PORT8_IOCR4_PC7_Msk (0xf8000000UL)
17370 /* --------------------------------- PORT8_IOCR8 -------------------------------- */
17371 #define PORT8_IOCR8_PC8_Pos (3UL)
17372 #define PORT8_IOCR8_PC8_Msk (0xf8UL)
17373 #define PORT8_IOCR8_PC9_Pos (11UL)
17374 #define PORT8_IOCR8_PC9_Msk (0xf800UL)
17375 #define PORT8_IOCR8_PC10_Pos (19UL)
17376 #define PORT8_IOCR8_PC10_Msk (0xf80000UL)
17377 #define PORT8_IOCR8_PC11_Pos (27UL)
17378 #define PORT8_IOCR8_PC11_Msk (0xf8000000UL)
17380 /* ---------------------------------- PORT8_IN ---------------------------------- */
17381 #define PORT8_IN_P0_Pos (0UL)
17382 #define PORT8_IN_P0_Msk (0x1UL)
17383 #define PORT8_IN_P1_Pos (1UL)
17384 #define PORT8_IN_P1_Msk (0x2UL)
17385 #define PORT8_IN_P2_Pos (2UL)
17386 #define PORT8_IN_P2_Msk (0x4UL)
17387 #define PORT8_IN_P3_Pos (3UL)
17388 #define PORT8_IN_P3_Msk (0x8UL)
17389 #define PORT8_IN_P4_Pos (4UL)
17390 #define PORT8_IN_P4_Msk (0x10UL)
17391 #define PORT8_IN_P5_Pos (5UL)
17392 #define PORT8_IN_P5_Msk (0x20UL)
17393 #define PORT8_IN_P6_Pos (6UL)
17394 #define PORT8_IN_P6_Msk (0x40UL)
17395 #define PORT8_IN_P7_Pos (7UL)
17396 #define PORT8_IN_P7_Msk (0x80UL)
17397 #define PORT8_IN_P8_Pos (8UL)
17398 #define PORT8_IN_P8_Msk (0x100UL)
17399 #define PORT8_IN_P9_Pos (9UL)
17400 #define PORT8_IN_P9_Msk (0x200UL)
17401 #define PORT8_IN_P10_Pos (10UL)
17402 #define PORT8_IN_P10_Msk (0x400UL)
17403 #define PORT8_IN_P11_Pos (11UL)
17404 #define PORT8_IN_P11_Msk (0x800UL)
17405 #define PORT8_IN_P12_Pos (12UL)
17406 #define PORT8_IN_P12_Msk (0x1000UL)
17407 #define PORT8_IN_P13_Pos (13UL)
17408 #define PORT8_IN_P13_Msk (0x2000UL)
17409 #define PORT8_IN_P14_Pos (14UL)
17410 #define PORT8_IN_P14_Msk (0x4000UL)
17411 #define PORT8_IN_P15_Pos (15UL)
17412 #define PORT8_IN_P15_Msk (0x8000UL)
17414 /* --------------------------------- PORT8_PDR0 --------------------------------- */
17415 #define PORT8_PDR0_PD0_Pos (0UL)
17416 #define PORT8_PDR0_PD0_Msk (0x7UL)
17417 #define PORT8_PDR0_PD1_Pos (4UL)
17418 #define PORT8_PDR0_PD1_Msk (0x70UL)
17419 #define PORT8_PDR0_PD2_Pos (8UL)
17420 #define PORT8_PDR0_PD2_Msk (0x700UL)
17421 #define PORT8_PDR0_PD3_Pos (12UL)
17422 #define PORT8_PDR0_PD3_Msk (0x7000UL)
17423 #define PORT8_PDR0_PD4_Pos (16UL)
17424 #define PORT8_PDR0_PD4_Msk (0x70000UL)
17425 #define PORT8_PDR0_PD5_Pos (20UL)
17426 #define PORT8_PDR0_PD5_Msk (0x700000UL)
17427 #define PORT8_PDR0_PD6_Pos (24UL)
17428 #define PORT8_PDR0_PD6_Msk (0x7000000UL)
17429 #define PORT8_PDR0_PD7_Pos (28UL)
17430 #define PORT8_PDR0_PD7_Msk (0x70000000UL)
17432 /* --------------------------------- PORT8_PDR1 --------------------------------- */
17433 #define PORT8_PDR1_PD8_Pos (0UL)
17434 #define PORT8_PDR1_PD8_Msk (0x7UL)
17435 #define PORT8_PDR1_PD9_Pos (4UL)
17436 #define PORT8_PDR1_PD9_Msk (0x70UL)
17437 #define PORT8_PDR1_PD10_Pos (8UL)
17438 #define PORT8_PDR1_PD10_Msk (0x700UL)
17439 #define PORT8_PDR1_PD11_Pos (12UL)
17440 #define PORT8_PDR1_PD11_Msk (0x7000UL)
17441 #define PORT8_PDR1_PD12_Pos (16UL)
17442 #define PORT8_PDR1_PD12_Msk (0x70000UL)
17443 #define PORT8_PDR1_PD13_Pos (20UL)
17444 #define PORT8_PDR1_PD13_Msk (0x700000UL)
17445 #define PORT8_PDR1_PD14_Pos (24UL)
17446 #define PORT8_PDR1_PD14_Msk (0x7000000UL)
17447 #define PORT8_PDR1_PD15_Pos (28UL)
17448 #define PORT8_PDR1_PD15_Msk (0x70000000UL)
17450 /* --------------------------------- PORT8_PDISC -------------------------------- */
17451 #define PORT8_PDISC_PDIS0_Pos (0UL)
17452 #define PORT8_PDISC_PDIS0_Msk (0x1UL)
17453 #define PORT8_PDISC_PDIS1_Pos (1UL)
17454 #define PORT8_PDISC_PDIS1_Msk (0x2UL)
17455 #define PORT8_PDISC_PDIS2_Pos (2UL)
17456 #define PORT8_PDISC_PDIS2_Msk (0x4UL)
17457 #define PORT8_PDISC_PDIS3_Pos (3UL)
17458 #define PORT8_PDISC_PDIS3_Msk (0x8UL)
17459 #define PORT8_PDISC_PDIS4_Pos (4UL)
17460 #define PORT8_PDISC_PDIS4_Msk (0x10UL)
17461 #define PORT8_PDISC_PDIS5_Pos (5UL)
17462 #define PORT8_PDISC_PDIS5_Msk (0x20UL)
17463 #define PORT8_PDISC_PDIS6_Pos (6UL)
17464 #define PORT8_PDISC_PDIS6_Msk (0x40UL)
17465 #define PORT8_PDISC_PDIS7_Pos (7UL)
17466 #define PORT8_PDISC_PDIS7_Msk (0x80UL)
17467 #define PORT8_PDISC_PDIS8_Pos (8UL)
17468 #define PORT8_PDISC_PDIS8_Msk (0x100UL)
17469 #define PORT8_PDISC_PDIS9_Pos (9UL)
17470 #define PORT8_PDISC_PDIS9_Msk (0x200UL)
17471 #define PORT8_PDISC_PDIS10_Pos (10UL)
17472 #define PORT8_PDISC_PDIS10_Msk (0x400UL)
17473 #define PORT8_PDISC_PDIS11_Pos (11UL)
17474 #define PORT8_PDISC_PDIS11_Msk (0x800UL)
17475 #define PORT8_PDISC_PDIS12_Pos (12UL)
17476 #define PORT8_PDISC_PDIS12_Msk (0x1000UL)
17477 #define PORT8_PDISC_PDIS13_Pos (13UL)
17478 #define PORT8_PDISC_PDIS13_Msk (0x2000UL)
17479 #define PORT8_PDISC_PDIS14_Pos (14UL)
17480 #define PORT8_PDISC_PDIS14_Msk (0x4000UL)
17481 #define PORT8_PDISC_PDIS15_Pos (15UL)
17482 #define PORT8_PDISC_PDIS15_Msk (0x8000UL)
17484 /* ---------------------------------- PORT8_PPS --------------------------------- */
17485 #define PORT8_PPS_PPS0_Pos (0UL)
17486 #define PORT8_PPS_PPS0_Msk (0x1UL)
17487 #define PORT8_PPS_PPS1_Pos (1UL)
17488 #define PORT8_PPS_PPS1_Msk (0x2UL)
17489 #define PORT8_PPS_PPS2_Pos (2UL)
17490 #define PORT8_PPS_PPS2_Msk (0x4UL)
17491 #define PORT8_PPS_PPS3_Pos (3UL)
17492 #define PORT8_PPS_PPS3_Msk (0x8UL)
17493 #define PORT8_PPS_PPS4_Pos (4UL)
17494 #define PORT8_PPS_PPS4_Msk (0x10UL)
17495 #define PORT8_PPS_PPS5_Pos (5UL)
17496 #define PORT8_PPS_PPS5_Msk (0x20UL)
17497 #define PORT8_PPS_PPS6_Pos (6UL)
17498 #define PORT8_PPS_PPS6_Msk (0x40UL)
17499 #define PORT8_PPS_PPS7_Pos (7UL)
17500 #define PORT8_PPS_PPS7_Msk (0x80UL)
17501 #define PORT8_PPS_PPS8_Pos (8UL)
17502 #define PORT8_PPS_PPS8_Msk (0x100UL)
17503 #define PORT8_PPS_PPS9_Pos (9UL)
17504 #define PORT8_PPS_PPS9_Msk (0x200UL)
17505 #define PORT8_PPS_PPS10_Pos (10UL)
17506 #define PORT8_PPS_PPS10_Msk (0x400UL)
17507 #define PORT8_PPS_PPS11_Pos (11UL)
17508 #define PORT8_PPS_PPS11_Msk (0x800UL)
17509 #define PORT8_PPS_PPS12_Pos (12UL)
17510 #define PORT8_PPS_PPS12_Msk (0x1000UL)
17511 #define PORT8_PPS_PPS13_Pos (13UL)
17512 #define PORT8_PPS_PPS13_Msk (0x2000UL)
17513 #define PORT8_PPS_PPS14_Pos (14UL)
17514 #define PORT8_PPS_PPS14_Msk (0x4000UL)
17515 #define PORT8_PPS_PPS15_Pos (15UL)
17516 #define PORT8_PPS_PPS15_Msk (0x8000UL)
17518 /* --------------------------------- PORT8_HWSEL -------------------------------- */
17519 #define PORT8_HWSEL_HW0_Pos (0UL)
17520 #define PORT8_HWSEL_HW0_Msk (0x3UL)
17521 #define PORT8_HWSEL_HW1_Pos (2UL)
17522 #define PORT8_HWSEL_HW1_Msk (0xcUL)
17523 #define PORT8_HWSEL_HW2_Pos (4UL)
17524 #define PORT8_HWSEL_HW2_Msk (0x30UL)
17525 #define PORT8_HWSEL_HW3_Pos (6UL)
17526 #define PORT8_HWSEL_HW3_Msk (0xc0UL)
17527 #define PORT8_HWSEL_HW4_Pos (8UL)
17528 #define PORT8_HWSEL_HW4_Msk (0x300UL)
17529 #define PORT8_HWSEL_HW5_Pos (10UL)
17530 #define PORT8_HWSEL_HW5_Msk (0xc00UL)
17531 #define PORT8_HWSEL_HW6_Pos (12UL)
17532 #define PORT8_HWSEL_HW6_Msk (0x3000UL)
17533 #define PORT8_HWSEL_HW7_Pos (14UL)
17534 #define PORT8_HWSEL_HW7_Msk (0xc000UL)
17535 #define PORT8_HWSEL_HW8_Pos (16UL)
17536 #define PORT8_HWSEL_HW8_Msk (0x30000UL)
17537 #define PORT8_HWSEL_HW9_Pos (18UL)
17538 #define PORT8_HWSEL_HW9_Msk (0xc0000UL)
17539 #define PORT8_HWSEL_HW10_Pos (20UL)
17540 #define PORT8_HWSEL_HW10_Msk (0x300000UL)
17541 #define PORT8_HWSEL_HW11_Pos (22UL)
17542 #define PORT8_HWSEL_HW11_Msk (0xc00000UL)
17543 #define PORT8_HWSEL_HW12_Pos (24UL)
17544 #define PORT8_HWSEL_HW12_Msk (0x3000000UL)
17545 #define PORT8_HWSEL_HW13_Pos (26UL)
17546 #define PORT8_HWSEL_HW13_Msk (0xc000000UL)
17547 #define PORT8_HWSEL_HW14_Pos (28UL)
17548 #define PORT8_HWSEL_HW14_Msk (0x30000000UL)
17549 #define PORT8_HWSEL_HW15_Pos (30UL)
17550 #define PORT8_HWSEL_HW15_Msk (0xc0000000UL)
17553 /* ================================================================================ */
17554 /* ================ struct 'PORT9' Position & Mask ================ */
17555 /* ================================================================================ */
17556 
17557 
17558 /* ---------------------------------- PORT9_OUT --------------------------------- */
17559 #define PORT9_OUT_P0_Pos (0UL)
17560 #define PORT9_OUT_P0_Msk (0x1UL)
17561 #define PORT9_OUT_P1_Pos (1UL)
17562 #define PORT9_OUT_P1_Msk (0x2UL)
17563 #define PORT9_OUT_P2_Pos (2UL)
17564 #define PORT9_OUT_P2_Msk (0x4UL)
17565 #define PORT9_OUT_P3_Pos (3UL)
17566 #define PORT9_OUT_P3_Msk (0x8UL)
17567 #define PORT9_OUT_P4_Pos (4UL)
17568 #define PORT9_OUT_P4_Msk (0x10UL)
17569 #define PORT9_OUT_P5_Pos (5UL)
17570 #define PORT9_OUT_P5_Msk (0x20UL)
17571 #define PORT9_OUT_P6_Pos (6UL)
17572 #define PORT9_OUT_P6_Msk (0x40UL)
17573 #define PORT9_OUT_P7_Pos (7UL)
17574 #define PORT9_OUT_P7_Msk (0x80UL)
17575 #define PORT9_OUT_P8_Pos (8UL)
17576 #define PORT9_OUT_P8_Msk (0x100UL)
17577 #define PORT9_OUT_P9_Pos (9UL)
17578 #define PORT9_OUT_P9_Msk (0x200UL)
17579 #define PORT9_OUT_P10_Pos (10UL)
17580 #define PORT9_OUT_P10_Msk (0x400UL)
17581 #define PORT9_OUT_P11_Pos (11UL)
17582 #define PORT9_OUT_P11_Msk (0x800UL)
17583 #define PORT9_OUT_P12_Pos (12UL)
17584 #define PORT9_OUT_P12_Msk (0x1000UL)
17585 #define PORT9_OUT_P13_Pos (13UL)
17586 #define PORT9_OUT_P13_Msk (0x2000UL)
17587 #define PORT9_OUT_P14_Pos (14UL)
17588 #define PORT9_OUT_P14_Msk (0x4000UL)
17589 #define PORT9_OUT_P15_Pos (15UL)
17590 #define PORT9_OUT_P15_Msk (0x8000UL)
17592 /* ---------------------------------- PORT9_OMR --------------------------------- */
17593 #define PORT9_OMR_PS0_Pos (0UL)
17594 #define PORT9_OMR_PS0_Msk (0x1UL)
17595 #define PORT9_OMR_PS1_Pos (1UL)
17596 #define PORT9_OMR_PS1_Msk (0x2UL)
17597 #define PORT9_OMR_PS2_Pos (2UL)
17598 #define PORT9_OMR_PS2_Msk (0x4UL)
17599 #define PORT9_OMR_PS3_Pos (3UL)
17600 #define PORT9_OMR_PS3_Msk (0x8UL)
17601 #define PORT9_OMR_PS4_Pos (4UL)
17602 #define PORT9_OMR_PS4_Msk (0x10UL)
17603 #define PORT9_OMR_PS5_Pos (5UL)
17604 #define PORT9_OMR_PS5_Msk (0x20UL)
17605 #define PORT9_OMR_PS6_Pos (6UL)
17606 #define PORT9_OMR_PS6_Msk (0x40UL)
17607 #define PORT9_OMR_PS7_Pos (7UL)
17608 #define PORT9_OMR_PS7_Msk (0x80UL)
17609 #define PORT9_OMR_PS8_Pos (8UL)
17610 #define PORT9_OMR_PS8_Msk (0x100UL)
17611 #define PORT9_OMR_PS9_Pos (9UL)
17612 #define PORT9_OMR_PS9_Msk (0x200UL)
17613 #define PORT9_OMR_PS10_Pos (10UL)
17614 #define PORT9_OMR_PS10_Msk (0x400UL)
17615 #define PORT9_OMR_PS11_Pos (11UL)
17616 #define PORT9_OMR_PS11_Msk (0x800UL)
17617 #define PORT9_OMR_PS12_Pos (12UL)
17618 #define PORT9_OMR_PS12_Msk (0x1000UL)
17619 #define PORT9_OMR_PS13_Pos (13UL)
17620 #define PORT9_OMR_PS13_Msk (0x2000UL)
17621 #define PORT9_OMR_PS14_Pos (14UL)
17622 #define PORT9_OMR_PS14_Msk (0x4000UL)
17623 #define PORT9_OMR_PS15_Pos (15UL)
17624 #define PORT9_OMR_PS15_Msk (0x8000UL)
17625 #define PORT9_OMR_PR0_Pos (16UL)
17626 #define PORT9_OMR_PR0_Msk (0x10000UL)
17627 #define PORT9_OMR_PR1_Pos (17UL)
17628 #define PORT9_OMR_PR1_Msk (0x20000UL)
17629 #define PORT9_OMR_PR2_Pos (18UL)
17630 #define PORT9_OMR_PR2_Msk (0x40000UL)
17631 #define PORT9_OMR_PR3_Pos (19UL)
17632 #define PORT9_OMR_PR3_Msk (0x80000UL)
17633 #define PORT9_OMR_PR4_Pos (20UL)
17634 #define PORT9_OMR_PR4_Msk (0x100000UL)
17635 #define PORT9_OMR_PR5_Pos (21UL)
17636 #define PORT9_OMR_PR5_Msk (0x200000UL)
17637 #define PORT9_OMR_PR6_Pos (22UL)
17638 #define PORT9_OMR_PR6_Msk (0x400000UL)
17639 #define PORT9_OMR_PR7_Pos (23UL)
17640 #define PORT9_OMR_PR7_Msk (0x800000UL)
17641 #define PORT9_OMR_PR8_Pos (24UL)
17642 #define PORT9_OMR_PR8_Msk (0x1000000UL)
17643 #define PORT9_OMR_PR9_Pos (25UL)
17644 #define PORT9_OMR_PR9_Msk (0x2000000UL)
17645 #define PORT9_OMR_PR10_Pos (26UL)
17646 #define PORT9_OMR_PR10_Msk (0x4000000UL)
17647 #define PORT9_OMR_PR11_Pos (27UL)
17648 #define PORT9_OMR_PR11_Msk (0x8000000UL)
17649 #define PORT9_OMR_PR12_Pos (28UL)
17650 #define PORT9_OMR_PR12_Msk (0x10000000UL)
17651 #define PORT9_OMR_PR13_Pos (29UL)
17652 #define PORT9_OMR_PR13_Msk (0x20000000UL)
17653 #define PORT9_OMR_PR14_Pos (30UL)
17654 #define PORT9_OMR_PR14_Msk (0x40000000UL)
17655 #define PORT9_OMR_PR15_Pos (31UL)
17656 #define PORT9_OMR_PR15_Msk (0x80000000UL)
17658 /* --------------------------------- PORT9_IOCR0 -------------------------------- */
17659 #define PORT9_IOCR0_PC0_Pos (3UL)
17660 #define PORT9_IOCR0_PC0_Msk (0xf8UL)
17661 #define PORT9_IOCR0_PC1_Pos (11UL)
17662 #define PORT9_IOCR0_PC1_Msk (0xf800UL)
17663 #define PORT9_IOCR0_PC2_Pos (19UL)
17664 #define PORT9_IOCR0_PC2_Msk (0xf80000UL)
17665 #define PORT9_IOCR0_PC3_Pos (27UL)
17666 #define PORT9_IOCR0_PC3_Msk (0xf8000000UL)
17668 /* --------------------------------- PORT9_IOCR4 -------------------------------- */
17669 #define PORT9_IOCR4_PC4_Pos (3UL)
17670 #define PORT9_IOCR4_PC4_Msk (0xf8UL)
17671 #define PORT9_IOCR4_PC5_Pos (11UL)
17672 #define PORT9_IOCR4_PC5_Msk (0xf800UL)
17673 #define PORT9_IOCR4_PC6_Pos (19UL)
17674 #define PORT9_IOCR4_PC6_Msk (0xf80000UL)
17675 #define PORT9_IOCR4_PC7_Pos (27UL)
17676 #define PORT9_IOCR4_PC7_Msk (0xf8000000UL)
17678 /* --------------------------------- PORT9_IOCR8 -------------------------------- */
17679 #define PORT9_IOCR8_PC8_Pos (3UL)
17680 #define PORT9_IOCR8_PC8_Msk (0xf8UL)
17681 #define PORT9_IOCR8_PC9_Pos (11UL)
17682 #define PORT9_IOCR8_PC9_Msk (0xf800UL)
17683 #define PORT9_IOCR8_PC10_Pos (19UL)
17684 #define PORT9_IOCR8_PC10_Msk (0xf80000UL)
17685 #define PORT9_IOCR8_PC11_Pos (27UL)
17686 #define PORT9_IOCR8_PC11_Msk (0xf8000000UL)
17688 /* ---------------------------------- PORT9_IN ---------------------------------- */
17689 #define PORT9_IN_P0_Pos (0UL)
17690 #define PORT9_IN_P0_Msk (0x1UL)
17691 #define PORT9_IN_P1_Pos (1UL)
17692 #define PORT9_IN_P1_Msk (0x2UL)
17693 #define PORT9_IN_P2_Pos (2UL)
17694 #define PORT9_IN_P2_Msk (0x4UL)
17695 #define PORT9_IN_P3_Pos (3UL)
17696 #define PORT9_IN_P3_Msk (0x8UL)
17697 #define PORT9_IN_P4_Pos (4UL)
17698 #define PORT9_IN_P4_Msk (0x10UL)
17699 #define PORT9_IN_P5_Pos (5UL)
17700 #define PORT9_IN_P5_Msk (0x20UL)
17701 #define PORT9_IN_P6_Pos (6UL)
17702 #define PORT9_IN_P6_Msk (0x40UL)
17703 #define PORT9_IN_P7_Pos (7UL)
17704 #define PORT9_IN_P7_Msk (0x80UL)
17705 #define PORT9_IN_P8_Pos (8UL)
17706 #define PORT9_IN_P8_Msk (0x100UL)
17707 #define PORT9_IN_P9_Pos (9UL)
17708 #define PORT9_IN_P9_Msk (0x200UL)
17709 #define PORT9_IN_P10_Pos (10UL)
17710 #define PORT9_IN_P10_Msk (0x400UL)
17711 #define PORT9_IN_P11_Pos (11UL)
17712 #define PORT9_IN_P11_Msk (0x800UL)
17713 #define PORT9_IN_P12_Pos (12UL)
17714 #define PORT9_IN_P12_Msk (0x1000UL)
17715 #define PORT9_IN_P13_Pos (13UL)
17716 #define PORT9_IN_P13_Msk (0x2000UL)
17717 #define PORT9_IN_P14_Pos (14UL)
17718 #define PORT9_IN_P14_Msk (0x4000UL)
17719 #define PORT9_IN_P15_Pos (15UL)
17720 #define PORT9_IN_P15_Msk (0x8000UL)
17722 /* --------------------------------- PORT9_PDR0 --------------------------------- */
17723 #define PORT9_PDR0_PD0_Pos (0UL)
17724 #define PORT9_PDR0_PD0_Msk (0x7UL)
17725 #define PORT9_PDR0_PD1_Pos (4UL)
17726 #define PORT9_PDR0_PD1_Msk (0x70UL)
17727 #define PORT9_PDR0_PD2_Pos (8UL)
17728 #define PORT9_PDR0_PD2_Msk (0x700UL)
17729 #define PORT9_PDR0_PD3_Pos (12UL)
17730 #define PORT9_PDR0_PD3_Msk (0x7000UL)
17731 #define PORT9_PDR0_PD4_Pos (16UL)
17732 #define PORT9_PDR0_PD4_Msk (0x70000UL)
17733 #define PORT9_PDR0_PD5_Pos (20UL)
17734 #define PORT9_PDR0_PD5_Msk (0x700000UL)
17735 #define PORT9_PDR0_PD6_Pos (24UL)
17736 #define PORT9_PDR0_PD6_Msk (0x7000000UL)
17737 #define PORT9_PDR0_PD7_Pos (28UL)
17738 #define PORT9_PDR0_PD7_Msk (0x70000000UL)
17740 /* --------------------------------- PORT9_PDR1 --------------------------------- */
17741 #define PORT9_PDR1_PD8_Pos (0UL)
17742 #define PORT9_PDR1_PD8_Msk (0x7UL)
17743 #define PORT9_PDR1_PD9_Pos (4UL)
17744 #define PORT9_PDR1_PD9_Msk (0x70UL)
17745 #define PORT9_PDR1_PD10_Pos (8UL)
17746 #define PORT9_PDR1_PD10_Msk (0x700UL)
17747 #define PORT9_PDR1_PD11_Pos (12UL)
17748 #define PORT9_PDR1_PD11_Msk (0x7000UL)
17749 #define PORT9_PDR1_PD12_Pos (16UL)
17750 #define PORT9_PDR1_PD12_Msk (0x70000UL)
17751 #define PORT9_PDR1_PD13_Pos (20UL)
17752 #define PORT9_PDR1_PD13_Msk (0x700000UL)
17753 #define PORT9_PDR1_PD14_Pos (24UL)
17754 #define PORT9_PDR1_PD14_Msk (0x7000000UL)
17755 #define PORT9_PDR1_PD15_Pos (28UL)
17756 #define PORT9_PDR1_PD15_Msk (0x70000000UL)
17758 /* --------------------------------- PORT9_PDISC -------------------------------- */
17759 #define PORT9_PDISC_PDIS0_Pos (0UL)
17760 #define PORT9_PDISC_PDIS0_Msk (0x1UL)
17761 #define PORT9_PDISC_PDIS1_Pos (1UL)
17762 #define PORT9_PDISC_PDIS1_Msk (0x2UL)
17763 #define PORT9_PDISC_PDIS2_Pos (2UL)
17764 #define PORT9_PDISC_PDIS2_Msk (0x4UL)
17765 #define PORT9_PDISC_PDIS3_Pos (3UL)
17766 #define PORT9_PDISC_PDIS3_Msk (0x8UL)
17767 #define PORT9_PDISC_PDIS4_Pos (4UL)
17768 #define PORT9_PDISC_PDIS4_Msk (0x10UL)
17769 #define PORT9_PDISC_PDIS5_Pos (5UL)
17770 #define PORT9_PDISC_PDIS5_Msk (0x20UL)
17771 #define PORT9_PDISC_PDIS6_Pos (6UL)
17772 #define PORT9_PDISC_PDIS6_Msk (0x40UL)
17773 #define PORT9_PDISC_PDIS7_Pos (7UL)
17774 #define PORT9_PDISC_PDIS7_Msk (0x80UL)
17775 #define PORT9_PDISC_PDIS8_Pos (8UL)
17776 #define PORT9_PDISC_PDIS8_Msk (0x100UL)
17777 #define PORT9_PDISC_PDIS9_Pos (9UL)
17778 #define PORT9_PDISC_PDIS9_Msk (0x200UL)
17779 #define PORT9_PDISC_PDIS10_Pos (10UL)
17780 #define PORT9_PDISC_PDIS10_Msk (0x400UL)
17781 #define PORT9_PDISC_PDIS11_Pos (11UL)
17782 #define PORT9_PDISC_PDIS11_Msk (0x800UL)
17783 #define PORT9_PDISC_PDIS12_Pos (12UL)
17784 #define PORT9_PDISC_PDIS12_Msk (0x1000UL)
17785 #define PORT9_PDISC_PDIS13_Pos (13UL)
17786 #define PORT9_PDISC_PDIS13_Msk (0x2000UL)
17787 #define PORT9_PDISC_PDIS14_Pos (14UL)
17788 #define PORT9_PDISC_PDIS14_Msk (0x4000UL)
17789 #define PORT9_PDISC_PDIS15_Pos (15UL)
17790 #define PORT9_PDISC_PDIS15_Msk (0x8000UL)
17792 /* ---------------------------------- PORT9_PPS --------------------------------- */
17793 #define PORT9_PPS_PPS0_Pos (0UL)
17794 #define PORT9_PPS_PPS0_Msk (0x1UL)
17795 #define PORT9_PPS_PPS1_Pos (1UL)
17796 #define PORT9_PPS_PPS1_Msk (0x2UL)
17797 #define PORT9_PPS_PPS2_Pos (2UL)
17798 #define PORT9_PPS_PPS2_Msk (0x4UL)
17799 #define PORT9_PPS_PPS3_Pos (3UL)
17800 #define PORT9_PPS_PPS3_Msk (0x8UL)
17801 #define PORT9_PPS_PPS4_Pos (4UL)
17802 #define PORT9_PPS_PPS4_Msk (0x10UL)
17803 #define PORT9_PPS_PPS5_Pos (5UL)
17804 #define PORT9_PPS_PPS5_Msk (0x20UL)
17805 #define PORT9_PPS_PPS6_Pos (6UL)
17806 #define PORT9_PPS_PPS6_Msk (0x40UL)
17807 #define PORT9_PPS_PPS7_Pos (7UL)
17808 #define PORT9_PPS_PPS7_Msk (0x80UL)
17809 #define PORT9_PPS_PPS8_Pos (8UL)
17810 #define PORT9_PPS_PPS8_Msk (0x100UL)
17811 #define PORT9_PPS_PPS9_Pos (9UL)
17812 #define PORT9_PPS_PPS9_Msk (0x200UL)
17813 #define PORT9_PPS_PPS10_Pos (10UL)
17814 #define PORT9_PPS_PPS10_Msk (0x400UL)
17815 #define PORT9_PPS_PPS11_Pos (11UL)
17816 #define PORT9_PPS_PPS11_Msk (0x800UL)
17817 #define PORT9_PPS_PPS12_Pos (12UL)
17818 #define PORT9_PPS_PPS12_Msk (0x1000UL)
17819 #define PORT9_PPS_PPS13_Pos (13UL)
17820 #define PORT9_PPS_PPS13_Msk (0x2000UL)
17821 #define PORT9_PPS_PPS14_Pos (14UL)
17822 #define PORT9_PPS_PPS14_Msk (0x4000UL)
17823 #define PORT9_PPS_PPS15_Pos (15UL)
17824 #define PORT9_PPS_PPS15_Msk (0x8000UL)
17826 /* --------------------------------- PORT9_HWSEL -------------------------------- */
17827 #define PORT9_HWSEL_HW0_Pos (0UL)
17828 #define PORT9_HWSEL_HW0_Msk (0x3UL)
17829 #define PORT9_HWSEL_HW1_Pos (2UL)
17830 #define PORT9_HWSEL_HW1_Msk (0xcUL)
17831 #define PORT9_HWSEL_HW2_Pos (4UL)
17832 #define PORT9_HWSEL_HW2_Msk (0x30UL)
17833 #define PORT9_HWSEL_HW3_Pos (6UL)
17834 #define PORT9_HWSEL_HW3_Msk (0xc0UL)
17835 #define PORT9_HWSEL_HW4_Pos (8UL)
17836 #define PORT9_HWSEL_HW4_Msk (0x300UL)
17837 #define PORT9_HWSEL_HW5_Pos (10UL)
17838 #define PORT9_HWSEL_HW5_Msk (0xc00UL)
17839 #define PORT9_HWSEL_HW6_Pos (12UL)
17840 #define PORT9_HWSEL_HW6_Msk (0x3000UL)
17841 #define PORT9_HWSEL_HW7_Pos (14UL)
17842 #define PORT9_HWSEL_HW7_Msk (0xc000UL)
17843 #define PORT9_HWSEL_HW8_Pos (16UL)
17844 #define PORT9_HWSEL_HW8_Msk (0x30000UL)
17845 #define PORT9_HWSEL_HW9_Pos (18UL)
17846 #define PORT9_HWSEL_HW9_Msk (0xc0000UL)
17847 #define PORT9_HWSEL_HW10_Pos (20UL)
17848 #define PORT9_HWSEL_HW10_Msk (0x300000UL)
17849 #define PORT9_HWSEL_HW11_Pos (22UL)
17850 #define PORT9_HWSEL_HW11_Msk (0xc00000UL)
17851 #define PORT9_HWSEL_HW12_Pos (24UL)
17852 #define PORT9_HWSEL_HW12_Msk (0x3000000UL)
17853 #define PORT9_HWSEL_HW13_Pos (26UL)
17854 #define PORT9_HWSEL_HW13_Msk (0xc000000UL)
17855 #define PORT9_HWSEL_HW14_Pos (28UL)
17856 #define PORT9_HWSEL_HW14_Msk (0x30000000UL)
17857 #define PORT9_HWSEL_HW15_Pos (30UL)
17858 #define PORT9_HWSEL_HW15_Msk (0xc0000000UL)
17861 /* ================================================================================ */
17862 /* ================ struct 'PORT14' Position & Mask ================ */
17863 /* ================================================================================ */
17864 
17865 
17866 /* --------------------------------- PORT14_OUT --------------------------------- */
17867 #define PORT14_OUT_P0_Pos (0UL)
17868 #define PORT14_OUT_P0_Msk (0x1UL)
17869 #define PORT14_OUT_P1_Pos (1UL)
17870 #define PORT14_OUT_P1_Msk (0x2UL)
17871 #define PORT14_OUT_P2_Pos (2UL)
17872 #define PORT14_OUT_P2_Msk (0x4UL)
17873 #define PORT14_OUT_P3_Pos (3UL)
17874 #define PORT14_OUT_P3_Msk (0x8UL)
17875 #define PORT14_OUT_P4_Pos (4UL)
17876 #define PORT14_OUT_P4_Msk (0x10UL)
17877 #define PORT14_OUT_P5_Pos (5UL)
17878 #define PORT14_OUT_P5_Msk (0x20UL)
17879 #define PORT14_OUT_P6_Pos (6UL)
17880 #define PORT14_OUT_P6_Msk (0x40UL)
17881 #define PORT14_OUT_P7_Pos (7UL)
17882 #define PORT14_OUT_P7_Msk (0x80UL)
17883 #define PORT14_OUT_P8_Pos (8UL)
17884 #define PORT14_OUT_P8_Msk (0x100UL)
17885 #define PORT14_OUT_P9_Pos (9UL)
17886 #define PORT14_OUT_P9_Msk (0x200UL)
17887 #define PORT14_OUT_P10_Pos (10UL)
17888 #define PORT14_OUT_P10_Msk (0x400UL)
17889 #define PORT14_OUT_P11_Pos (11UL)
17890 #define PORT14_OUT_P11_Msk (0x800UL)
17891 #define PORT14_OUT_P12_Pos (12UL)
17892 #define PORT14_OUT_P12_Msk (0x1000UL)
17893 #define PORT14_OUT_P13_Pos (13UL)
17894 #define PORT14_OUT_P13_Msk (0x2000UL)
17895 #define PORT14_OUT_P14_Pos (14UL)
17896 #define PORT14_OUT_P14_Msk (0x4000UL)
17897 #define PORT14_OUT_P15_Pos (15UL)
17898 #define PORT14_OUT_P15_Msk (0x8000UL)
17900 /* --------------------------------- PORT14_OMR --------------------------------- */
17901 #define PORT14_OMR_PS0_Pos (0UL)
17902 #define PORT14_OMR_PS0_Msk (0x1UL)
17903 #define PORT14_OMR_PS1_Pos (1UL)
17904 #define PORT14_OMR_PS1_Msk (0x2UL)
17905 #define PORT14_OMR_PS2_Pos (2UL)
17906 #define PORT14_OMR_PS2_Msk (0x4UL)
17907 #define PORT14_OMR_PS3_Pos (3UL)
17908 #define PORT14_OMR_PS3_Msk (0x8UL)
17909 #define PORT14_OMR_PS4_Pos (4UL)
17910 #define PORT14_OMR_PS4_Msk (0x10UL)
17911 #define PORT14_OMR_PS5_Pos (5UL)
17912 #define PORT14_OMR_PS5_Msk (0x20UL)
17913 #define PORT14_OMR_PS6_Pos (6UL)
17914 #define PORT14_OMR_PS6_Msk (0x40UL)
17915 #define PORT14_OMR_PS7_Pos (7UL)
17916 #define PORT14_OMR_PS7_Msk (0x80UL)
17917 #define PORT14_OMR_PS8_Pos (8UL)
17918 #define PORT14_OMR_PS8_Msk (0x100UL)
17919 #define PORT14_OMR_PS9_Pos (9UL)
17920 #define PORT14_OMR_PS9_Msk (0x200UL)
17921 #define PORT14_OMR_PS10_Pos (10UL)
17922 #define PORT14_OMR_PS10_Msk (0x400UL)
17923 #define PORT14_OMR_PS11_Pos (11UL)
17924 #define PORT14_OMR_PS11_Msk (0x800UL)
17925 #define PORT14_OMR_PS12_Pos (12UL)
17926 #define PORT14_OMR_PS12_Msk (0x1000UL)
17927 #define PORT14_OMR_PS13_Pos (13UL)
17928 #define PORT14_OMR_PS13_Msk (0x2000UL)
17929 #define PORT14_OMR_PS14_Pos (14UL)
17930 #define PORT14_OMR_PS14_Msk (0x4000UL)
17931 #define PORT14_OMR_PS15_Pos (15UL)
17932 #define PORT14_OMR_PS15_Msk (0x8000UL)
17933 #define PORT14_OMR_PR0_Pos (16UL)
17934 #define PORT14_OMR_PR0_Msk (0x10000UL)
17935 #define PORT14_OMR_PR1_Pos (17UL)
17936 #define PORT14_OMR_PR1_Msk (0x20000UL)
17937 #define PORT14_OMR_PR2_Pos (18UL)
17938 #define PORT14_OMR_PR2_Msk (0x40000UL)
17939 #define PORT14_OMR_PR3_Pos (19UL)
17940 #define PORT14_OMR_PR3_Msk (0x80000UL)
17941 #define PORT14_OMR_PR4_Pos (20UL)
17942 #define PORT14_OMR_PR4_Msk (0x100000UL)
17943 #define PORT14_OMR_PR5_Pos (21UL)
17944 #define PORT14_OMR_PR5_Msk (0x200000UL)
17945 #define PORT14_OMR_PR6_Pos (22UL)
17946 #define PORT14_OMR_PR6_Msk (0x400000UL)
17947 #define PORT14_OMR_PR7_Pos (23UL)
17948 #define PORT14_OMR_PR7_Msk (0x800000UL)
17949 #define PORT14_OMR_PR8_Pos (24UL)
17950 #define PORT14_OMR_PR8_Msk (0x1000000UL)
17951 #define PORT14_OMR_PR9_Pos (25UL)
17952 #define PORT14_OMR_PR9_Msk (0x2000000UL)
17953 #define PORT14_OMR_PR10_Pos (26UL)
17954 #define PORT14_OMR_PR10_Msk (0x4000000UL)
17955 #define PORT14_OMR_PR11_Pos (27UL)
17956 #define PORT14_OMR_PR11_Msk (0x8000000UL)
17957 #define PORT14_OMR_PR12_Pos (28UL)
17958 #define PORT14_OMR_PR12_Msk (0x10000000UL)
17959 #define PORT14_OMR_PR13_Pos (29UL)
17960 #define PORT14_OMR_PR13_Msk (0x20000000UL)
17961 #define PORT14_OMR_PR14_Pos (30UL)
17962 #define PORT14_OMR_PR14_Msk (0x40000000UL)
17963 #define PORT14_OMR_PR15_Pos (31UL)
17964 #define PORT14_OMR_PR15_Msk (0x80000000UL)
17966 /* -------------------------------- PORT14_IOCR0 -------------------------------- */
17967 #define PORT14_IOCR0_PC0_Pos (3UL)
17968 #define PORT14_IOCR0_PC0_Msk (0xf8UL)
17969 #define PORT14_IOCR0_PC1_Pos (11UL)
17970 #define PORT14_IOCR0_PC1_Msk (0xf800UL)
17971 #define PORT14_IOCR0_PC2_Pos (19UL)
17972 #define PORT14_IOCR0_PC2_Msk (0xf80000UL)
17973 #define PORT14_IOCR0_PC3_Pos (27UL)
17974 #define PORT14_IOCR0_PC3_Msk (0xf8000000UL)
17976 /* -------------------------------- PORT14_IOCR4 -------------------------------- */
17977 #define PORT14_IOCR4_PC4_Pos (3UL)
17978 #define PORT14_IOCR4_PC4_Msk (0xf8UL)
17979 #define PORT14_IOCR4_PC5_Pos (11UL)
17980 #define PORT14_IOCR4_PC5_Msk (0xf800UL)
17981 #define PORT14_IOCR4_PC6_Pos (19UL)
17982 #define PORT14_IOCR4_PC6_Msk (0xf80000UL)
17983 #define PORT14_IOCR4_PC7_Pos (27UL)
17984 #define PORT14_IOCR4_PC7_Msk (0xf8000000UL)
17986 /* -------------------------------- PORT14_IOCR8 -------------------------------- */
17987 #define PORT14_IOCR8_PC8_Pos (3UL)
17988 #define PORT14_IOCR8_PC8_Msk (0xf8UL)
17989 #define PORT14_IOCR8_PC9_Pos (11UL)
17990 #define PORT14_IOCR8_PC9_Msk (0xf800UL)
17991 #define PORT14_IOCR8_PC10_Pos (19UL)
17992 #define PORT14_IOCR8_PC10_Msk (0xf80000UL)
17993 #define PORT14_IOCR8_PC11_Pos (27UL)
17994 #define PORT14_IOCR8_PC11_Msk (0xf8000000UL)
17996 /* -------------------------------- PORT14_IOCR12 ------------------------------- */
17997 #define PORT14_IOCR12_PC12_Pos (3UL)
17998 #define PORT14_IOCR12_PC12_Msk (0xf8UL)
17999 #define PORT14_IOCR12_PC13_Pos (11UL)
18000 #define PORT14_IOCR12_PC13_Msk (0xf800UL)
18001 #define PORT14_IOCR12_PC14_Pos (19UL)
18002 #define PORT14_IOCR12_PC14_Msk (0xf80000UL)
18003 #define PORT14_IOCR12_PC15_Pos (27UL)
18004 #define PORT14_IOCR12_PC15_Msk (0xf8000000UL)
18006 /* ---------------------------------- PORT14_IN --------------------------------- */
18007 #define PORT14_IN_P0_Pos (0UL)
18008 #define PORT14_IN_P0_Msk (0x1UL)
18009 #define PORT14_IN_P1_Pos (1UL)
18010 #define PORT14_IN_P1_Msk (0x2UL)
18011 #define PORT14_IN_P2_Pos (2UL)
18012 #define PORT14_IN_P2_Msk (0x4UL)
18013 #define PORT14_IN_P3_Pos (3UL)
18014 #define PORT14_IN_P3_Msk (0x8UL)
18015 #define PORT14_IN_P4_Pos (4UL)
18016 #define PORT14_IN_P4_Msk (0x10UL)
18017 #define PORT14_IN_P5_Pos (5UL)
18018 #define PORT14_IN_P5_Msk (0x20UL)
18019 #define PORT14_IN_P6_Pos (6UL)
18020 #define PORT14_IN_P6_Msk (0x40UL)
18021 #define PORT14_IN_P7_Pos (7UL)
18022 #define PORT14_IN_P7_Msk (0x80UL)
18023 #define PORT14_IN_P8_Pos (8UL)
18024 #define PORT14_IN_P8_Msk (0x100UL)
18025 #define PORT14_IN_P9_Pos (9UL)
18026 #define PORT14_IN_P9_Msk (0x200UL)
18027 #define PORT14_IN_P10_Pos (10UL)
18028 #define PORT14_IN_P10_Msk (0x400UL)
18029 #define PORT14_IN_P11_Pos (11UL)
18030 #define PORT14_IN_P11_Msk (0x800UL)
18031 #define PORT14_IN_P12_Pos (12UL)
18032 #define PORT14_IN_P12_Msk (0x1000UL)
18033 #define PORT14_IN_P13_Pos (13UL)
18034 #define PORT14_IN_P13_Msk (0x2000UL)
18035 #define PORT14_IN_P14_Pos (14UL)
18036 #define PORT14_IN_P14_Msk (0x4000UL)
18037 #define PORT14_IN_P15_Pos (15UL)
18038 #define PORT14_IN_P15_Msk (0x8000UL)
18040 /* -------------------------------- PORT14_PDISC -------------------------------- */
18041 #define PORT14_PDISC_PDIS0_Pos (0UL)
18042 #define PORT14_PDISC_PDIS0_Msk (0x1UL)
18043 #define PORT14_PDISC_PDIS1_Pos (1UL)
18044 #define PORT14_PDISC_PDIS1_Msk (0x2UL)
18045 #define PORT14_PDISC_PDIS2_Pos (2UL)
18046 #define PORT14_PDISC_PDIS2_Msk (0x4UL)
18047 #define PORT14_PDISC_PDIS3_Pos (3UL)
18048 #define PORT14_PDISC_PDIS3_Msk (0x8UL)
18049 #define PORT14_PDISC_PDIS4_Pos (4UL)
18050 #define PORT14_PDISC_PDIS4_Msk (0x10UL)
18051 #define PORT14_PDISC_PDIS5_Pos (5UL)
18052 #define PORT14_PDISC_PDIS5_Msk (0x20UL)
18053 #define PORT14_PDISC_PDIS6_Pos (6UL)
18054 #define PORT14_PDISC_PDIS6_Msk (0x40UL)
18055 #define PORT14_PDISC_PDIS7_Pos (7UL)
18056 #define PORT14_PDISC_PDIS7_Msk (0x80UL)
18057 #define PORT14_PDISC_PDIS8_Pos (8UL)
18058 #define PORT14_PDISC_PDIS8_Msk (0x100UL)
18059 #define PORT14_PDISC_PDIS9_Pos (9UL)
18060 #define PORT14_PDISC_PDIS9_Msk (0x200UL)
18061 #define PORT14_PDISC_PDIS12_Pos (12UL)
18062 #define PORT14_PDISC_PDIS12_Msk (0x1000UL)
18063 #define PORT14_PDISC_PDIS13_Pos (13UL)
18064 #define PORT14_PDISC_PDIS13_Msk (0x2000UL)
18065 #define PORT14_PDISC_PDIS14_Pos (14UL)
18066 #define PORT14_PDISC_PDIS14_Msk (0x4000UL)
18067 #define PORT14_PDISC_PDIS15_Pos (15UL)
18068 #define PORT14_PDISC_PDIS15_Msk (0x8000UL)
18070 /* --------------------------------- PORT14_PPS --------------------------------- */
18071 #define PORT14_PPS_PPS0_Pos (0UL)
18072 #define PORT14_PPS_PPS0_Msk (0x1UL)
18073 #define PORT14_PPS_PPS1_Pos (1UL)
18074 #define PORT14_PPS_PPS1_Msk (0x2UL)
18075 #define PORT14_PPS_PPS2_Pos (2UL)
18076 #define PORT14_PPS_PPS2_Msk (0x4UL)
18077 #define PORT14_PPS_PPS3_Pos (3UL)
18078 #define PORT14_PPS_PPS3_Msk (0x8UL)
18079 #define PORT14_PPS_PPS4_Pos (4UL)
18080 #define PORT14_PPS_PPS4_Msk (0x10UL)
18081 #define PORT14_PPS_PPS5_Pos (5UL)
18082 #define PORT14_PPS_PPS5_Msk (0x20UL)
18083 #define PORT14_PPS_PPS6_Pos (6UL)
18084 #define PORT14_PPS_PPS6_Msk (0x40UL)
18085 #define PORT14_PPS_PPS7_Pos (7UL)
18086 #define PORT14_PPS_PPS7_Msk (0x80UL)
18087 #define PORT14_PPS_PPS8_Pos (8UL)
18088 #define PORT14_PPS_PPS8_Msk (0x100UL)
18089 #define PORT14_PPS_PPS9_Pos (9UL)
18090 #define PORT14_PPS_PPS9_Msk (0x200UL)
18091 #define PORT14_PPS_PPS10_Pos (10UL)
18092 #define PORT14_PPS_PPS10_Msk (0x400UL)
18093 #define PORT14_PPS_PPS11_Pos (11UL)
18094 #define PORT14_PPS_PPS11_Msk (0x800UL)
18095 #define PORT14_PPS_PPS12_Pos (12UL)
18096 #define PORT14_PPS_PPS12_Msk (0x1000UL)
18097 #define PORT14_PPS_PPS13_Pos (13UL)
18098 #define PORT14_PPS_PPS13_Msk (0x2000UL)
18099 #define PORT14_PPS_PPS14_Pos (14UL)
18100 #define PORT14_PPS_PPS14_Msk (0x4000UL)
18101 #define PORT14_PPS_PPS15_Pos (15UL)
18102 #define PORT14_PPS_PPS15_Msk (0x8000UL)
18104 /* -------------------------------- PORT14_HWSEL -------------------------------- */
18105 #define PORT14_HWSEL_HW0_Pos (0UL)
18106 #define PORT14_HWSEL_HW0_Msk (0x3UL)
18107 #define PORT14_HWSEL_HW1_Pos (2UL)
18108 #define PORT14_HWSEL_HW1_Msk (0xcUL)
18109 #define PORT14_HWSEL_HW2_Pos (4UL)
18110 #define PORT14_HWSEL_HW2_Msk (0x30UL)
18111 #define PORT14_HWSEL_HW3_Pos (6UL)
18112 #define PORT14_HWSEL_HW3_Msk (0xc0UL)
18113 #define PORT14_HWSEL_HW4_Pos (8UL)
18114 #define PORT14_HWSEL_HW4_Msk (0x300UL)
18115 #define PORT14_HWSEL_HW5_Pos (10UL)
18116 #define PORT14_HWSEL_HW5_Msk (0xc00UL)
18117 #define PORT14_HWSEL_HW6_Pos (12UL)
18118 #define PORT14_HWSEL_HW6_Msk (0x3000UL)
18119 #define PORT14_HWSEL_HW7_Pos (14UL)
18120 #define PORT14_HWSEL_HW7_Msk (0xc000UL)
18121 #define PORT14_HWSEL_HW8_Pos (16UL)
18122 #define PORT14_HWSEL_HW8_Msk (0x30000UL)
18123 #define PORT14_HWSEL_HW9_Pos (18UL)
18124 #define PORT14_HWSEL_HW9_Msk (0xc0000UL)
18125 #define PORT14_HWSEL_HW10_Pos (20UL)
18126 #define PORT14_HWSEL_HW10_Msk (0x300000UL)
18127 #define PORT14_HWSEL_HW11_Pos (22UL)
18128 #define PORT14_HWSEL_HW11_Msk (0xc00000UL)
18129 #define PORT14_HWSEL_HW12_Pos (24UL)
18130 #define PORT14_HWSEL_HW12_Msk (0x3000000UL)
18131 #define PORT14_HWSEL_HW13_Pos (26UL)
18132 #define PORT14_HWSEL_HW13_Msk (0xc000000UL)
18133 #define PORT14_HWSEL_HW14_Pos (28UL)
18134 #define PORT14_HWSEL_HW14_Msk (0x30000000UL)
18135 #define PORT14_HWSEL_HW15_Pos (30UL)
18136 #define PORT14_HWSEL_HW15_Msk (0xc0000000UL)
18139 /* ================================================================================ */
18140 /* ================ struct 'PORT15' Position & Mask ================ */
18141 /* ================================================================================ */
18142 
18143 
18144 /* --------------------------------- PORT15_OUT --------------------------------- */
18145 #define PORT15_OUT_P0_Pos (0UL)
18146 #define PORT15_OUT_P0_Msk (0x1UL)
18147 #define PORT15_OUT_P1_Pos (1UL)
18148 #define PORT15_OUT_P1_Msk (0x2UL)
18149 #define PORT15_OUT_P2_Pos (2UL)
18150 #define PORT15_OUT_P2_Msk (0x4UL)
18151 #define PORT15_OUT_P3_Pos (3UL)
18152 #define PORT15_OUT_P3_Msk (0x8UL)
18153 #define PORT15_OUT_P4_Pos (4UL)
18154 #define PORT15_OUT_P4_Msk (0x10UL)
18155 #define PORT15_OUT_P5_Pos (5UL)
18156 #define PORT15_OUT_P5_Msk (0x20UL)
18157 #define PORT15_OUT_P6_Pos (6UL)
18158 #define PORT15_OUT_P6_Msk (0x40UL)
18159 #define PORT15_OUT_P7_Pos (7UL)
18160 #define PORT15_OUT_P7_Msk (0x80UL)
18161 #define PORT15_OUT_P8_Pos (8UL)
18162 #define PORT15_OUT_P8_Msk (0x100UL)
18163 #define PORT15_OUT_P9_Pos (9UL)
18164 #define PORT15_OUT_P9_Msk (0x200UL)
18165 #define PORT15_OUT_P10_Pos (10UL)
18166 #define PORT15_OUT_P10_Msk (0x400UL)
18167 #define PORT15_OUT_P11_Pos (11UL)
18168 #define PORT15_OUT_P11_Msk (0x800UL)
18169 #define PORT15_OUT_P12_Pos (12UL)
18170 #define PORT15_OUT_P12_Msk (0x1000UL)
18171 #define PORT15_OUT_P13_Pos (13UL)
18172 #define PORT15_OUT_P13_Msk (0x2000UL)
18173 #define PORT15_OUT_P14_Pos (14UL)
18174 #define PORT15_OUT_P14_Msk (0x4000UL)
18175 #define PORT15_OUT_P15_Pos (15UL)
18176 #define PORT15_OUT_P15_Msk (0x8000UL)
18178 /* --------------------------------- PORT15_OMR --------------------------------- */
18179 #define PORT15_OMR_PS0_Pos (0UL)
18180 #define PORT15_OMR_PS0_Msk (0x1UL)
18181 #define PORT15_OMR_PS1_Pos (1UL)
18182 #define PORT15_OMR_PS1_Msk (0x2UL)
18183 #define PORT15_OMR_PS2_Pos (2UL)
18184 #define PORT15_OMR_PS2_Msk (0x4UL)
18185 #define PORT15_OMR_PS3_Pos (3UL)
18186 #define PORT15_OMR_PS3_Msk (0x8UL)
18187 #define PORT15_OMR_PS4_Pos (4UL)
18188 #define PORT15_OMR_PS4_Msk (0x10UL)
18189 #define PORT15_OMR_PS5_Pos (5UL)
18190 #define PORT15_OMR_PS5_Msk (0x20UL)
18191 #define PORT15_OMR_PS6_Pos (6UL)
18192 #define PORT15_OMR_PS6_Msk (0x40UL)
18193 #define PORT15_OMR_PS7_Pos (7UL)
18194 #define PORT15_OMR_PS7_Msk (0x80UL)
18195 #define PORT15_OMR_PS8_Pos (8UL)
18196 #define PORT15_OMR_PS8_Msk (0x100UL)
18197 #define PORT15_OMR_PS9_Pos (9UL)
18198 #define PORT15_OMR_PS9_Msk (0x200UL)
18199 #define PORT15_OMR_PS10_Pos (10UL)
18200 #define PORT15_OMR_PS10_Msk (0x400UL)
18201 #define PORT15_OMR_PS11_Pos (11UL)
18202 #define PORT15_OMR_PS11_Msk (0x800UL)
18203 #define PORT15_OMR_PS12_Pos (12UL)
18204 #define PORT15_OMR_PS12_Msk (0x1000UL)
18205 #define PORT15_OMR_PS13_Pos (13UL)
18206 #define PORT15_OMR_PS13_Msk (0x2000UL)
18207 #define PORT15_OMR_PS14_Pos (14UL)
18208 #define PORT15_OMR_PS14_Msk (0x4000UL)
18209 #define PORT15_OMR_PS15_Pos (15UL)
18210 #define PORT15_OMR_PS15_Msk (0x8000UL)
18211 #define PORT15_OMR_PR0_Pos (16UL)
18212 #define PORT15_OMR_PR0_Msk (0x10000UL)
18213 #define PORT15_OMR_PR1_Pos (17UL)
18214 #define PORT15_OMR_PR1_Msk (0x20000UL)
18215 #define PORT15_OMR_PR2_Pos (18UL)
18216 #define PORT15_OMR_PR2_Msk (0x40000UL)
18217 #define PORT15_OMR_PR3_Pos (19UL)
18218 #define PORT15_OMR_PR3_Msk (0x80000UL)
18219 #define PORT15_OMR_PR4_Pos (20UL)
18220 #define PORT15_OMR_PR4_Msk (0x100000UL)
18221 #define PORT15_OMR_PR5_Pos (21UL)
18222 #define PORT15_OMR_PR5_Msk (0x200000UL)
18223 #define PORT15_OMR_PR6_Pos (22UL)
18224 #define PORT15_OMR_PR6_Msk (0x400000UL)
18225 #define PORT15_OMR_PR7_Pos (23UL)
18226 #define PORT15_OMR_PR7_Msk (0x800000UL)
18227 #define PORT15_OMR_PR8_Pos (24UL)
18228 #define PORT15_OMR_PR8_Msk (0x1000000UL)
18229 #define PORT15_OMR_PR9_Pos (25UL)
18230 #define PORT15_OMR_PR9_Msk (0x2000000UL)
18231 #define PORT15_OMR_PR10_Pos (26UL)
18232 #define PORT15_OMR_PR10_Msk (0x4000000UL)
18233 #define PORT15_OMR_PR11_Pos (27UL)
18234 #define PORT15_OMR_PR11_Msk (0x8000000UL)
18235 #define PORT15_OMR_PR12_Pos (28UL)
18236 #define PORT15_OMR_PR12_Msk (0x10000000UL)
18237 #define PORT15_OMR_PR13_Pos (29UL)
18238 #define PORT15_OMR_PR13_Msk (0x20000000UL)
18239 #define PORT15_OMR_PR14_Pos (30UL)
18240 #define PORT15_OMR_PR14_Msk (0x40000000UL)
18241 #define PORT15_OMR_PR15_Pos (31UL)
18242 #define PORT15_OMR_PR15_Msk (0x80000000UL)
18244 /* -------------------------------- PORT15_IOCR0 -------------------------------- */
18245 #define PORT15_IOCR0_PC0_Pos (3UL)
18246 #define PORT15_IOCR0_PC0_Msk (0xf8UL)
18247 #define PORT15_IOCR0_PC1_Pos (11UL)
18248 #define PORT15_IOCR0_PC1_Msk (0xf800UL)
18249 #define PORT15_IOCR0_PC2_Pos (19UL)
18250 #define PORT15_IOCR0_PC2_Msk (0xf80000UL)
18251 #define PORT15_IOCR0_PC3_Pos (27UL)
18252 #define PORT15_IOCR0_PC3_Msk (0xf8000000UL)
18254 /* -------------------------------- PORT15_IOCR4 -------------------------------- */
18255 #define PORT15_IOCR4_PC4_Pos (3UL)
18256 #define PORT15_IOCR4_PC4_Msk (0xf8UL)
18257 #define PORT15_IOCR4_PC5_Pos (11UL)
18258 #define PORT15_IOCR4_PC5_Msk (0xf800UL)
18259 #define PORT15_IOCR4_PC6_Pos (19UL)
18260 #define PORT15_IOCR4_PC6_Msk (0xf80000UL)
18261 #define PORT15_IOCR4_PC7_Pos (27UL)
18262 #define PORT15_IOCR4_PC7_Msk (0xf8000000UL)
18264 /* -------------------------------- PORT15_IOCR8 -------------------------------- */
18265 #define PORT15_IOCR8_PC8_Pos (3UL)
18266 #define PORT15_IOCR8_PC8_Msk (0xf8UL)
18267 #define PORT15_IOCR8_PC9_Pos (11UL)
18268 #define PORT15_IOCR8_PC9_Msk (0xf800UL)
18269 #define PORT15_IOCR8_PC10_Pos (19UL)
18270 #define PORT15_IOCR8_PC10_Msk (0xf80000UL)
18271 #define PORT15_IOCR8_PC11_Pos (27UL)
18272 #define PORT15_IOCR8_PC11_Msk (0xf8000000UL)
18274 /* -------------------------------- PORT15_IOCR12 ------------------------------- */
18275 #define PORT15_IOCR12_PC12_Pos (3UL)
18276 #define PORT15_IOCR12_PC12_Msk (0xf8UL)
18277 #define PORT15_IOCR12_PC13_Pos (11UL)
18278 #define PORT15_IOCR12_PC13_Msk (0xf800UL)
18279 #define PORT15_IOCR12_PC14_Pos (19UL)
18280 #define PORT15_IOCR12_PC14_Msk (0xf80000UL)
18281 #define PORT15_IOCR12_PC15_Pos (27UL)
18282 #define PORT15_IOCR12_PC15_Msk (0xf8000000UL)
18284 /* ---------------------------------- PORT15_IN --------------------------------- */
18285 #define PORT15_IN_P0_Pos (0UL)
18286 #define PORT15_IN_P0_Msk (0x1UL)
18287 #define PORT15_IN_P1_Pos (1UL)
18288 #define PORT15_IN_P1_Msk (0x2UL)
18289 #define PORT15_IN_P2_Pos (2UL)
18290 #define PORT15_IN_P2_Msk (0x4UL)
18291 #define PORT15_IN_P3_Pos (3UL)
18292 #define PORT15_IN_P3_Msk (0x8UL)
18293 #define PORT15_IN_P4_Pos (4UL)
18294 #define PORT15_IN_P4_Msk (0x10UL)
18295 #define PORT15_IN_P5_Pos (5UL)
18296 #define PORT15_IN_P5_Msk (0x20UL)
18297 #define PORT15_IN_P6_Pos (6UL)
18298 #define PORT15_IN_P6_Msk (0x40UL)
18299 #define PORT15_IN_P7_Pos (7UL)
18300 #define PORT15_IN_P7_Msk (0x80UL)
18301 #define PORT15_IN_P8_Pos (8UL)
18302 #define PORT15_IN_P8_Msk (0x100UL)
18303 #define PORT15_IN_P9_Pos (9UL)
18304 #define PORT15_IN_P9_Msk (0x200UL)
18305 #define PORT15_IN_P10_Pos (10UL)
18306 #define PORT15_IN_P10_Msk (0x400UL)
18307 #define PORT15_IN_P11_Pos (11UL)
18308 #define PORT15_IN_P11_Msk (0x800UL)
18309 #define PORT15_IN_P12_Pos (12UL)
18310 #define PORT15_IN_P12_Msk (0x1000UL)
18311 #define PORT15_IN_P13_Pos (13UL)
18312 #define PORT15_IN_P13_Msk (0x2000UL)
18313 #define PORT15_IN_P14_Pos (14UL)
18314 #define PORT15_IN_P14_Msk (0x4000UL)
18315 #define PORT15_IN_P15_Pos (15UL)
18316 #define PORT15_IN_P15_Msk (0x8000UL)
18318 /* -------------------------------- PORT15_PDISC -------------------------------- */
18319 #define PORT15_PDISC_PDIS2_Pos (2UL)
18320 #define PORT15_PDISC_PDIS2_Msk (0x4UL)
18321 #define PORT15_PDISC_PDIS3_Pos (3UL)
18322 #define PORT15_PDISC_PDIS3_Msk (0x8UL)
18323 #define PORT15_PDISC_PDIS4_Pos (4UL)
18324 #define PORT15_PDISC_PDIS4_Msk (0x10UL)
18325 #define PORT15_PDISC_PDIS5_Pos (5UL)
18326 #define PORT15_PDISC_PDIS5_Msk (0x20UL)
18327 #define PORT15_PDISC_PDIS6_Pos (6UL)
18328 #define PORT15_PDISC_PDIS6_Msk (0x40UL)
18329 #define PORT15_PDISC_PDIS7_Pos (7UL)
18330 #define PORT15_PDISC_PDIS7_Msk (0x80UL)
18331 #define PORT15_PDISC_PDIS8_Pos (8UL)
18332 #define PORT15_PDISC_PDIS8_Msk (0x100UL)
18333 #define PORT15_PDISC_PDIS9_Pos (9UL)
18334 #define PORT15_PDISC_PDIS9_Msk (0x200UL)
18335 #define PORT15_PDISC_PDIS12_Pos (12UL)
18336 #define PORT15_PDISC_PDIS12_Msk (0x1000UL)
18337 #define PORT15_PDISC_PDIS13_Pos (13UL)
18338 #define PORT15_PDISC_PDIS13_Msk (0x2000UL)
18339 #define PORT15_PDISC_PDIS14_Pos (14UL)
18340 #define PORT15_PDISC_PDIS14_Msk (0x4000UL)
18341 #define PORT15_PDISC_PDIS15_Pos (15UL)
18342 #define PORT15_PDISC_PDIS15_Msk (0x8000UL)
18344 /* --------------------------------- PORT15_PPS --------------------------------- */
18345 #define PORT15_PPS_PPS0_Pos (0UL)
18346 #define PORT15_PPS_PPS0_Msk (0x1UL)
18347 #define PORT15_PPS_PPS1_Pos (1UL)
18348 #define PORT15_PPS_PPS1_Msk (0x2UL)
18349 #define PORT15_PPS_PPS2_Pos (2UL)
18350 #define PORT15_PPS_PPS2_Msk (0x4UL)
18351 #define PORT15_PPS_PPS3_Pos (3UL)
18352 #define PORT15_PPS_PPS3_Msk (0x8UL)
18353 #define PORT15_PPS_PPS4_Pos (4UL)
18354 #define PORT15_PPS_PPS4_Msk (0x10UL)
18355 #define PORT15_PPS_PPS5_Pos (5UL)
18356 #define PORT15_PPS_PPS5_Msk (0x20UL)
18357 #define PORT15_PPS_PPS6_Pos (6UL)
18358 #define PORT15_PPS_PPS6_Msk (0x40UL)
18359 #define PORT15_PPS_PPS7_Pos (7UL)
18360 #define PORT15_PPS_PPS7_Msk (0x80UL)
18361 #define PORT15_PPS_PPS8_Pos (8UL)
18362 #define PORT15_PPS_PPS8_Msk (0x100UL)
18363 #define PORT15_PPS_PPS9_Pos (9UL)
18364 #define PORT15_PPS_PPS9_Msk (0x200UL)
18365 #define PORT15_PPS_PPS10_Pos (10UL)
18366 #define PORT15_PPS_PPS10_Msk (0x400UL)
18367 #define PORT15_PPS_PPS11_Pos (11UL)
18368 #define PORT15_PPS_PPS11_Msk (0x800UL)
18369 #define PORT15_PPS_PPS12_Pos (12UL)
18370 #define PORT15_PPS_PPS12_Msk (0x1000UL)
18371 #define PORT15_PPS_PPS13_Pos (13UL)
18372 #define PORT15_PPS_PPS13_Msk (0x2000UL)
18373 #define PORT15_PPS_PPS14_Pos (14UL)
18374 #define PORT15_PPS_PPS14_Msk (0x4000UL)
18375 #define PORT15_PPS_PPS15_Pos (15UL)
18376 #define PORT15_PPS_PPS15_Msk (0x8000UL)
18378 /* -------------------------------- PORT15_HWSEL -------------------------------- */
18379 #define PORT15_HWSEL_HW0_Pos (0UL)
18380 #define PORT15_HWSEL_HW0_Msk (0x3UL)
18381 #define PORT15_HWSEL_HW1_Pos (2UL)
18382 #define PORT15_HWSEL_HW1_Msk (0xcUL)
18383 #define PORT15_HWSEL_HW2_Pos (4UL)
18384 #define PORT15_HWSEL_HW2_Msk (0x30UL)
18385 #define PORT15_HWSEL_HW3_Pos (6UL)
18386 #define PORT15_HWSEL_HW3_Msk (0xc0UL)
18387 #define PORT15_HWSEL_HW4_Pos (8UL)
18388 #define PORT15_HWSEL_HW4_Msk (0x300UL)
18389 #define PORT15_HWSEL_HW5_Pos (10UL)
18390 #define PORT15_HWSEL_HW5_Msk (0xc00UL)
18391 #define PORT15_HWSEL_HW6_Pos (12UL)
18392 #define PORT15_HWSEL_HW6_Msk (0x3000UL)
18393 #define PORT15_HWSEL_HW7_Pos (14UL)
18394 #define PORT15_HWSEL_HW7_Msk (0xc000UL)
18395 #define PORT15_HWSEL_HW8_Pos (16UL)
18396 #define PORT15_HWSEL_HW8_Msk (0x30000UL)
18397 #define PORT15_HWSEL_HW9_Pos (18UL)
18398 #define PORT15_HWSEL_HW9_Msk (0xc0000UL)
18399 #define PORT15_HWSEL_HW10_Pos (20UL)
18400 #define PORT15_HWSEL_HW10_Msk (0x300000UL)
18401 #define PORT15_HWSEL_HW11_Pos (22UL)
18402 #define PORT15_HWSEL_HW11_Msk (0xc00000UL)
18403 #define PORT15_HWSEL_HW12_Pos (24UL)
18404 #define PORT15_HWSEL_HW12_Msk (0x3000000UL)
18405 #define PORT15_HWSEL_HW13_Pos (26UL)
18406 #define PORT15_HWSEL_HW13_Msk (0xc000000UL)
18407 #define PORT15_HWSEL_HW14_Pos (28UL)
18408 #define PORT15_HWSEL_HW14_Msk (0x30000000UL)
18409 #define PORT15_HWSEL_HW15_Pos (30UL)
18410 #define PORT15_HWSEL_HW15_Msk (0xc0000000UL)
18414 /* ================================================================================ */
18415 /* ================ Peripheral memory map ================ */
18416 /* ================================================================================ */
18417 
18418 #define PPB_BASE 0xE000E000UL
18419 #define DLR_BASE 0x50004900UL
18420 #define ERU0_BASE 0x50004800UL
18421 #define ERU1_BASE 0x40044000UL
18422 #define GPDMA0_BASE 0x500142C0UL
18423 #define GPDMA0_CH0_BASE 0x50014000UL
18424 #define GPDMA0_CH1_BASE 0x50014058UL
18425 #define GPDMA0_CH2_BASE 0x500140B0UL
18426 #define GPDMA0_CH3_BASE 0x50014108UL
18427 #define GPDMA0_CH4_BASE 0x50014160UL
18428 #define GPDMA0_CH5_BASE 0x500141B8UL
18429 #define GPDMA0_CH6_BASE 0x50014210UL
18430 #define GPDMA0_CH7_BASE 0x50014268UL
18431 #define GPDMA1_BASE 0x500182C0UL
18432 #define GPDMA1_CH0_BASE 0x50018000UL
18433 #define GPDMA1_CH1_BASE 0x50018058UL
18434 #define GPDMA1_CH2_BASE 0x500180B0UL
18435 #define GPDMA1_CH3_BASE 0x50018108UL
18436 #define FCE_BASE 0x50020000UL
18437 #define FCE_KE0_BASE 0x50020020UL
18438 #define FCE_KE1_BASE 0x50020040UL
18439 #define FCE_KE2_BASE 0x50020060UL
18440 #define FCE_KE3_BASE 0x50020080UL
18441 #define PBA0_BASE 0x40000000UL
18442 #define PBA1_BASE 0x48000000UL
18443 #define FLASH0_BASE 0x58001000UL
18444 #define PREF_BASE 0x58004000UL
18445 #define PMU0_BASE 0x58000508UL
18446 #define WDT_BASE 0x50008000UL
18447 #define RTC_BASE 0x50004A00UL
18448 #define SCU_CLK_BASE 0x50004600UL
18449 #define SCU_OSC_BASE 0x50004700UL
18450 #define SCU_PLL_BASE 0x50004710UL
18451 #define SCU_GENERAL_BASE 0x50004000UL
18452 #define SCU_INTERRUPT_BASE 0x50004074UL
18453 #define SCU_PARITY_BASE 0x5000413CUL
18454 #define SCU_TRAP_BASE 0x50004160UL
18455 #define SCU_HIBERNATE_BASE 0x50004300UL
18456 #define SCU_POWER_BASE 0x50004200UL
18457 #define SCU_RESET_BASE 0x50004400UL
18458 #define LEDTS0_BASE 0x48010000UL
18459 #define SDMMC_CON_BASE 0x500040B4UL
18460 #define SDMMC_BASE 0x4801C000UL
18461 #define EBU_BASE 0x58008000UL
18462 #define ETH0_CON_BASE 0x50004040UL
18463 #define ETH0_BASE 0x5000C000UL
18464 #define ECAT0_CON_BASE 0x500041B0UL
18465 #define ECAT0_BASE 0x54010000UL
18466 #define ECAT0_FMMU0_BASE 0x54010600UL
18467 #define ECAT0_FMMU1_BASE 0x54010610UL
18468 #define ECAT0_FMMU2_BASE 0x54010620UL
18469 #define ECAT0_FMMU3_BASE 0x54010630UL
18470 #define ECAT0_FMMU4_BASE 0x54010640UL
18471 #define ECAT0_FMMU5_BASE 0x54010650UL
18472 #define ECAT0_FMMU6_BASE 0x54010660UL
18473 #define ECAT0_FMMU7_BASE 0x54010670UL
18474 #define ECAT0_SM0_BASE 0x54010800UL
18475 #define ECAT0_SM1_BASE 0x54010808UL
18476 #define ECAT0_SM2_BASE 0x54010810UL
18477 #define ECAT0_SM3_BASE 0x54010818UL
18478 #define ECAT0_SM4_BASE 0x54010820UL
18479 #define ECAT0_SM5_BASE 0x54010828UL
18480 #define ECAT0_SM6_BASE 0x54010830UL
18481 #define ECAT0_SM7_BASE 0x54010838UL
18482 #define USB0_BASE 0x50040000UL
18483 #define USB_EP_BASE 0x50040900UL
18484 #define USB0_EP1_BASE 0x50040920UL
18485 #define USB0_EP2_BASE 0x50040940UL
18486 #define USB0_EP3_BASE 0x50040960UL
18487 #define USB0_EP4_BASE 0x50040980UL
18488 #define USB0_EP5_BASE 0x500409A0UL
18489 #define USB0_EP6_BASE 0x500409C0UL
18490 #define USB0_CH0_BASE 0x50040500UL
18491 #define USB0_CH1_BASE 0x50040520UL
18492 #define USB0_CH2_BASE 0x50040540UL
18493 #define USB0_CH3_BASE 0x50040560UL
18494 #define USB0_CH4_BASE 0x50040580UL
18495 #define USB0_CH5_BASE 0x500405A0UL
18496 #define USB0_CH6_BASE 0x500405C0UL
18497 #define USB0_CH7_BASE 0x500405E0UL
18498 #define USB0_CH8_BASE 0x50040600UL
18499 #define USB0_CH9_BASE 0x50040620UL
18500 #define USB0_CH10_BASE 0x50040640UL
18501 #define USB0_CH11_BASE 0x50040660UL
18502 #define USB0_CH12_BASE 0x50040680UL
18503 #define USB0_CH13_BASE 0x500406A0UL
18504 #define USIC0_BASE 0x40030008UL
18505 #define USIC1_BASE 0x48020008UL
18506 #define USIC2_BASE 0x48024008UL
18507 #define USIC0_CH0_BASE 0x40030000UL
18508 #define USIC0_CH1_BASE 0x40030200UL
18509 #define USIC1_CH0_BASE 0x48020000UL
18510 #define USIC1_CH1_BASE 0x48020200UL
18511 #define USIC2_CH0_BASE 0x48024000UL
18512 #define USIC2_CH1_BASE 0x48024200UL
18513 #define CAN_BASE 0x48014000UL
18514 #define CAN_NODE0_BASE 0x48014200UL
18515 #define CAN_NODE1_BASE 0x48014300UL
18516 #define CAN_NODE2_BASE 0x48014400UL
18517 #define CAN_NODE3_BASE 0x48014500UL
18518 #define CAN_NODE4_BASE 0x48014600UL
18519 #define CAN_NODE5_BASE 0x48014700UL
18520 #define CAN_MO_BASE 0x48015000UL
18521 #define VADC_BASE 0x40004000UL
18522 #define VADC_G0_BASE 0x40004400UL
18523 #define VADC_G1_BASE 0x40004800UL
18524 #define VADC_G2_BASE 0x40004C00UL
18525 #define VADC_G3_BASE 0x40005000UL
18526 #define DSD_BASE 0x40008000UL
18527 #define DSD_CH0_BASE 0x40008100UL
18528 #define DSD_CH1_BASE 0x40008200UL
18529 #define DSD_CH2_BASE 0x40008300UL
18530 #define DSD_CH3_BASE 0x40008400UL
18531 #define DAC_BASE 0x48018000UL
18532 #define CCU40_BASE 0x4000C000UL
18533 #define CCU41_BASE 0x40010000UL
18534 #define CCU42_BASE 0x40014000UL
18535 #define CCU43_BASE 0x48004000UL
18536 #define CCU40_CC40_BASE 0x4000C100UL
18537 #define CCU40_CC41_BASE 0x4000C200UL
18538 #define CCU40_CC42_BASE 0x4000C300UL
18539 #define CCU40_CC43_BASE 0x4000C400UL
18540 #define CCU41_CC40_BASE 0x40010100UL
18541 #define CCU41_CC41_BASE 0x40010200UL
18542 #define CCU41_CC42_BASE 0x40010300UL
18543 #define CCU41_CC43_BASE 0x40010400UL
18544 #define CCU42_CC40_BASE 0x40014100UL
18545 #define CCU42_CC41_BASE 0x40014200UL
18546 #define CCU42_CC42_BASE 0x40014300UL
18547 #define CCU42_CC43_BASE 0x40014400UL
18548 #define CCU43_CC40_BASE 0x48004100UL
18549 #define CCU43_CC41_BASE 0x48004200UL
18550 #define CCU43_CC42_BASE 0x48004300UL
18551 #define CCU43_CC43_BASE 0x48004400UL
18552 #define CCU80_BASE 0x40020000UL
18553 #define CCU81_BASE 0x40024000UL
18554 #define CCU80_CC80_BASE 0x40020100UL
18555 #define CCU80_CC81_BASE 0x40020200UL
18556 #define CCU80_CC82_BASE 0x40020300UL
18557 #define CCU80_CC83_BASE 0x40020400UL
18558 #define CCU81_CC80_BASE 0x40024100UL
18559 #define CCU81_CC81_BASE 0x40024200UL
18560 #define CCU81_CC82_BASE 0x40024300UL
18561 #define CCU81_CC83_BASE 0x40024400UL
18562 #define POSIF0_BASE 0x40028000UL
18563 #define POSIF1_BASE 0x4002C000UL
18564 #define PORT0_BASE 0x48028000UL
18565 #define PORT1_BASE 0x48028100UL
18566 #define PORT2_BASE 0x48028200UL
18567 #define PORT3_BASE 0x48028300UL
18568 #define PORT4_BASE 0x48028400UL
18569 #define PORT5_BASE 0x48028500UL
18570 #define PORT6_BASE 0x48028600UL
18571 #define PORT7_BASE 0x48028700UL
18572 #define PORT8_BASE 0x48028800UL
18573 #define PORT9_BASE 0x48028900UL
18574 #define PORT14_BASE 0x48028E00UL
18575 #define PORT15_BASE 0x48028F00UL
18576 
18577 
18578 /* ================================================================================ */
18579 /* ================ Peripheral declaration ================ */
18580 /* ================================================================================ */
18581 
18582 #define PPB ((PPB_Type *) PPB_BASE)
18583 #define DLR ((DLR_GLOBAL_TypeDef *) DLR_BASE)
18584 #define ERU0 ((ERU_GLOBAL_TypeDef *) ERU0_BASE)
18585 #define ERU1 ((ERU_GLOBAL_TypeDef *) ERU1_BASE)
18586 #define GPDMA0 ((GPDMA0_GLOBAL_TypeDef *) GPDMA0_BASE)
18587 #define GPDMA0_CH0 ((GPDMA0_CH_TypeDef *) GPDMA0_CH0_BASE)
18588 #define GPDMA0_CH1 ((GPDMA0_CH_TypeDef *) GPDMA0_CH1_BASE)
18589 #define GPDMA0_CH2 ((GPDMA0_CH_TypeDef *) GPDMA0_CH2_BASE)
18590 #define GPDMA0_CH3 ((GPDMA0_CH_TypeDef *) GPDMA0_CH3_BASE)
18591 #define GPDMA0_CH4 ((GPDMA0_CH_TypeDef *) GPDMA0_CH4_BASE)
18592 #define GPDMA0_CH5 ((GPDMA0_CH_TypeDef *) GPDMA0_CH5_BASE)
18593 #define GPDMA0_CH6 ((GPDMA0_CH_TypeDef *) GPDMA0_CH6_BASE)
18594 #define GPDMA0_CH7 ((GPDMA0_CH_TypeDef *) GPDMA0_CH7_BASE)
18595 #define GPDMA1 ((GPDMA1_GLOBAL_TypeDef *) GPDMA1_BASE)
18596 #define GPDMA1_CH0 ((GPDMA1_CH_TypeDef *) GPDMA1_CH0_BASE)
18597 #define GPDMA1_CH1 ((GPDMA1_CH_TypeDef *) GPDMA1_CH1_BASE)
18598 #define GPDMA1_CH2 ((GPDMA1_CH_TypeDef *) GPDMA1_CH2_BASE)
18599 #define GPDMA1_CH3 ((GPDMA1_CH_TypeDef *) GPDMA1_CH3_BASE)
18600 #define FCE ((FCE_GLOBAL_TypeDef *) FCE_BASE)
18601 #define FCE_KE0 ((FCE_KE_TypeDef *) FCE_KE0_BASE)
18602 #define FCE_KE1 ((FCE_KE_TypeDef *) FCE_KE1_BASE)
18603 #define FCE_KE2 ((FCE_KE_TypeDef *) FCE_KE2_BASE)
18604 #define FCE_KE3 ((FCE_KE_TypeDef *) FCE_KE3_BASE)
18605 #define PBA0 ((PBA_GLOBAL_TypeDef *) PBA0_BASE)
18606 #define PBA1 ((PBA_GLOBAL_TypeDef *) PBA1_BASE)
18607 #define FLASH0 ((FLASH0_GLOBAL_TypeDef *) FLASH0_BASE)
18608 #define PREF ((PREF_GLOBAL_TypeDef *) PREF_BASE)
18609 #define PMU0 ((PMU0_GLOBAL_TypeDef *) PMU0_BASE)
18610 #define WDT ((WDT_GLOBAL_TypeDef *) WDT_BASE)
18611 #define RTC ((RTC_GLOBAL_TypeDef *) RTC_BASE)
18612 #define SCU_CLK ((SCU_CLK_TypeDef *) SCU_CLK_BASE)
18613 #define SCU_OSC ((SCU_OSC_TypeDef *) SCU_OSC_BASE)
18614 #define SCU_PLL ((SCU_PLL_TypeDef *) SCU_PLL_BASE)
18615 #define SCU_GENERAL ((SCU_GENERAL_TypeDef *) SCU_GENERAL_BASE)
18616 #define SCU_INTERRUPT ((SCU_INTERRUPT_TypeDef *) SCU_INTERRUPT_BASE)
18617 #define SCU_PARITY ((SCU_PARITY_TypeDef *) SCU_PARITY_BASE)
18618 #define SCU_TRAP ((SCU_TRAP_TypeDef *) SCU_TRAP_BASE)
18619 #define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE)
18620 #define SCU_POWER ((SCU_POWER_TypeDef *) SCU_POWER_BASE)
18621 #define SCU_RESET ((SCU_RESET_TypeDef *) SCU_RESET_BASE)
18622 #define LEDTS0 ((LEDTS0_GLOBAL_TypeDef *) LEDTS0_BASE)
18623 #define SDMMC_CON ((SDMMC_CON_Type *) SDMMC_CON_BASE)
18624 #define SDMMC ((SDMMC_GLOBAL_TypeDef *) SDMMC_BASE)
18625 #define EBU ((EBU_Type *) EBU_BASE)
18626 #define ETH0_CON ((ETH0_CON_GLOBAL_TypeDef *) ETH0_CON_BASE)
18627 #define ETH0 ((ETH_GLOBAL_TypeDef *) ETH0_BASE)
18628 #define ECAT0_CON ((ECAT0_CON_Type *) ECAT0_CON_BASE)
18629 #define ECAT0 ((ECAT_Type *) ECAT0_BASE)
18630 #define ECAT0_FMMU0 ((ECAT0_FMMU_Type *) ECAT0_FMMU0_BASE)
18631 #define ECAT0_FMMU1 ((ECAT0_FMMU_Type *) ECAT0_FMMU1_BASE)
18632 #define ECAT0_FMMU2 ((ECAT0_FMMU_Type *) ECAT0_FMMU2_BASE)
18633 #define ECAT0_FMMU3 ((ECAT0_FMMU_Type *) ECAT0_FMMU3_BASE)
18634 #define ECAT0_FMMU4 ((ECAT0_FMMU_Type *) ECAT0_FMMU4_BASE)
18635 #define ECAT0_FMMU5 ((ECAT0_FMMU_Type *) ECAT0_FMMU5_BASE)
18636 #define ECAT0_FMMU6 ((ECAT0_FMMU_Type *) ECAT0_FMMU6_BASE)
18637 #define ECAT0_FMMU7 ((ECAT0_FMMU_Type *) ECAT0_FMMU7_BASE)
18638 #define ECAT0_SM0 ((ECAT0_SM_Type *) ECAT0_SM0_BASE)
18639 #define ECAT0_SM1 ((ECAT0_SM_Type *) ECAT0_SM1_BASE)
18640 #define ECAT0_SM2 ((ECAT0_SM_Type *) ECAT0_SM2_BASE)
18641 #define ECAT0_SM3 ((ECAT0_SM_Type *) ECAT0_SM3_BASE)
18642 #define ECAT0_SM4 ((ECAT0_SM_Type *) ECAT0_SM4_BASE)
18643 #define ECAT0_SM5 ((ECAT0_SM_Type *) ECAT0_SM5_BASE)
18644 #define ECAT0_SM6 ((ECAT0_SM_Type *) ECAT0_SM6_BASE)
18645 #define ECAT0_SM7 ((ECAT0_SM_Type *) ECAT0_SM7_BASE)
18646 #define USB0 ((USB0_GLOBAL_TypeDef *) USB0_BASE)
18647 #define USB0_EP0 ((USB0_EP0_TypeDef *) USB_EP_BASE)
18648 #define USB0_EP1 ((USB0_EP_TypeDef *) USB0_EP1_BASE)
18649 #define USB0_EP2 ((USB0_EP_TypeDef *) USB0_EP2_BASE)
18650 #define USB0_EP3 ((USB0_EP_TypeDef *) USB0_EP3_BASE)
18651 #define USB0_EP4 ((USB0_EP_TypeDef *) USB0_EP4_BASE)
18652 #define USB0_EP5 ((USB0_EP_TypeDef *) USB0_EP5_BASE)
18653 #define USB0_EP6 ((USB0_EP_TypeDef *) USB0_EP6_BASE)
18654 #define USB0_CH0 ((USB0_CH_TypeDef *) USB0_CH0_BASE)
18655 #define USB0_CH1 ((USB0_CH_TypeDef *) USB0_CH1_BASE)
18656 #define USB0_CH2 ((USB0_CH_TypeDef *) USB0_CH2_BASE)
18657 #define USB0_CH3 ((USB0_CH_TypeDef *) USB0_CH3_BASE)
18658 #define USB0_CH4 ((USB0_CH_TypeDef *) USB0_CH4_BASE)
18659 #define USB0_CH5 ((USB0_CH_TypeDef *) USB0_CH5_BASE)
18660 #define USB0_CH6 ((USB0_CH_TypeDef *) USB0_CH6_BASE)
18661 #define USB0_CH7 ((USB0_CH_TypeDef *) USB0_CH7_BASE)
18662 #define USB0_CH8 ((USB0_CH_TypeDef *) USB0_CH8_BASE)
18663 #define USB0_CH9 ((USB0_CH_TypeDef *) USB0_CH9_BASE)
18664 #define USB0_CH10 ((USB0_CH_TypeDef *) USB0_CH10_BASE)
18665 #define USB0_CH11 ((USB0_CH_TypeDef *) USB0_CH11_BASE)
18666 #define USB0_CH12 ((USB0_CH_TypeDef *) USB0_CH12_BASE)
18667 #define USB0_CH13 ((USB0_CH_TypeDef *) USB0_CH13_BASE)
18668 #define USIC0 ((USIC_GLOBAL_TypeDef *) USIC0_BASE)
18669 #define USIC1 ((USIC_GLOBAL_TypeDef *) USIC1_BASE)
18670 #define USIC2 ((USIC_GLOBAL_TypeDef *) USIC2_BASE)
18671 #define USIC0_CH0 ((USIC_CH_TypeDef *) USIC0_CH0_BASE)
18672 #define USIC0_CH1 ((USIC_CH_TypeDef *) USIC0_CH1_BASE)
18673 #define USIC1_CH0 ((USIC_CH_TypeDef *) USIC1_CH0_BASE)
18674 #define USIC1_CH1 ((USIC_CH_TypeDef *) USIC1_CH1_BASE)
18675 #define USIC2_CH0 ((USIC_CH_TypeDef *) USIC2_CH0_BASE)
18676 #define USIC2_CH1 ((USIC_CH_TypeDef *) USIC2_CH1_BASE)
18677 #define CAN ((CAN_GLOBAL_TypeDef *) CAN_BASE)
18678 #define CAN_NODE0 ((CAN_NODE_TypeDef *) CAN_NODE0_BASE)
18679 #define CAN_NODE1 ((CAN_NODE_TypeDef *) CAN_NODE1_BASE)
18680 #define CAN_NODE2 ((CAN_NODE_TypeDef *) CAN_NODE2_BASE)
18681 #define CAN_NODE3 ((CAN_NODE_TypeDef *) CAN_NODE3_BASE)
18682 #define CAN_NODE4 ((CAN_NODE_TypeDef *) CAN_NODE4_BASE)
18683 #define CAN_NODE5 ((CAN_NODE_TypeDef *) CAN_NODE5_BASE)
18684 #define CAN_MO ((CAN_MO_CLUSTER_Type *) CAN_MO_BASE)
18685 #define VADC ((VADC_GLOBAL_TypeDef *) VADC_BASE)
18686 #define VADC_G0 ((VADC_G_TypeDef *) VADC_G0_BASE)
18687 #define VADC_G1 ((VADC_G_TypeDef *) VADC_G1_BASE)
18688 #define VADC_G2 ((VADC_G_TypeDef *) VADC_G2_BASE)
18689 #define VADC_G3 ((VADC_G_TypeDef *) VADC_G3_BASE)
18690 #define DSD ((DSD_GLOBAL_TypeDef *) DSD_BASE)
18691 #define DSD_CH0 ((DSD_CH_TypeDef *) DSD_CH0_BASE)
18692 #define DSD_CH1 ((DSD_CH_TypeDef *) DSD_CH1_BASE)
18693 #define DSD_CH2 ((DSD_CH_TypeDef *) DSD_CH2_BASE)
18694 #define DSD_CH3 ((DSD_CH_TypeDef *) DSD_CH3_BASE)
18695 #define DAC ((DAC_GLOBAL_TypeDef *) DAC_BASE)
18696 #define CCU40 ((CCU4_GLOBAL_TypeDef *) CCU40_BASE)
18697 #define CCU41 ((CCU4_GLOBAL_TypeDef *) CCU41_BASE)
18698 #define CCU42 ((CCU4_GLOBAL_TypeDef *) CCU42_BASE)
18699 #define CCU43 ((CCU4_GLOBAL_TypeDef *) CCU43_BASE)
18700 #define CCU40_CC40 ((CCU4_CC4_TypeDef *) CCU40_CC40_BASE)
18701 #define CCU40_CC41 ((CCU4_CC4_TypeDef *) CCU40_CC41_BASE)
18702 #define CCU40_CC42 ((CCU4_CC4_TypeDef *) CCU40_CC42_BASE)
18703 #define CCU40_CC43 ((CCU4_CC4_TypeDef *) CCU40_CC43_BASE)
18704 #define CCU41_CC40 ((CCU4_CC4_TypeDef *) CCU41_CC40_BASE)
18705 #define CCU41_CC41 ((CCU4_CC4_TypeDef *) CCU41_CC41_BASE)
18706 #define CCU41_CC42 ((CCU4_CC4_TypeDef *) CCU41_CC42_BASE)
18707 #define CCU41_CC43 ((CCU4_CC4_TypeDef *) CCU41_CC43_BASE)
18708 #define CCU42_CC40 ((CCU4_CC4_TypeDef *) CCU42_CC40_BASE)
18709 #define CCU42_CC41 ((CCU4_CC4_TypeDef *) CCU42_CC41_BASE)
18710 #define CCU42_CC42 ((CCU4_CC4_TypeDef *) CCU42_CC42_BASE)
18711 #define CCU42_CC43 ((CCU4_CC4_TypeDef *) CCU42_CC43_BASE)
18712 #define CCU43_CC40 ((CCU4_CC4_TypeDef *) CCU43_CC40_BASE)
18713 #define CCU43_CC41 ((CCU4_CC4_TypeDef *) CCU43_CC41_BASE)
18714 #define CCU43_CC42 ((CCU4_CC4_TypeDef *) CCU43_CC42_BASE)
18715 #define CCU43_CC43 ((CCU4_CC4_TypeDef *) CCU43_CC43_BASE)
18716 #define CCU80 ((CCU8_GLOBAL_TypeDef *) CCU80_BASE)
18717 #define CCU81 ((CCU8_GLOBAL_TypeDef *) CCU81_BASE)
18718 #define CCU80_CC80 ((CCU8_CC8_TypeDef *) CCU80_CC80_BASE)
18719 #define CCU80_CC81 ((CCU8_CC8_TypeDef *) CCU80_CC81_BASE)
18720 #define CCU80_CC82 ((CCU8_CC8_TypeDef *) CCU80_CC82_BASE)
18721 #define CCU80_CC83 ((CCU8_CC8_TypeDef *) CCU80_CC83_BASE)
18722 #define CCU81_CC80 ((CCU8_CC8_TypeDef *) CCU81_CC80_BASE)
18723 #define CCU81_CC81 ((CCU8_CC8_TypeDef *) CCU81_CC81_BASE)
18724 #define CCU81_CC82 ((CCU8_CC8_TypeDef *) CCU81_CC82_BASE)
18725 #define CCU81_CC83 ((CCU8_CC8_TypeDef *) CCU81_CC83_BASE)
18726 #define POSIF0 ((POSIF_GLOBAL_TypeDef *) POSIF0_BASE)
18727 #define POSIF1 ((POSIF_GLOBAL_TypeDef *) POSIF1_BASE)
18728 #define PORT0 ((PORT0_Type *) PORT0_BASE)
18729 #define PORT1 ((PORT1_Type *) PORT1_BASE)
18730 #define PORT2 ((PORT2_Type *) PORT2_BASE)
18731 #define PORT3 ((PORT3_Type *) PORT3_BASE)
18732 #define PORT4 ((PORT4_Type *) PORT4_BASE)
18733 #define PORT5 ((PORT5_Type *) PORT5_BASE)
18734 #define PORT6 ((PORT6_Type *) PORT6_BASE)
18735 #define PORT7 ((PORT7_Type *) PORT7_BASE)
18736 #define PORT8 ((PORT8_Type *) PORT8_BASE)
18737 #define PORT9 ((PORT9_Type *) PORT9_BASE)
18738 #define PORT14 ((PORT14_Type *) PORT14_BASE)
18739 #define PORT15 ((PORT15_Type *) PORT15_BASE)
18740 
18741  /* End of group Device_Peripheral_Registers */ /* End of group XMC4800 */ /* End of group Infineon */
18745 
18746 #ifdef __cplusplus
18747 }
18748 #endif
18749 
18750 
18751 #endif /* XMC4800_H */
18752 
USB0_GLOBAL_TypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: XMC4800.h:1771
CCU8_CC8_TypeDef::STC
__IO uint32_t STC
Definition: XMC4800.h:2354
PORT1_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2438
ECAT_Type::DC_SYNC1_CYC_TIME
__IO uint32_t DC_SYNC1_CYC_TIME
Definition: XMC4800.h:1627
GPDMA0_CH_TypeDef::CFGL
__IO uint32_t CFGL
Definition: XMC4800.h:638
GPDMA0_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:605
GPDMA0_GLOBAL_TypeDef::STATUSSRCTRAN
__I uint32_t STATUSSRCTRAN
Definition: XMC4800.h:561
PORT3_Type::IOCR12
__IO uint32_t IOCR12
Definition: XMC4800.h:2504
PPB_Type::NVIC_ISPR0
__IO uint32_t NVIC_ISPR0
Definition: XMC4800.h:419
GPDMA1_GLOBAL_TypeDef::RESERVED22
__I uint32_t RESERVED22
Definition: XMC4800.h:723
RTC_GLOBAL_TypeDef::CLRSR
__O uint32_t CLRSR
Definition: XMC4800.h:907
ERU0_0_IRQn
@ ERU0_0_IRQn
Definition: XMC4800.h:80
WDT_GLOBAL_TypeDef::TIM
__I uint32_t TIM
Definition: XMC4800.h:884
PORT4_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2531
CCU8_GLOBAL_TypeDef::GIDLC
__O uint32_t GIDLC
Definition: XMC4800.h:2303
ECAT_Type::ERR_LED
__IO uint8_t ERR_LED
Definition: XMC4800.h:1549
PPB_Type::CPACR
__IO uint32_t CPACR
Definition: XMC4800.h:480
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: XMC4800.h:69
USB0_EP_TypeDef::DTXFSTS
__I uint32_t DTXFSTS
Definition: XMC4800.h:1828
GPDMA1_GLOBAL_TypeDef::RESERVED15
__I uint32_t RESERVED15
Definition: XMC4800.h:709
system_XMC4800.h
USB0_GLOBAL_TypeDef::GNPTXFSIZ_HOSTMODE
__IO uint32_t GNPTXFSIZ_HOSTMODE
Definition: XMC4800.h:1732
CAN_GLOBAL_TypeDef::FDR
__IO uint32_t FDR
Definition: XMC4800.h:1973
VADC_G_TypeDef
Analog to Digital Converter (VADC_G)
Definition: XMC4800.h:2075
CCU8_CC8_TypeDef::TCST
__I uint32_t TCST
Definition: XMC4800.h:2325
POSIF_GLOBAL_TypeDef::MIDR
__I uint32_t MIDR
Definition: XMC4800.h:2376
ETH_GLOBAL_TypeDef::RXIPV4_NO_PAYLOAD_OCTETS
__I uint32_t RXIPV4_NO_PAYLOAD_OCTETS
Definition: XMC4800.h:1435
GPDMA0_GLOBAL_TypeDef::RESERVED17
__I uint32_t RESERVED17
Definition: XMC4800.h:582
VADC_GLOBAL_TypeDef::GLOBRESD
__IO uint32_t GLOBRESD
Definition: XMC4800.h:2060
ETH_GLOBAL_TypeDef::RX_FIFO_OVERFLOW_FRAMES
__I uint32_t RX_FIFO_OVERFLOW_FRAMES
Definition: XMC4800.h:1407
USB0_GLOBAL_TypeDef::GRXSTSR_DEVICEMODE
__I uint32_t GRXSTSR_DEVICEMODE
Definition: XMC4800.h:1720
LEDTS0_GLOBAL_TypeDef::EVFR
__O uint32_t EVFR
Definition: XMC4800.h:1167
CCU8_CC8_TypeDef::INTE
__IO uint32_t INTE
Definition: XMC4800.h:2350
USIC_CH_TypeDef::TRBPTR
__I uint32_t TRBPTR
Definition: XMC4800.h:1950
DLR_GLOBAL_TypeDef::OVRSTAT
__I uint32_t OVRSTAT
Definition: XMC4800.h:512
PORT1_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2448
PPB_Type::STIR
__O uint32_t STIR
Definition: XMC4800.h:494
PPB_Type::NVIC_ICPR3
__IO uint32_t NVIC_ICPR3
Definition: XMC4800.h:427
USB0_GLOBAL_TypeDef::DIEPTXF3
__IO uint32_t DIEPTXF3
Definition: XMC4800.h:1743
PORT2_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2479
ETH_GLOBAL_TypeDef::TX_PAUSE_FRAMES
__I uint32_t TX_PAUSE_FRAMES
Definition: XMC4800.h:1376
GPDMA1_GLOBAL_TypeDef::STATUSTFR
__I uint32_t STATUSTFR
Definition: XMC4800.h:688
ETH_GLOBAL_TypeDef::INTERRUPT_MASK
__IO uint32_t INTERRUPT_MASK
Definition: XMC4800.h:1322
USIC_CH_TypeDef::RBUFSR
__I uint32_t RBUFSR
Definition: XMC4800.h:1937
PPB_Type::SYST_CSR
__IO uint32_t SYST_CSR
Definition: XMC4800.h:404
VADC_G_TypeDef::REVNP1
__IO uint32_t REVNP1
Definition: XMC4800.h:2120
SCU_RESET_TypeDef::PRSTAT0
__I uint32_t PRSTAT0
Definition: XMC4800.h:1139
ECAT_Type::PDI_EXT_CONFIG
__I uint16_t PDI_EXT_CONFIG
Definition: XMC4800.h:1556
SCU_GENERAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:1004
CAN_NODE_TypeDef::NCR
__IO uint32_t NCR
Definition: XMC4800.h:1997
PREF_GLOBAL_TypeDef::PCON
__IO uint32_t PCON
Definition: XMC4800.h:853
ECAT0_SM_Type::SM_CONTROL
__I uint8_t SM_CONTROL
Definition: XMC4800.h:1686
SCU_CLK_TypeDef::ECATCLKCR
__IO uint32_t ECATCLKCR
Definition: XMC4800.h:939
SCU_OSC_TypeDef::OSCHPSTAT
__I uint32_t OSCHPSTAT
Definition: XMC4800.h:966
PPB_Type::VTOR
__IO uint32_t VTOR
Definition: XMC4800.h:465
FCE_KE_TypeDef::IR
__IO uint32_t IR
Definition: XMC4800.h:791
CCU8_CC8_TypeDef::PSC
__IO uint32_t PSC
Definition: XMC4800.h:2332
PPB_Type::RESERVED11
__I uint32_t RESERVED11
Definition: XMC4800.h:481
PORT9_Type
Port 9 (PORT9)
Definition: XMC4800.h:2668
CCU4_CC4_TypeDef::INS
__IO uint32_t INS
Definition: XMC4800.h:2259
POSIF_GLOBAL_TypeDef::HALP
__I uint32_t HALP
Definition: XMC4800.h:2378
SCU_RESET_TypeDef::PRSET2
__O uint32_t PRSET2
Definition: XMC4800.h:1146
PPB_Type::MPU_RNR
__IO uint32_t MPU_RNR
Definition: XMC4800.h:484
CCU8_CC8_TypeDef::CR2
__I uint32_t CR2
Definition: XMC4800.h:2339
PPB_Type::MPU_RBAR_A1
__IO uint32_t MPU_RBAR_A1
Definition: XMC4800.h:487
PORT15_Type::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:2732
GPDMA1_0_IRQn
@ GPDMA1_0_IRQn
Definition: XMC4800.h:180
ETH_GLOBAL_TypeDef::RXUDP_ERROR_FRAMES
__I uint32_t RXUDP_ERROR_FRAMES
Definition: XMC4800.h:1427
DSD_CH_TypeDef::CGSYNC
__IO uint32_t CGSYNC
Definition: XMC4800.h:2196
ETH_GLOBAL_TypeDef::TX_512TO1023OCTETS_FRAMES_GOOD_BAD
__I uint32_t TX_512TO1023OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1350
PORT9_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2672
PPB_Type::NVIC_IPR0
__IO uint32_t NVIC_IPR0
Definition: XMC4800.h:434
ETH_GLOBAL_TypeDef::RXTCP_ERROR_OCTETS
__I uint32_t RXTCP_ERROR_OCTETS
Definition: XMC4800.h:1444
GPDMA0_GLOBAL_TypeDef::STATUSTFR
__I uint32_t STATUSTFR
Definition: XMC4800.h:557
PMU0_0_IRQn
@ PMU0_0_IRQn
Definition: XMC4800.h:88
ETH0_CON_GLOBAL_TypeDef
Ethernet Control Register (ETH0_CON)
Definition: XMC4800.h:1293
GPDMA1_GLOBAL_TypeDef::LSTSRCREG
__IO uint32_t LSTSRCREG
Definition: XMC4800.h:728
USB0_GLOBAL_TypeDef::HAINT
__I uint32_t HAINT
Definition: XMC4800.h:1753
PORT5_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2562
USB0_GLOBAL_TypeDef::DIEPTXF6
__IO uint32_t DIEPTXF6
Definition: XMC4800.h:1746
SCU_PARITY_TypeDef::MCHKCON
__IO uint32_t MCHKCON
Definition: XMC4800.h:1056
DSD_CH_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:2189
CAN_MO_TypeDef::MOFCR
__IO uint32_t MOFCR
Definition: XMC4800.h:376
FLASH0_GLOBAL_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:829
SDMMC_GLOBAL_TypeDef::WAKEUP_CTRL
__IO uint8_t WAKEUP_CTRL
Definition: XMC4800.h:1217
CCU41_1_IRQn
@ CCU41_1_IRQn
Definition: XMC4800.h:124
GPDMA0_GLOBAL_TypeDef::RESERVED27
__I uint32_t RESERVED27
Definition: XMC4800.h:602
EBU_Type::CLC
__IO uint32_t CLC
Definition: XMC4800.h:1252
USIC2_1_IRQn
@ USIC2_1_IRQn
Definition: XMC4800.h:168
__O
#define __O
Definition: core_cm4.h:221
DLR_GLOBAL_TypeDef::LNEN
__IO uint32_t LNEN
Definition: XMC4800.h:516
ETH_GLOBAL_TypeDef::TIMESTAMP_CONTROL
__IO uint32_t TIMESTAMP_CONTROL
Definition: XMC4800.h:1448
ETH_GLOBAL_TypeDef::AHB_STATUS
__I uint32_t AHB_STATUS
Definition: XMC4800.h:1471
CCU8_CC8_TypeDef::FPCS
__IO uint32_t FPCS
Definition: XMC4800.h:2334
ETH_GLOBAL_TypeDef::RXIPV4_FRAGMENTED_FRAMES
__I uint32_t RXIPV4_FRAGMENTED_FRAMES
Definition: XMC4800.h:1420
VADC0_G0_3_IRQn
@ VADC0_G0_3_IRQn
Definition: XMC4800.h:96
PPB_Type::RESERVED9
__I uint32_t RESERVED9
Definition: XMC4800.h:475
USB0_GLOBAL_TypeDef::GINTSTS_DEVICEMODE
__IO uint32_t GINTSTS_DEVICEMODE
Definition: XMC4800.h:1710
PORT6_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2597
USB0_GLOBAL_TypeDef::PCGCCTL
__IO uint32_t PCGCCTL
Definition: XMC4800.h:1774
GPDMA0_CH2_7_Type::CFGL
__IO uint32_t CFGL
Definition: XMC4800.h:663
ECAT_Type::ESC_RESET_PDI_WRITEMode
__I uint8_t ESC_RESET_PDI_WRITEMode
Definition: XMC4800.h:1533
ECAT_Type::WD_COUNT_PDATA
__I uint8_t WD_COUNT_PDATA
Definition: XMC4800.h:1585
USB0_GLOBAL_TypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: XMC4800.h:1752
ETH_GLOBAL_TypeDef::RXTCP_ERROR_FRAMES
__I uint32_t RXTCP_ERROR_FRAMES
Definition: XMC4800.h:1429
SDMMC_GLOBAL_TypeDef::SW_RESET
__IO uint8_t SW_RESET
Definition: XMC4800.h:1220
ECAT0_CON_Type::CON
__IO uint32_t CON
Definition: XMC4800.h:1491
CCU4_CC4_TypeDef
Capture Compare Unit 4 - Unit 0 (CCU4_CC4)
Definition: XMC4800.h:2258
ETH_GLOBAL_TypeDef::SYSTEM_TIME_HIGHER_WORD_SECONDS
__IO uint32_t SYSTEM_TIME_HIGHER_WORD_SECONDS
Definition: XMC4800.h:1457
VADC_G_TypeDef::VFR
__IO uint32_t VFR
Definition: XMC4800.h:2128
PORT7_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2621
VADC_GLOBAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:2032
SDMMC_GLOBAL_TypeDef::DEBUG_SEL
__O uint32_t DEBUG_SEL
Definition: XMC4800.h:1236
PPB_Type::FPDSCR
__IO uint32_t FPDSCR
Definition: XMC4800.h:498
GPDMA1_GLOBAL_TypeDef::RESERVED11
__I uint32_t RESERVED11
Definition: XMC4800.h:701
LEDTS0_GLOBAL_TypeDef::FNCTL
__IO uint32_t FNCTL
Definition: XMC4800.h:1166
ETH_GLOBAL_TypeDef::RXICMP_ERROR_FRAMES
__I uint32_t RXICMP_ERROR_FRAMES
Definition: XMC4800.h:1431
CCU40_2_IRQn
@ CCU40_2_IRQn
Definition: XMC4800.h:121
ETH_GLOBAL_TypeDef::TX_MULTICAST_FRAMES_GOOD_BAD
__I uint32_t TX_MULTICAST_FRAMES_GOOD_BAD
Definition: XMC4800.h:1356
SCU_TRAP_TypeDef
System Control Unit (SCU_TRAP)
Definition: XMC4800.h:1075
SDMMC_GLOBAL_TypeDef::MAX_CURRENT_CAP
__I uint32_t MAX_CURRENT_CAP
Definition: XMC4800.h:1231
PPB_Type::CCR
__IO uint32_t CCR
Definition: XMC4800.h:468
ETH_GLOBAL_TypeDef::VERSION
__I uint32_t VERSION
Definition: XMC4800.h:1316
VADC_G_TypeDef::QSR0
__I uint32_t QSR0
Definition: XMC4800.h:2096
GPDMA1_GLOBAL_TypeDef::RESERVED19
__I uint32_t RESERVED19
Definition: XMC4800.h:717
USB0_GLOBAL_TypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: XMC4800.h:1769
ETH_GLOBAL_TypeDef::TARGET_TIME_NANOSECONDS
__IO uint32_t TARGET_TIME_NANOSECONDS
Definition: XMC4800.h:1456
USB0_EP_TypeDef::DIEPCTL_ISOCONT
__IO uint32_t DIEPCTL_ISOCONT
Definition: XMC4800.h:1821
PORT0_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2413
GPDMA0_GLOBAL_TypeDef::CLEARSRCTRAN
__O uint32_t CLEARSRCTRAN
Definition: XMC4800.h:581
USIC_CH_TypeDef::PCR_SSCMode
__IO uint32_t PCR_SSCMode
Definition: XMC4800.h:1922
VADC0_C0_1_IRQn
@ VADC0_C0_1_IRQn
Definition: XMC4800.h:90
CCU8_CC8_TypeDef::PR
__I uint32_t PR
Definition: XMC4800.h:2335
CAN0_4_IRQn
@ CAN0_4_IRQn
Definition: XMC4800.h:151
__I
#define __I
Definition: core_cm4.h:219
SCU_GENERAL_TypeDef::DTSSTAT
__I uint32_t DTSSTAT
Definition: XMC4800.h:1015
ETH_GLOBAL_TypeDef::HASH_TABLE_HIGH
__IO uint32_t HASH_TABLE_HIGH
Definition: XMC4800.h:1310
CAN_GLOBAL_TypeDef::PANCTR
__IO uint32_t PANCTR
Definition: XMC4800.h:1981
GPDMA0_GLOBAL_TypeDef::RESERVED23
__I uint32_t RESERVED23
Definition: XMC4800.h:594
PORT8_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2645
GPDMA0_GLOBAL_TypeDef::RESERVED24
__I uint32_t RESERVED24
Definition: XMC4800.h:596
PORT15_Type
Port 15 (PORT15)
Definition: XMC4800.h:2724
USB0_GLOBAL_TypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: XMC4800.h:1764
USB0_GLOBAL_TypeDef::HPRT
__IO uint32_t HPRT
Definition: XMC4800.h:1757
PORT8_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2654
CCU4_CC4_TypeDef::CR
__I uint32_t CR
Definition: XMC4800.h:2273
ETH_GLOBAL_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:1379
GPDMA1_GLOBAL_TypeDef::RAWSRCTRAN
__IO uint32_t RAWSRCTRAN
Definition: XMC4800.h:682
PPB_Type::NVIC_IPR1
__IO uint32_t NVIC_IPR1
Definition: XMC4800.h:435
GPDMA0_CH2_7_Type::DAR
__IO uint32_t DAR
Definition: XMC4800.h:658
PORT9_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2681
SCU_RESET_TypeDef::PRCLR1
__O uint32_t PRCLR1
Definition: XMC4800.h:1144
PPB_Type::NVIC_IPR17
__IO uint32_t NVIC_IPR17
Definition: XMC4800.h:451
SDMMC_GLOBAL_TypeDef::POWER_CTRL
__IO uint8_t POWER_CTRL
Definition: XMC4800.h:1215
GPDMA1_GLOBAL_TypeDef
General Purpose DMA Unit 1 (GPDMA1)
Definition: XMC4800.h:677
GPDMA0_CH2_7_Type::CTLL
__IO uint32_t CTLL
Definition: XMC4800.h:660
CAN0_6_IRQn
@ CAN0_6_IRQn
Definition: XMC4800.h:153
GPDMA1_CH_TypeDef::DAR
__IO uint32_t DAR
Definition: XMC4800.h:755
PORT14_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2710
SCU_CLK_TypeDef::CGATSTAT3
__I uint32_t CGATSTAT3
Definition: XMC4800.h:950
ETH_GLOBAL_TypeDef::MAC_ADDRESS3_HIGH
__IO uint32_t MAC_ADDRESS3_HIGH
Definition: XMC4800.h:1329
VADC0_C0_2_IRQn
@ VADC0_C0_2_IRQn
Definition: XMC4800.h:91
PORT3_Type::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:2505
GPDMA0_GLOBAL_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:556
ETH_GLOBAL_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:1416
PORT1_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2451
GPDMA0_GLOBAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:548
USB0_GLOBAL_TypeDef::DIEPTXF1
__IO uint32_t DIEPTXF1
Definition: XMC4800.h:1741
VADC_G_TypeDef::RESERVED16
__I uint32_t RESERVED16
Definition: XMC4800.h:2129
PPB_Type::FPCCR
__IO uint32_t FPCCR
Definition: XMC4800.h:496
ECAT_Type::DC_SPEED_COUNT_FIL_DEPTH
__IO uint8_t DC_SPEED_COUNT_FIL_DEPTH
Definition: XMC4800.h:1615
USIC_CH_TypeDef::PSR_SSCMode
__IO uint32_t PSR_SSCMode
Definition: XMC4800.h:1932
PPB_Type::SYST_RVR
__IO uint32_t SYST_RVR
Definition: XMC4800.h:405
ETH_GLOBAL_TypeDef::RX_65TO127OCTETS_FRAMES_GOOD_BAD
__I uint32_t RX_65TO127OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1393
DAC_GLOBAL_TypeDef::DAC1PATH
__IO uint32_t DAC1PATH
Definition: XMC4800.h:2223
SCU_CLK_TypeDef::CGATSET0
__O uint32_t CGATSET0
Definition: XMC4800.h:942
PORT9_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2679
ECAT_Type::EVENT_MASK
__I uint16_t EVENT_MASK
Definition: XMC4800.h:1558
ETH_GLOBAL_TypeDef::HASH_TABLE_LOW
__IO uint32_t HASH_TABLE_LOW
Definition: XMC4800.h:1311
GPDMA1_GLOBAL_TypeDef::MASKSRCTRAN
__IO uint32_t MASKSRCTRAN
Definition: XMC4800.h:702
PORT7_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2618
USIC_CH_TypeDef::TCSR
__IO uint32_t TCSR
Definition: XMC4800.h:1917
POSIF_GLOBAL_TypeDef::PRUN
__I uint32_t PRUN
Definition: XMC4800.h:2374
EBU_Type::SDRMREF
__IO uint32_t SDRMREF
Definition: XMC4800.h:1279
SDMMC_GLOBAL_TypeDef::BLOCK_SIZE
__IO uint16_t BLOCK_SIZE
Definition: XMC4800.h:1203
CAN_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:1972
ECAT_Type::PROC_ERR_COUNT
__I uint8_t PROC_ERR_COUNT
Definition: XMC4800.h:1572
USB0_EP0_TypeDef::DOEPINT0
__IO uint32_t DOEPINT0
Definition: XMC4800.h:1799
ECAT_Type::RESERVED34
__I uint32_t RESERVED34
Definition: XMC4800.h:1648
GPDMA1_CH_TypeDef::CFGL
__IO uint32_t CFGL
Definition: XMC4800.h:760
CCU8_CC8_TypeDef::ECRD0
__I uint32_t ECRD0
Definition: XMC4800.h:2355
PPB_Type::NVIC_ISPR2
__IO uint32_t NVIC_ISPR2
Definition: XMC4800.h:421
ETH_GLOBAL_TypeDef::RX_MULTICAST_FRAMES_GOOD
__I uint32_t RX_MULTICAST_FRAMES_GOOD
Definition: XMC4800.h:1384
ECAT_Type::RUN_LED
__IO uint8_t RUN_LED
Definition: XMC4800.h:1548
DSD_CH_TypeDef::FCFGC
__IO uint32_t FCFGC
Definition: XMC4800.h:2181
USIC_CH_TypeDef::RBUF
__I uint32_t RBUF
Definition: XMC4800.h:1938
SCU_HIBERNATE_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1098
GPDMA0_CH_TypeDef::CTLL
__IO uint32_t CTLL
Definition: XMC4800.h:628
PBA_GLOBAL_TypeDef
Peripheral Bridge AHB 0 (PBA)
Definition: XMC4800.h:811
CCU4_GLOBAL_TypeDef::GCTRL
__IO uint32_t GCTRL
Definition: XMC4800.h:2237
SCU_RESET_TypeDef
System Control Unit (SCU_RESET)
Definition: XMC4800.h:1135
CAN0_2_IRQn
@ CAN0_2_IRQn
Definition: XMC4800.h:149
USIC_CH_TypeDef::CMTR
__IO uint32_t CMTR
Definition: XMC4800.h:1927
ETH_GLOBAL_TypeDef::RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
__I uint32_t RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1401
PPB_Type::NVIC_ISPR1
__IO uint32_t NVIC_ISPR1
Definition: XMC4800.h:420
VADC_G_TypeDef::SEVNP
__IO uint32_t SEVNP
Definition: XMC4800.h:2122
PORT2_Type::IOCR12
__IO uint32_t IOCR12
Definition: XMC4800.h:2474
ETH_GLOBAL_TypeDef::RXIPV4_GOOD_FRAMES
__I uint32_t RXIPV4_GOOD_FRAMES
Definition: XMC4800.h:1417
GPDMA0_GLOBAL_TypeDef::CHENREG
__IO uint32_t CHENREG
Definition: XMC4800.h:603
ECAT_Type::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:1537
ECAT_Type::ESC_DL_CONTROL
__I uint32_t ESC_DL_CONTROL
Definition: XMC4800.h:1536
EBU_Type::BUSRAP0
__IO uint32_t BUSRAP0
Definition: XMC4800.h:1262
GPDMA0_GLOBAL_TypeDef::MASKERR
__IO uint32_t MASKERR
Definition: XMC4800.h:575
GPDMA0_GLOBAL_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:554
SDMMC_GLOBAL_TypeDef::EN_INT_SIGNAL_ERR
__IO uint16_t EN_INT_SIGNAL_ERR
Definition: XMC4800.h:1226
SysTick_IRQn
@ SysTick_IRQn
Definition: XMC4800.h:77
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
USIC0_2_IRQn
@ USIC0_2_IRQn
Definition: XMC4800.h:157
USIC_CH_TypeDef::TBCTR
__IO uint32_t TBCTR
Definition: XMC4800.h:1948
CAN_MO_TypeDef::MODATAL
__IO uint32_t MODATAL
Definition: XMC4800.h:380
EBU_Type::ID
__I uint32_t ID
Definition: XMC4800.h:1254
PPB_Type::ACTLR
__IO uint32_t ACTLR
Definition: XMC4800.h:402
VADC0_C0_3_IRQn
@ VADC0_C0_3_IRQn
Definition: XMC4800.h:92
ECAT0_FMMU_Type::FMMU_L_START_BIT
__I uint8_t FMMU_L_START_BIT
Definition: XMC4800.h:1665
ETH_GLOBAL_TypeDef::SYSTEM_TIME_SECONDS_UPDATE
__IO uint32_t SYSTEM_TIME_SECONDS_UPDATE
Definition: XMC4800.h:1452
DSD_CH_TypeDef::RECTCFG
__IO uint32_t RECTCFG
Definition: XMC4800.h:2198
GPDMA1_GLOBAL_TypeDef::CLEARSRCTRAN
__O uint32_t CLEARSRCTRAN
Definition: XMC4800.h:712
ETH_GLOBAL_TypeDef
Ethernet Unit 0 (ETH)
Definition: XMC4800.h:1307
EBU_Type::SDRMOD
__IO uint32_t SDRMOD
Definition: XMC4800.h:1278
ETH_GLOBAL_TypeDef::RXIPV6_HEADER_ERROR_OCTETS
__I uint32_t RXIPV6_HEADER_ERROR_OCTETS
Definition: XMC4800.h:1439
PORT4_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2528
CAN_NODE_TypeDef::NECNT
__IO uint32_t NECNT
Definition: XMC4800.h:2002
ETH_GLOBAL_TypeDef::VLAN_TAG
__IO uint32_t VLAN_TAG
Definition: XMC4800.h:1315
ECAT0_CON_Type::CONP1
__IO uint32_t CONP1
Definition: XMC4800.h:1493
SDMMC_GLOBAL_TypeDef::RESPONSE6
__I uint32_t RESPONSE6
Definition: XMC4800.h:1211
SCU_CLK_TypeDef
System Control Unit (SCU_CLK)
Definition: XMC4800.h:924
VADC_GLOBAL_TypeDef::GLOBEFLAG
__IO uint32_t GLOBEFLAG
Definition: XMC4800.h:2043
CCU80_2_IRQn
@ CCU80_2_IRQn
Definition: XMC4800.h:137
PORT15_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2730
GPDMA1_GLOBAL_TypeDef::REQSRCREG
__IO uint32_t REQSRCREG
Definition: XMC4800.h:720
PORT5_Type
Port 5 (PORT5)
Definition: XMC4800.h:2554
DSD_CH_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:2187
SCU_INTERRUPT_TypeDef::SRSET
__O uint32_t SRSET
Definition: XMC4800.h:1040
SDMMC_CON_Type::SDMMC_CON
__IO uint32_t SDMMC_CON
Definition: XMC4800.h:1188
DSD_CH_TypeDef::BOUNDSEL
__IO uint32_t BOUNDSEL
Definition: XMC4800.h:2186
PPB_Type::NVIC_IPR2
__IO uint32_t NVIC_IPR2
Definition: XMC4800.h:436
WDT_GLOBAL_TypeDef::WUB
__IO uint32_t WUB
Definition: XMC4800.h:886
POSIF_GLOBAL_TypeDef::PCONF
__IO uint32_t PCONF
Definition: XMC4800.h:2370
USB0_GLOBAL_TypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: XMC4800.h:1763
ETH_GLOBAL_TypeDef::MAC_ADDRESS0_HIGH
__IO uint32_t MAC_ADDRESS0_HIGH
Definition: XMC4800.h:1323
GPDMA1_GLOBAL_TypeDef::RESERVED14
__I uint32_t RESERVED14
Definition: XMC4800.h:707
DSD0_A_6_IRQn
@ DSD0_A_6_IRQn
Definition: XMC4800.h:115
PORT2_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2471
ECAT_Type::RESERVED30
__I uint32_t RESERVED30
Definition: XMC4800.h:1630
PORT6_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2587
POSIF_GLOBAL_TypeDef::PFLG
__I uint32_t PFLG
Definition: XMC4800.h:2389
DLR_GLOBAL_TypeDef::SRSEL1
__IO uint32_t SRSEL1
Definition: XMC4800.h:515
SCU_HIBERNATE_TypeDef::HDSTAT
__I uint32_t HDSTAT
Definition: XMC4800.h:1094
BusFault_IRQn
@ BusFault_IRQn
Definition: XMC4800.h:71
ETH_GLOBAL_TypeDef::RX_128TO255OCTETS_FRAMES_GOOD_BAD
__I uint32_t RX_128TO255OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1395
SCU_PLL_TypeDef::PLLCON1
__IO uint32_t PLLCON1
Definition: XMC4800.h:985
EBU_Type::BUSRCON1
__IO uint32_t BUSRCON1
Definition: XMC4800.h:1265
CCU43_2_IRQn
@ CCU43_2_IRQn
Definition: XMC4800.h:133
CCU8_CC8_TypeDef
Capture Compare Unit 8 - Unit 0 (CCU8_CC8)
Definition: XMC4800.h:2322
ETH_GLOBAL_TypeDef::RXIPV6_NO_PAYLOAD_FRAMES
__I uint32_t RXIPV6_NO_PAYLOAD_FRAMES
Definition: XMC4800.h:1425
GPDMA1_GLOBAL_TypeDef::RAWBLOCK
__IO uint32_t RAWBLOCK
Definition: XMC4800.h:680
CCU8_CC8_TypeDef::CHC
__IO uint32_t CHC
Definition: XMC4800.h:2341
CCU8_CC8_TypeDef::TCSET
__O uint32_t TCSET
Definition: XMC4800.h:2326
GPDMA0_GLOBAL_TypeDef::STATUSDSTTRAN
__I uint32_t STATUSDSTTRAN
Definition: XMC4800.h:563
ECAT_Type::LOST_LINK_COUNT0
__I uint8_t LOST_LINK_COUNT0
Definition: XMC4800.h:1575
SCU_RESET_TypeDef::PRCLR3
__O uint32_t PRCLR3
Definition: XMC4800.h:1150
PORT6_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2592
PORT15_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2728
PPB_Type::NVIC_IPR24
__IO uint32_t NVIC_IPR24
Definition: XMC4800.h:458
CCU8_GLOBAL_TypeDef::GCTRL
__IO uint32_t GCTRL
Definition: XMC4800.h:2300
ECAT_Type::RESERVED20
__I uint16_t RESERVED20
Definition: XMC4800.h:1574
PPB_Type::SYST_CALIB
__IO uint32_t SYST_CALIB
Definition: XMC4800.h:407
SCU_CLK_TypeDef::CGATSET2
__O uint32_t CGATSET2
Definition: XMC4800.h:948
FCE_KE_TypeDef::CRC
__IO uint32_t CRC
Definition: XMC4800.h:797
PPB_Type::NVIC_IPR18
__IO uint32_t NVIC_IPR18
Definition: XMC4800.h:452
FCE_GLOBAL_TypeDef
Flexible CRC Engine (FCE)
Definition: XMC4800.h:774
ERU_GLOBAL_TypeDef
Event Request Unit 0 (ERU)
Definition: XMC4800.h:529
PORT0_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2411
RTC_GLOBAL_TypeDef::CTR
__IO uint32_t CTR
Definition: XMC4800.h:903
ECAT_Type::SYNC_MANAGER
__I uint8_t SYNC_MANAGER
Definition: XMC4800.h:1511
DSD0_M_1_IRQn
@ DSD0_M_1_IRQn
Definition: XMC4800.h:110
GPDMA0_CH_TypeDef::CTLH
__IO uint32_t CTLH
Definition: XMC4800.h:629
ETH_GLOBAL_TypeDef::TX_UNICAST_FRAMES_GOOD_BAD
__I uint32_t TX_UNICAST_FRAMES_GOOD_BAD
Definition: XMC4800.h:1354
ECAT_Type::AL_EVENT_REQ
__IO uint32_t AL_EVENT_REQ
Definition: XMC4800.h:1564
GPDMA1_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:736
PORT15_Type::PDISC
__IO uint32_t PDISC
Definition: XMC4800.h:2735
POSIF_GLOBAL_TypeDef::RPFLG
__O uint32_t RPFLG
Definition: XMC4800.h:2392
CCU4_CC4_TypeDef::PR
__I uint32_t PR
Definition: XMC4800.h:2271
EBU_Type::BUSWAP3
__IO uint32_t BUSWAP3
Definition: XMC4800.h:1276
SCU_TRAP_TypeDef::TRAPDIS
__IO uint32_t TRAPDIS
Definition: XMC4800.h:1078
USB0_EP0_TypeDef::DIEPTSIZ0
__IO uint32_t DIEPTSIZ0
Definition: XMC4800.h:1792
PPB_Type::SHCSR
__IO uint32_t SHCSR
Definition: XMC4800.h:472
DSD0_M_3_IRQn
@ DSD0_M_3_IRQn
Definition: XMC4800.h:112
PORT1_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2453
ETH_GLOBAL_TypeDef::TX_OSIZE_FRAMES_GOOD
__I uint32_t TX_OSIZE_FRAMES_GOOD
Definition: XMC4800.h:1378
PORT3_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2502
CCU40_0_IRQn
@ CCU40_0_IRQn
Definition: XMC4800.h:119
PPB_Type::MPU_TYPE
__I uint32_t MPU_TYPE
Definition: XMC4800.h:482
ETH_GLOBAL_TypeDef::RXUDP_ERROR_OCTETS
__I uint32_t RXUDP_ERROR_OCTETS
Definition: XMC4800.h:1442
USIC2_5_IRQn
@ USIC2_5_IRQn
Definition: XMC4800.h:172
ETH_GLOBAL_TypeDef::RXIPV4_HEADER_ERROR_OCTETS
__I uint32_t RXIPV4_HEADER_ERROR_OCTETS
Definition: XMC4800.h:1434
PBA_GLOBAL_TypeDef::WADDR
__I uint32_t WADDR
Definition: XMC4800.h:813
ETH_GLOBAL_TypeDef::FLOW_CONTROL
__IO uint32_t FLOW_CONTROL
Definition: XMC4800.h:1314
RTC_GLOBAL_TypeDef::MSKSR
__IO uint32_t MSKSR
Definition: XMC4800.h:906
USIC_CH_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1903
GPDMA0_CH_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:633
GPDMA0_CH_TypeDef::SSTATAR
__IO uint32_t SSTATAR
Definition: XMC4800.h:634
USIC2_0_IRQn
@ USIC2_0_IRQn
Definition: XMC4800.h:167
ECAT_Type::DC_RCV_TIME_PORT0
__I uint32_t DC_RCV_TIME_PORT0
Definition: XMC4800.h:1600
CAN0_3_IRQn
@ CAN0_3_IRQn
Definition: XMC4800.h:150
LEDTS0_GLOBAL_TypeDef::LINE1
__IO uint32_t LINE1
Definition: XMC4800.h:1170
VADC_G_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:2086
CCU81_2_IRQn
@ CCU81_2_IRQn
Definition: XMC4800.h:141
SDMMC_GLOBAL_TypeDef::INT_STATUS_ERR
__IO uint16_t INT_STATUS_ERR
Definition: XMC4800.h:1222
GPDMA0_GLOBAL_TypeDef::RESERVED28
__I uint32_t RESERVED28
Definition: XMC4800.h:604
SCU_CLK_TypeDef::EXTCLKCR
__IO uint32_t EXTCLKCR
Definition: XMC4800.h:935
SDMMC_GLOBAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1202
ECAT0_SM_Type::SM_P_START_ADR
__I uint16_t SM_P_START_ADR
Definition: XMC4800.h:1684
USIC_CH_TypeDef::PSR_IISMode
__IO uint32_t PSR_IISMode
Definition: XMC4800.h:1931
GPDMA0_GLOBAL_TypeDef::MASKSRCTRAN
__IO uint32_t MASKSRCTRAN
Definition: XMC4800.h:571
VADC_G_TypeDef::QINR0
__O uint32_t QINR0
Definition: XMC4800.h:2101
SCU_RESET_TypeDef::PRCLR2
__O uint32_t PRCLR2
Definition: XMC4800.h:1147
USB0_GLOBAL_TypeDef::GNPTXSTS
__I uint32_t GNPTXSTS
Definition: XMC4800.h:1734
PORT14_Type::IOCR12
__IO uint32_t IOCR12
Definition: XMC4800.h:2704
GPDMA0_CH_TypeDef::SAR
__IO uint32_t SAR
Definition: XMC4800.h:622
DSD0_A_5_IRQn
@ DSD0_A_5_IRQn
Definition: XMC4800.h:114
ECAT_Type::AL_EVENT_MASK
__IO uint32_t AL_EVENT_MASK
Definition: XMC4800.h:1560
PORT2_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2473
SCU_HIBERNATE_TypeDef::OSCULCTRL
__IO uint32_t OSCULCTRL
Definition: XMC4800.h:1101
ECAT0_FMMU_Type::FMMU_L_START_ADR
__I uint32_t FMMU_L_START_ADR
Definition: XMC4800.h:1663
VADC_G_TypeDef::ALIAS
__IO uint32_t ALIAS
Definition: XMC4800.h:2083
PPB_Type::FPCAR
__IO uint32_t FPCAR
Definition: XMC4800.h:497
GPDMA1_GLOBAL_TypeDef::CHENREG
__IO uint32_t CHENREG
Definition: XMC4800.h:734
GPDMA1_GLOBAL_TypeDef::STATUSDSTTRAN
__I uint32_t STATUSDSTTRAN
Definition: XMC4800.h:694
SCU_PARITY_TypeDef::PMTPR
__IO uint32_t PMTPR
Definition: XMC4800.h:1061
PPB_Type::NVIC_IPR23
__IO uint32_t NVIC_IPR23
Definition: XMC4800.h:457
DAC_GLOBAL_TypeDef
Digital to Analog Converter (DAC)
Definition: XMC4800.h:2211
SCU_OSC_TypeDef::CLKCALCONST
__IO uint32_t CLKCALCONST
Definition: XMC4800.h:969
ECAT_Type::FWD_RX_ERR_COUNT0
__I uint8_t FWD_RX_ERR_COUNT0
Definition: XMC4800.h:1569
USIC2_4_IRQn
@ USIC2_4_IRQn
Definition: XMC4800.h:171
VADC_G_TypeDef::SYNCTR
__IO uint32_t SYNCTR
Definition: XMC4800.h:2087
ECAT0_FMMU_Type::FMMU_ACT
__I uint8_t FMMU_ACT
Definition: XMC4800.h:1670
GPDMA0_CH_TypeDef::DSTATAR
__IO uint32_t DSTATAR
Definition: XMC4800.h:636
CAN_MO_TypeDef::MOAR
__IO uint32_t MOAR
Definition: XMC4800.h:382
PORT4_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2534
PORT8_Type
Port 8 (PORT8)
Definition: XMC4800.h:2639
VADC_GLOBAL_TypeDef
Analog to Digital Converter (VADC)
Definition: XMC4800.h:2030
ETH_GLOBAL_TypeDef::TX_DEFERRED_FRAMES
__I uint32_t TX_DEFERRED_FRAMES
Definition: XMC4800.h:1365
ETH_GLOBAL_TypeDef::MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER
__I uint32_t MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER
Definition: XMC4800.h:1468
SCU_CLK_TypeDef::WDTCLKCR
__IO uint32_t WDTCLKCR
Definition: XMC4800.h:934
FCE_KE_TypeDef::CTR
__IO uint32_t CTR
Definition: XMC4800.h:798
GPDMA0_GLOBAL_TypeDef::STATUSBLOCK
__I uint32_t STATUSBLOCK
Definition: XMC4800.h:559
SCU_RESET_TypeDef::PRSTAT1
__I uint32_t PRSTAT1
Definition: XMC4800.h:1142
VADC_GLOBAL_TypeDef::EMUXSEL
__IO uint32_t EMUXSEL
Definition: XMC4800.h:2062
USB0_GLOBAL_TypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: XMC4800.h:1704
USB0_EP0_TypeDef::DOEPDMAB0
__I uint32_t DOEPDMAB0
Definition: XMC4800.h:1804
VADC0_G0_2_IRQn
@ VADC0_G0_2_IRQn
Definition: XMC4800.h:95
PORT5_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2560
ETH_GLOBAL_TypeDef::MAC_ADDRESS0_LOW
__IO uint32_t MAC_ADDRESS0_LOW
Definition: XMC4800.h:1324
ECAT_Type::PDI_CONFIG
__I uint8_t PDI_CONFIG
Definition: XMC4800.h:1554
VADC0_G0_1_IRQn
@ VADC0_G0_1_IRQn
Definition: XMC4800.h:94
GPDMA1_GLOBAL_TypeDef::RESERVED8
__I uint32_t RESERVED8
Definition: XMC4800.h:695
CCU4_GLOBAL_TypeDef::GSTAT
__I uint32_t GSTAT
Definition: XMC4800.h:2238
CCU4_CC4_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:2284
VADC_GLOBAL_TypeDef::BRSMR
__IO uint32_t BRSMR
Definition: XMC4800.h:2054
GPDMA1_GLOBAL_TypeDef::RAWDSTTRAN
__IO uint32_t RAWDSTTRAN
Definition: XMC4800.h:684
SDMMC_GLOBAL_TypeDef::ACMD_ERR_STATUS
__I uint16_t ACMD_ERR_STATUS
Definition: XMC4800.h:1227
USB0_CH_TypeDef::HCTSIZ_BUFFERMODE
__IO uint32_t HCTSIZ_BUFFERMODE
Definition: XMC4800.h:1867
USB0_GLOBAL_TypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: XMC4800.h:1706
USIC_GLOBAL_TypeDef
Universal Serial Interface Controller 0 (USIC)
Definition: XMC4800.h:1888
PORT7_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2615
USB0_GLOBAL_TypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: XMC4800.h:1728
ETH_GLOBAL_TypeDef::TX_CARRIER_ERROR_FRAMES
__I uint32_t TX_CARRIER_ERROR_FRAMES
Definition: XMC4800.h:1370
USB0_EP_TypeDef::DOEPCTL_ISOCONT
__IO uint32_t DOEPCTL_ISOCONT
Definition: XMC4800.h:1834
CCU8_CC8_TypeDef::CR2S
__IO uint32_t CR2S
Definition: XMC4800.h:2340
DSD_CH_TypeDef::TSTMP
__I uint32_t TSTMP
Definition: XMC4800.h:2194
PPB_Type::MPU_RASR
__IO uint32_t MPU_RASR
Definition: XMC4800.h:486
UsageFault_IRQn
@ UsageFault_IRQn
Definition: XMC4800.h:73
DAC_GLOBAL_TypeDef::DAC1CFG0
__IO uint32_t DAC1CFG0
Definition: XMC4800.h:2215
CCU41_2_IRQn
@ CCU41_2_IRQn
Definition: XMC4800.h:125
CCU4_GLOBAL_TypeDef
Capture Compare Unit 4 - Unit 0 (CCU4)
Definition: XMC4800.h:2236
PPB_Type::NVIC_IABR0
__IO uint32_t NVIC_IABR0
Definition: XMC4800.h:429
VADC0_G2_1_IRQn
@ VADC0_G2_1_IRQn
Definition: XMC4800.h:102
POSIF_GLOBAL_TypeDef::PDBG
__I uint32_t PDBG
Definition: XMC4800.h:2394
ERU1_3_IRQn
@ ERU1_3_IRQn
Definition: XMC4800.h:87
DSD0_M_0_IRQn
@ DSD0_M_0_IRQn
Definition: XMC4800.h:109
ETH_GLOBAL_TypeDef::BUS_MODE
__IO uint32_t BUS_MODE
Definition: XMC4800.h:1460
GPDMA0_GLOBAL_TypeDef::RESERVED10
__I uint32_t RESERVED10
Definition: XMC4800.h:568
CCU43_0_IRQn
@ CCU43_0_IRQn
Definition: XMC4800.h:131
USIC0_4_IRQn
@ USIC0_4_IRQn
Definition: XMC4800.h:159
USIC_CH_TypeDef::SCTR
__IO uint32_t SCTR
Definition: XMC4800.h:1916
USB0_EP_TypeDef::DOEPTSIZ_ISO
__IO uint32_t DOEPTSIZ_ISO
Definition: XMC4800.h:1842
USB0_GLOBAL_TypeDef
Universal Serial Bus (USB)
Definition: XMC4800.h:1702
FLASH0_GLOBAL_TypeDef::FSR
__I uint32_t FSR
Definition: XMC4800.h:830
VADC_G_TypeDef::CEVNP0
__IO uint32_t CEVNP0
Definition: XMC4800.h:2117
SCU_PARITY_TypeDef::PETE
__IO uint32_t PETE
Definition: XMC4800.h:1057
ETH_GLOBAL_TypeDef::INTERRUPT_STATUS
__I uint32_t INTERRUPT_STATUS
Definition: XMC4800.h:1321
PORT7_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2611
ECAT_Type::EEP_CONT_STAT
__IO uint16_t EEP_CONT_STAT
Definition: XMC4800.h:1590
PPB_Type::NVIC_ICER2
__IO uint32_t NVIC_ICER2
Definition: XMC4800.h:416
PORT14_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2706
SCU_RESET_TypeDef::PRSET0
__O uint32_t PRSET0
Definition: XMC4800.h:1140
FLASH0_GLOBAL_TypeDef
Flash Memory Controller (FLASH)
Definition: XMC4800.h:826
SCU_RESET_TypeDef::PRSTAT2
__I uint32_t PRSTAT2
Definition: XMC4800.h:1145
ECAT0_SM_Type::SM_LEN
__I uint16_t SM_LEN
Definition: XMC4800.h:1685
PORT15_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2737
EBU_Type::SDRSTAT
__I uint32_t SDRSTAT
Definition: XMC4800.h:1280
PORT14_Type::PDISC
__IO uint32_t PDISC
Definition: XMC4800.h:2708
RTC_GLOBAL_TypeDef::STSSR
__I uint32_t STSSR
Definition: XMC4800.h:905
ECAT_Type::DC_LATCH1_STAT
__I uint8_t DC_LATCH1_STAT
Definition: XMC4800.h:1632
ETH_GLOBAL_TypeDef::RXTCP_GOOD_OCTETS
__I uint32_t RXTCP_GOOD_OCTETS
Definition: XMC4800.h:1443
USB0_CH_TypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: XMC4800.h:1863
WDT_GLOBAL_TypeDef
Watch Dog Timer (WDT)
Definition: XMC4800.h:880
CCU8_CC8_TypeDef::ECRD1
__I uint32_t ECRD1
Definition: XMC4800.h:2356
SCU_HIBERNATE_TypeDef::OSCSICTRL
__IO uint32_t OSCSICTRL
Definition: XMC4800.h:1099
PORT7_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2620
GPDMA1_GLOBAL_TypeDef::RESERVED6
__I uint32_t RESERVED6
Definition: XMC4800.h:691
PPB_Type::NVIC_ICER3
__IO uint32_t NVIC_ICER3
Definition: XMC4800.h:417
PMU0_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:867
ETH_GLOBAL_TypeDef::MAC_FRAME_FILTER
__IO uint32_t MAC_FRAME_FILTER
Definition: XMC4800.h:1309
GPDMA0_CH2_7_Type::SAR
__IO uint32_t SAR
Definition: XMC4800.h:656
CAN_NODE_TypeDef::NIPR
__IO uint32_t NIPR
Definition: XMC4800.h:1999
LEDTS0_GLOBAL_TypeDef::TSVAL
__IO uint32_t TSVAL
Definition: XMC4800.h:1168
ECAT_Type::ESC_RESET_ECAT_READMode
__I uint8_t ESC_RESET_ECAT_READMode
Definition: XMC4800.h:1527
GPDMA1_GLOBAL_TypeDef::RESERVED18
__I uint32_t RESERVED18
Definition: XMC4800.h:715
PPB_Type::SHPR1
__IO uint32_t SHPR1
Definition: XMC4800.h:469
ECAT_Type::DC_ECAT_CNG_EV_TIME
__I uint32_t DC_ECAT_CNG_EV_TIME
Definition: XMC4800.h:1642
CCU4_GLOBAL_TypeDef::MIDR
__I uint32_t MIDR
Definition: XMC4800.h:2245
SCU_GENERAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1007
ETH_GLOBAL_TypeDef::RX_WATCHDOG_ERROR_FRAMES
__I uint32_t RX_WATCHDOG_ERROR_FRAMES
Definition: XMC4800.h:1409
PORT5_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2559
USB0_EP_TypeDef::DIEPDMAB
__I uint32_t DIEPDMAB
Definition: XMC4800.h:1829
PPB_Type::HFSR
__IO uint32_t HFSR
Definition: XMC4800.h:474
PORT6_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2590
USB0_EP_TypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: XMC4800.h:1844
SCU_GENERAL_TypeDef
System Control Unit (SCU_GENERAL)
Definition: XMC4800.h:1003
GPDMA1_GLOBAL_TypeDef::TYPE
__I uint32_t TYPE
Definition: XMC4800.h:738
SCU_CLK_TypeDef::EBUCLKCR
__IO uint32_t EBUCLKCR
Definition: XMC4800.h:932
USB0_GLOBAL_TypeDef::RESERVED7
__I uint32_t RESERVED7
Definition: XMC4800.h:1762
SCU_CLK_TypeDef::MLINKCLKCR
__IO uint32_t MLINKCLKCR
Definition: XMC4800.h:936
PORT3_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2513
USB0_EP_TypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: XMC4800.h:1827
ECAT0_FMMU_Type::FMMU_LEN
__I uint16_t FMMU_LEN
Definition: XMC4800.h:1664
ETH_GLOBAL_TypeDef::RX_RECEIVE_ERROR_FRAMES
__I uint32_t RX_RECEIVE_ERROR_FRAMES
Definition: XMC4800.h:1410
GPDMA0_GLOBAL_TypeDef::CLEARDSTTRAN
__O uint32_t CLEARDSTTRAN
Definition: XMC4800.h:583
ETH_GLOBAL_TypeDef::RXUDP_GOOD_FRAMES
__I uint32_t RXUDP_GOOD_FRAMES
Definition: XMC4800.h:1426
SDMMC_GLOBAL_TypeDef::INT_STATUS_NORM
__IO uint16_t INT_STATUS_NORM
Definition: XMC4800.h:1221
GPDMA0_CH_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:635
USB0_EP_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:1836
PORT4_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2536
RTC_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:902
CCU81_3_IRQn
@ CCU81_3_IRQn
Definition: XMC4800.h:142
ECAT_Type::RX_ERR_COUNT0
__I uint16_t RX_ERR_COUNT0
Definition: XMC4800.h:1566
DAC_GLOBAL_TypeDef::DAC0CFG0
__IO uint32_t DAC0CFG0
Definition: XMC4800.h:2213
SCU_TRAP_TypeDef::TRAPSET
__O uint32_t TRAPSET
Definition: XMC4800.h:1080
CCU4_GLOBAL_TypeDef::GIDLS
__O uint32_t GIDLS
Definition: XMC4800.h:2239
ETH_GLOBAL_TypeDef::RX_CONTROL_FRAMES_GOOD
__I uint32_t RX_CONTROL_FRAMES_GOOD
Definition: XMC4800.h:1411
SCU_CLK_TypeDef::PBCLKCR
__IO uint32_t PBCLKCR
Definition: XMC4800.h:930
PPB_Type::NVIC_ICER0
__IO uint32_t NVIC_ICER0
Definition: XMC4800.h:414
GPDMA0_GLOBAL_TypeDef::RAWTFR
__IO uint32_t RAWTFR
Definition: XMC4800.h:547
GPDMA0_GLOBAL_TypeDef::DMACFGREG
__IO uint32_t DMACFGREG
Definition: XMC4800.h:601
PORT3_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2514
PORT4_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2538
SCU_TRAP_TypeDef::TRAPCLR
__O uint32_t TRAPCLR
Definition: XMC4800.h:1079
USIC_CH_TypeDef::DX4CR
__IO uint32_t DX4CR
Definition: XMC4800.h:1914
PORT15_Type::IOCR12
__IO uint32_t IOCR12
Definition: XMC4800.h:2731
USIC_CH_TypeDef::PCR_ASCMode
__IO uint32_t PCR_ASCMode
Definition: XMC4800.h:1924
ETH_GLOBAL_TypeDef::SYSTEM_TIME_NANOSECONDS_UPDATE
__IO uint32_t SYSTEM_TIME_NANOSECONDS_UPDATE
Definition: XMC4800.h:1453
PORT9_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2673
USIC1_3_IRQn
@ USIC1_3_IRQn
Definition: XMC4800.h:164
SCU_PARITY_TypeDef::PEFLAG
__IO uint32_t PEFLAG
Definition: XMC4800.h:1060
ECAT_Type::MII_CONT_STAT
__IO uint16_t MII_CONT_STAT
Definition: XMC4800.h:1593
POSIF_GLOBAL_TypeDef::SPFLG
__O uint32_t SPFLG
Definition: XMC4800.h:2391
GPDMA0_GLOBAL_TypeDef::RESERVED15
__I uint32_t RESERVED15
Definition: XMC4800.h:578
PORT1_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2449
GPDMA1_GLOBAL_TypeDef::LSTDSTREG
__IO uint32_t LSTDSTREG
Definition: XMC4800.h:730
GPDMA1_GLOBAL_TypeDef::SGLREQSRCREG
__IO uint32_t SGLREQSRCREG
Definition: XMC4800.h:724
ETH_GLOBAL_TypeDef::RX_ALIGNMENT_ERROR_FRAMES
__I uint32_t RX_ALIGNMENT_ERROR_FRAMES
Definition: XMC4800.h:1386
VADC_GLOBAL_TypeDef::GLOBRES
__IO uint32_t GLOBRES
Definition: XMC4800.h:2058
ETH_GLOBAL_TypeDef::RXICMP_GOOD_FRAMES
__I uint32_t RXICMP_GOOD_FRAMES
Definition: XMC4800.h:1430
ECAT0_FMMU_Type
EtherCAT 0 (ECAT0_FMMU)
Definition: XMC4800.h:1662
HardFault_IRQn
@ HardFault_IRQn
Definition: XMC4800.h:68
CCU4_CC4_TypeDef::INTE
__IO uint32_t INTE
Definition: XMC4800.h:2280
RTC_GLOBAL_TypeDef::TIM1
__IO uint32_t TIM1
Definition: XMC4800.h:911
VADC0_G1_3_IRQn
@ VADC0_G1_3_IRQn
Definition: XMC4800.h:100
CCU4_CC4_TypeDef::PRS
__IO uint32_t PRS
Definition: XMC4800.h:2272
CCU8_CC8_TypeDef::FPC
__IO uint32_t FPC
Definition: XMC4800.h:2333
VADC_G_TypeDef::REVNP0
__IO uint32_t REVNP0
Definition: XMC4800.h:2119
FCE_KE_TypeDef::RES
__I uint32_t RES
Definition: XMC4800.h:792
ECAT_Type::DC_SYS_TIME_WRITEMode
__O uint32_t DC_SYS_TIME_WRITEMode
Definition: XMC4800.h:1606
DAC_GLOBAL_TypeDef::DAC1CFG1
__IO uint32_t DAC1CFG1
Definition: XMC4800.h:2216
SDMMC_GLOBAL_TypeDef::RESPONSE0
__I uint32_t RESPONSE0
Definition: XMC4800.h:1208
SDMMC_GLOBAL_TypeDef::RESERVED1
__I uint16_t RESERVED1
Definition: XMC4800.h:1228
ETH_GLOBAL_TypeDef::CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS
__I uint32_t CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS
Definition: XMC4800.h:1475
VADC_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:2033
ETH_GLOBAL_TypeDef::RECEIVE_POLL_DEMAND
__IO uint32_t RECEIVE_POLL_DEMAND
Definition: XMC4800.h:1462
USIC_CH_TypeDef::DX1CR
__IO uint32_t DX1CR
Definition: XMC4800.h:1911
SDMMC_GLOBAL_TypeDef::FORCE_EVENT_ACMD_ERR_STATUS
__O uint16_t FORCE_EVENT_ACMD_ERR_STATUS
Definition: XMC4800.h:1233
SCU_HIBERNATE_TypeDef
System Control Unit (SCU_HIBERNATE)
Definition: XMC4800.h:1093
PORT3_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2508
CAN_NODE_TypeDef::NSR
__IO uint32_t NSR
Definition: XMC4800.h:1998
CAN_MO_TypeDef::MODATAH
__IO uint32_t MODATAH
Definition: XMC4800.h:381
GPDMA0_GLOBAL_TypeDef::RESERVED16
__I uint32_t RESERVED16
Definition: XMC4800.h:580
GPDMA0_CH_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:627
PPB_Type::MPU_RBAR_A3
__IO uint32_t MPU_RBAR_A3
Definition: XMC4800.h:491
PORT0_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2412
SDMMC_GLOBAL_TypeDef::PRESENT_STATE
__I uint32_t PRESENT_STATE
Definition: XMC4800.h:1213
SDMMC_GLOBAL_TypeDef::EN_INT_STATUS_ERR
__IO uint16_t EN_INT_STATUS_ERR
Definition: XMC4800.h:1224
SCU_POWER_TypeDef::EVRSTAT
__I uint32_t EVRSTAT
Definition: XMC4800.h:1119
USB0_GLOBAL_TypeDef::GRXSTSP_HOSTMODE
__I uint32_t GRXSTSP_HOSTMODE
Definition: XMC4800.h:1725
GPDMA1_GLOBAL_TypeDef::MASKDSTTRAN
__IO uint32_t MASKDSTTRAN
Definition: XMC4800.h:704
ETH_GLOBAL_TypeDef::MMC_RECEIVE_INTERRUPT
__I uint32_t MMC_RECEIVE_INTERRUPT
Definition: XMC4800.h:1333
USB0_EP_TypeDef
Universal Serial Bus (USB_EP)
Definition: XMC4800.h:1817
GPDMA0_GLOBAL_TypeDef::REQDSTREG
__IO uint32_t REQDSTREG
Definition: XMC4800.h:591
SCU_RESET_TypeDef::PRSET1
__O uint32_t PRSET1
Definition: XMC4800.h:1143
FCE_KE_TypeDef::CFG
__IO uint32_t CFG
Definition: XMC4800.h:793
SCU_0_IRQn
@ SCU_0_IRQn
Definition: XMC4800.h:79
PORT4_Type
Port 4 (PORT4)
Definition: XMC4800.h:2527
PPB_Type::NVIC_ICPR2
__IO uint32_t NVIC_ICPR2
Definition: XMC4800.h:426
SCU_CLK_TypeDef::CGATSTAT1
__I uint32_t CGATSTAT1
Definition: XMC4800.h:944
CCU4_CC4_TypeDef::SWS
__O uint32_t SWS
Definition: XMC4800.h:2282
CAN_GLOBAL_TypeDef
Controller Area Networks (CAN)
Definition: XMC4800.h:1969
GPDMA1_GLOBAL_TypeDef::CLEARERR
__O uint32_t CLEARERR
Definition: XMC4800.h:716
ETH_GLOBAL_TypeDef::TX_FRAME_COUNT_GOOD_BAD
__I uint32_t TX_FRAME_COUNT_GOOD_BAD
Definition: XMC4800.h:1339
VADC_G_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:2088
GPDMA0_GLOBAL_TypeDef::TYPE
__I uint32_t TYPE
Definition: XMC4800.h:607
GPDMA0_CH_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:623
SDMMC0_0_IRQn
@ SDMMC0_0_IRQn
Definition: XMC4800.h:176
ECAT_Type::REVISION
__I uint8_t REVISION
Definition: XMC4800.h:1508
DSD_CH_TypeDef::OFFM
__IO uint32_t OFFM
Definition: XMC4800.h:2190
USIC1_1_IRQn
@ USIC1_1_IRQn
Definition: XMC4800.h:162
ECAT_Type::AL_STATUS_CODE
__IO uint16_t AL_STATUS_CODE
Definition: XMC4800.h:1546
GPDMA1_CH_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:754
CAN0_1_IRQn
@ CAN0_1_IRQn
Definition: XMC4800.h:148
POSIF1_1_IRQn
@ POSIF1_1_IRQn
Definition: XMC4800.h:146
CCU40_1_IRQn
@ CCU40_1_IRQn
Definition: XMC4800.h:120
USB0_GLOBAL_TypeDef::DIEPTXF4
__IO uint32_t DIEPTXF4
Definition: XMC4800.h:1744
GPDMA0_GLOBAL_TypeDef::RESERVED22
__I uint32_t RESERVED22
Definition: XMC4800.h:592
SCU_PARITY_TypeDef::PMTSR
__IO uint32_t PMTSR
Definition: XMC4800.h:1062
PORT6_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2588
SCU_POWER_TypeDef::PWRMON
__IO uint32_t PWRMON
Definition: XMC4800.h:1122
GPDMA0_GLOBAL_TypeDef::RESERVED7
__I uint32_t RESERVED7
Definition: XMC4800.h:562
CCU42_0_IRQn
@ CCU42_0_IRQn
Definition: XMC4800.h:127
ETH0_0_IRQn
@ ETH0_0_IRQn
Definition: XMC4800.h:178
LEDTS0_GLOBAL_TypeDef::LDCMP1
__IO uint32_t LDCMP1
Definition: XMC4800.h:1172
LEDTS0_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:1164
POSIF_GLOBAL_TypeDef::PRUNS
__O uint32_t PRUNS
Definition: XMC4800.h:2372
SCU_TRAP_TypeDef::TRAPSTAT
__I uint32_t TRAPSTAT
Definition: XMC4800.h:1076
ETH_GLOBAL_TypeDef::TX_OCTET_COUNT_GOOD_BAD
__I uint32_t TX_OCTET_COUNT_GOOD_BAD
Definition: XMC4800.h:1337
USIC_CH_TypeDef::BRG
__IO uint32_t BRG
Definition: XMC4800.h:1908
USB0_EP_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:1838
PPB_Type::SCR
__IO uint32_t SCR
Definition: XMC4800.h:467
ETH_GLOBAL_TypeDef::TRANSMIT_POLL_DEMAND
__IO uint32_t TRANSMIT_POLL_DEMAND
Definition: XMC4800.h:1461
SDMMC_GLOBAL_TypeDef::EN_INT_SIGNAL_NORM
__IO uint16_t EN_INT_SIGNAL_NORM
Definition: XMC4800.h:1225
VADC_G_TypeDef::ASCTRL
__IO uint32_t ASCTRL
Definition: XMC4800.h:2104
EBU_Type::BUSWCON0
__IO uint32_t BUSWCON0
Definition: XMC4800.h:1263
PORT9_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2684
USIC_CH_TypeDef::RBUF1
__I uint32_t RBUF1
Definition: XMC4800.h:1941
ECAT_Type::FWD_RX_ERR_COUNT1
__I uint8_t FWD_RX_ERR_COUNT1
Definition: XMC4800.h:1570
PPB_Type::NVIC_ISPR3
__IO uint32_t NVIC_ISPR3
Definition: XMC4800.h:422
USIC1_4_IRQn
@ USIC1_4_IRQn
Definition: XMC4800.h:165
SCU_CLK_TypeDef::CGATCLR3
__O uint32_t CGATCLR3
Definition: XMC4800.h:952
VADC_G_TypeDef::ARBCFG
__IO uint32_t ARBCFG
Definition: XMC4800.h:2077
VADC_G_TypeDef::ASPND
__IO uint32_t ASPND
Definition: XMC4800.h:2107
ETH_GLOBAL_TypeDef::MMC_IPC_RECEIVE_INTERRUPT
__I uint32_t MMC_IPC_RECEIVE_INTERRUPT
Definition: XMC4800.h:1415
SDMMC_CON_Type
SD and Multimediacard Control Register (SDMMC_CON)
Definition: XMC4800.h:1187
PORT4_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2540
SCU_CLK_TypeDef::CGATCLR2
__O uint32_t CGATCLR2
Definition: XMC4800.h:949
PORT8_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2644
ETH_GLOBAL_TypeDef::RX_UNICAST_FRAMES_GOOD
__I uint32_t RX_UNICAST_FRAMES_GOOD
Definition: XMC4800.h:1403
ETH_GLOBAL_TypeDef::RESERVED9
__I uint32_t RESERVED9
Definition: XMC4800.h:1470
VADC0_G3_3_IRQn
@ VADC0_G3_3_IRQn
Definition: XMC4800.h:108
USB0_EP_TypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: XMC4800.h:1824
ECAT_Type::ESC_WR_ENABLE
__I uint8_t ESC_WR_ENABLE
Definition: XMC4800.h:1522
GPDMA1_GLOBAL_TypeDef::REQDSTREG
__IO uint32_t REQDSTREG
Definition: XMC4800.h:722
SCU_CLK_TypeDef::CLKSET
__O uint32_t CLKSET
Definition: XMC4800.h:926
GPDMA0_GLOBAL_TypeDef::CLEARERR
__O uint32_t CLEARERR
Definition: XMC4800.h:585
PPB_Type::SHPR3
__IO uint32_t SHPR3
Definition: XMC4800.h:471
POSIF_GLOBAL_TypeDef::QDC
__IO uint32_t QDC
Definition: XMC4800.h:2387
POSIF0_1_IRQn
@ POSIF0_1_IRQn
Definition: XMC4800.h:144
SCU_CLK_TypeDef::CPUCLKCR
__IO uint32_t CPUCLKCR
Definition: XMC4800.h:929
ERU0_3_IRQn
@ ERU0_3_IRQn
Definition: XMC4800.h:83
ETH_GLOBAL_TypeDef::RXICMP_ERROR_OCTETS
__I uint32_t RXICMP_ERROR_OCTETS
Definition: XMC4800.h:1446
ETH_GLOBAL_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:1414
DLR_GLOBAL_TypeDef::SRSEL0
__IO uint32_t SRSEL0
Definition: XMC4800.h:514
PORT1_Type::IOCR12
__IO uint32_t IOCR12
Definition: XMC4800.h:2444
CCU8_CC8_TypeDef::TC
__IO uint32_t TC
Definition: XMC4800.h:2328
CCU8_CC8_TypeDef::INTS
__I uint32_t INTS
Definition: XMC4800.h:2349
SDMMC_GLOBAL_TypeDef::TRANSFER_MODE
__IO uint16_t TRANSFER_MODE
Definition: XMC4800.h:1206
GPDMA0_GLOBAL_TypeDef::RESERVED14
__I uint32_t RESERVED14
Definition: XMC4800.h:576
ETH_GLOBAL_TypeDef::SYSTEM_TIME_SECONDS
__I uint32_t SYSTEM_TIME_SECONDS
Definition: XMC4800.h:1450
PPB_Type::NVIC_ICER1
__IO uint32_t NVIC_ICER1
Definition: XMC4800.h:415
SDMMC_GLOBAL_TypeDef::EN_INT_STATUS_NORM
__IO uint16_t EN_INT_STATUS_NORM
Definition: XMC4800.h:1223
ECAT_Type::EVENT_REQ
__I uint16_t EVENT_REQ
Definition: XMC4800.h:1562
SCU_OSC_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:968
CCU8_CC8_TypeDef::CMC
__IO uint32_t CMC
Definition: XMC4800.h:2324
SCU_CLK_TypeDef::DSLEEPCR
__IO uint32_t DSLEEPCR
Definition: XMC4800.h:938
PORT6_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2584
VADC_G_TypeDef::BFLS
__O uint32_t BFLS
Definition: XMC4800.h:2090
PORT3_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2499
RTC_GLOBAL_TypeDef::ATIM1
__IO uint32_t ATIM1
Definition: XMC4800.h:909
ECAT0_CON_Type
EtherCAT 0 Control Register (ECAT0_CON)
Definition: XMC4800.h:1490
VADC_G_TypeDef::RESERVED9
__I uint32_t RESERVED9
Definition: XMC4800.h:2112
POSIF_GLOBAL_TypeDef::PSUS
__IO uint32_t PSUS
Definition: XMC4800.h:2371
PPB_Type::MPU_CTRL
__IO uint32_t MPU_CTRL
Definition: XMC4800.h:483
GPDMA1_GLOBAL_TypeDef::RESERVED26
__I uint32_t RESERVED26
Definition: XMC4800.h:731
USIC_CH_TypeDef::FMR
__O uint32_t FMR
Definition: XMC4800.h:1943
GPDMA0_0_IRQn
@ GPDMA0_0_IRQn
Definition: XMC4800.h:175
USIC_CH_TypeDef::CCFG
__I uint32_t CCFG
Definition: XMC4800.h:1904
CCU8_CC8_TypeDef::DC2R
__IO uint32_t DC2R
Definition: XMC4800.h:2344
PPB_Type::CFSR
__IO uint32_t CFSR
Definition: XMC4800.h:473
ETH_GLOBAL_TypeDef::TX_SINGLE_COLLISION_GOOD_FRAMES
__I uint32_t TX_SINGLE_COLLISION_GOOD_FRAMES
Definition: XMC4800.h:1361
POSIF_GLOBAL_TypeDef::HALPS
__IO uint32_t HALPS
Definition: XMC4800.h:2379
PORT9_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2674
GPDMA0_CH_TypeDef::DSR
__IO uint32_t DSR
Definition: XMC4800.h:642
USB0_GLOBAL_TypeDef::GINTMSK_HOSTMODE
__IO uint32_t GINTMSK_HOSTMODE
Definition: XMC4800.h:1716
USB0_EP_TypeDef::DIEPCTL_INTBULK
__IO uint32_t DIEPCTL_INTBULK
Definition: XMC4800.h:1820
PORT15_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2733
CCU8_CC8_TypeDef::DIT
__I uint32_t DIT
Definition: XMC4800.h:2330
EBU_Type::BUSWAP1
__IO uint32_t BUSWAP1
Definition: XMC4800.h:1268
PPB_Type::NVIC_IABR3
__IO uint32_t NVIC_IABR3
Definition: XMC4800.h:432
ECAT_Type::SYNC_LATCH_CONFIG
__I uint8_t SYNC_LATCH_CONFIG
Definition: XMC4800.h:1555
ETH_GLOBAL_TypeDef::RX_FRAMES_COUNT_GOOD_BAD
__I uint32_t RX_FRAMES_COUNT_GOOD_BAD
Definition: XMC4800.h:1380
GPDMA0_CH2_7_Type::CTLH
__IO uint32_t CTLH
Definition: XMC4800.h:661
GPDMA0_CH_TypeDef
General Purpose DMA Unit 0 (GPDMA0_CH0_1)
Definition: XMC4800.h:621
PORT8_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2652
ETH_GLOBAL_TypeDef::RX_UNDERSIZE_FRAMES_GOOD
__I uint32_t RX_UNDERSIZE_FRAMES_GOOD
Definition: XMC4800.h:1389
ECAT_Type::MII_PDI_ACS_STATE
__IO uint8_t MII_PDI_ACS_STATE
Definition: XMC4800.h:1598
ETH_GLOBAL_TypeDef::RX_BROADCAST_FRAMES_GOOD
__I uint32_t RX_BROADCAST_FRAMES_GOOD
Definition: XMC4800.h:1383
USIC_CH_TypeDef::KSCFG
__IO uint32_t KSCFG
Definition: XMC4800.h:1906
ETH_GLOBAL_TypeDef::TIMESTAMP_ADDEND
__IO uint32_t TIMESTAMP_ADDEND
Definition: XMC4800.h:1454
PORT15_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2729
VADC_G_TypeDef::QBUR0
__I uint32_t QBUR0
Definition: XMC4800.h:2100
GPDMA0_GLOBAL_TypeDef::RAWBLOCK
__IO uint32_t RAWBLOCK
Definition: XMC4800.h:549
SCU_PLL_TypeDef::USBPLLCON
__IO uint32_t USBPLLCON
Definition: XMC4800.h:988
PPB_Type::AIRCR
__IO uint32_t AIRCR
Definition: XMC4800.h:466
USB0_GLOBAL_TypeDef::DIEPTXF5
__IO uint32_t DIEPTXF5
Definition: XMC4800.h:1745
PPB_Type::NVIC_IPR9
__IO uint32_t NVIC_IPR9
Definition: XMC4800.h:443
USB0_EP0_TypeDef::DIEPCTL0
__IO uint32_t DIEPCTL0
Definition: XMC4800.h:1788
VADC_GLOBAL_TypeDef::GLOBCFG
__IO uint32_t GLOBCFG
Definition: XMC4800.h:2037
PORT2_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2469
ETH_GLOBAL_TypeDef::TIMESTAMP_STATUS
__I uint32_t TIMESTAMP_STATUS
Definition: XMC4800.h:1458
PORT3_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2501
ETH_GLOBAL_TypeDef::TX_VLAN_FRAMES_GOOD
__I uint32_t TX_VLAN_FRAMES_GOOD
Definition: XMC4800.h:1377
SDMMC_GLOBAL_TypeDef::SLOT_INT_STATUS
__I uint16_t SLOT_INT_STATUS
Definition: XMC4800.h:1238
ECAT_Type::RESERVED14
__I uint16_t RESERVED14
Definition: XMC4800.h:1559
PPB_Type::NVIC_IPR12
__IO uint32_t NVIC_IPR12
Definition: XMC4800.h:446
PORT4_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2541
CCU42_2_IRQn
@ CCU42_2_IRQn
Definition: XMC4800.h:129
ECAT0_0_IRQn
@ ECAT0_0_IRQn
Definition: XMC4800.h:179
USB0_GLOBAL_TypeDef::GDFIFOCFG
__IO uint32_t GDFIFOCFG
Definition: XMC4800.h:1738
GPDMA1_GLOBAL_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:687
VADC0_G3_2_IRQn
@ VADC0_G3_2_IRQn
Definition: XMC4800.h:107
SCU_INTERRUPT_TypeDef::SRCLR
__O uint32_t SRCLR
Definition: XMC4800.h:1039
ECAT_Type::DC_SPEED_COUNT_START
__IO uint16_t DC_SPEED_COUNT_START
Definition: XMC4800.h:1612
DSD_GLOBAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:2151
USB0_EP0_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:1791
USIC_CH_TypeDef::DX5CR
__IO uint32_t DX5CR
Definition: XMC4800.h:1915
ETH_GLOBAL_TypeDef::RX_LENGTH_ERROR_FRAMES
__I uint32_t RX_LENGTH_ERROR_FRAMES
Definition: XMC4800.h:1404
DAC_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:2212
USB0_EP_TypeDef::DOEPDMAB
__I uint32_t DOEPDMAB
Definition: XMC4800.h:1846
ECAT_Type::RESERVED18
__I uint32_t RESERVED18
Definition: XMC4800.h:1568
GPDMA0_GLOBAL_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:552
ETH_GLOBAL_TypeDef::RXIPV6_NO_PAYLOAD_OCTETS
__I uint32_t RXIPV6_NO_PAYLOAD_OCTETS
Definition: XMC4800.h:1440
ETH_GLOBAL_TypeDef::RX_OVERSIZE_FRAMES_GOOD
__I uint32_t RX_OVERSIZE_FRAMES_GOOD
Definition: XMC4800.h:1390
DSD0_A_7_IRQn
@ DSD0_A_7_IRQn
Definition: XMC4800.h:116
GPDMA1_CH_TypeDef::CTLH
__IO uint32_t CTLH
Definition: XMC4800.h:758
CCU4_CC4_TypeDef::DIT
__I uint32_t DIT
Definition: XMC4800.h:2266
CCU8_GLOBAL_TypeDef
Capture Compare Unit 8 - Unit 0 (CCU8)
Definition: XMC4800.h:2299
ECAT_Type::DC_PULSE_LEN
__I uint16_t DC_PULSE_LEN
Definition: XMC4800.h:1619
CCU4_CC4_TypeDef::TCST
__I uint32_t TCST
Definition: XMC4800.h:2261
USB0_EP_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1823
VADC_G_TypeDef::CHASS
__IO uint32_t CHASS
Definition: XMC4800.h:2079
PORT7_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2616
GPDMA0_GLOBAL_TypeDef::RESERVED13
__I uint32_t RESERVED13
Definition: XMC4800.h:574
GPDMA0_GLOBAL_TypeDef::RESERVED11
__I uint32_t RESERVED11
Definition: XMC4800.h:570
CAN_NODE_TypeDef::NPCR
__IO uint32_t NPCR
Definition: XMC4800.h:2000
USB0_CH_TypeDef::HCTSIZ_SCATGATHER
__IO uint32_t HCTSIZ_SCATGATHER
Definition: XMC4800.h:1866
ECAT_Type::EEP_CONF
__I uint8_t EEP_CONF
Definition: XMC4800.h:1588
GPDMA0_GLOBAL_TypeDef::RESERVED6
__I uint32_t RESERVED6
Definition: XMC4800.h:560
ECAT0_FMMU_Type::FMMU_L_STOP_BIT
__I uint8_t FMMU_L_STOP_BIT
Definition: XMC4800.h:1666
CCU8_GLOBAL_TypeDef::MIDR
__I uint32_t MIDR
Definition: XMC4800.h:2309
GPDMA0_CH_TypeDef::SGR
__IO uint32_t SGR
Definition: XMC4800.h:640
SCU_POWER_TypeDef::PWRCLR
__O uint32_t PWRCLR
Definition: XMC4800.h:1117
ETH_GLOBAL_TypeDef::TX_BROADCAST_FRAMES_GOOD_BAD
__I uint32_t TX_BROADCAST_FRAMES_GOOD_BAD
Definition: XMC4800.h:1358
SCU_POWER_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1118
CCU8_GLOBAL_TypeDef::GIDLS
__O uint32_t GIDLS
Definition: XMC4800.h:2302
SCU_CLK_TypeDef::CLKCLR
__O uint32_t CLKCLR
Definition: XMC4800.h:927
ETH_GLOBAL_TypeDef::TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
__I uint32_t TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1352
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: XMC4800.h:75
USB0_GLOBAL_TypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: XMC4800.h:1740
CAN_NODE_TypeDef
Controller Area Networks (CAN_NODE)
Definition: XMC4800.h:1996
USIC_CH_TypeDef::RBUF0
__I uint32_t RBUF0
Definition: XMC4800.h:1940
PPB_Type::NVIC_IPR10
__IO uint32_t NVIC_IPR10
Definition: XMC4800.h:444
GPDMA0_CH_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:631
DSD_GLOBAL_TypeDef::EVFLAGCLR
__O uint32_t EVFLAGCLR
Definition: XMC4800.h:2163
VADC_G_TypeDef::SRACT
__O uint32_t SRACT
Definition: XMC4800.h:2124
ECAT_Type::RESERVED10
__I uint16_t RESERVED10
Definition: XMC4800.h:1547
PPB_Type::NVIC_IPR22
__IO uint32_t NVIC_IPR22
Definition: XMC4800.h:456
USB0_GLOBAL_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:1751
PPB_Type::MPU_RBAR
__IO uint32_t MPU_RBAR
Definition: XMC4800.h:485
ECAT_Type::DC_SPEED_COUNT_DIFF
__I uint16_t DC_SPEED_COUNT_DIFF
Definition: XMC4800.h:1613
SCU_RESET_TypeDef::RSTSET
__O uint32_t RSTSET
Definition: XMC4800.h:1137
ETH_GLOBAL_TypeDef::RX_512TO1023OCTETS_FRAMES_GOOD_BAD
__I uint32_t RX_512TO1023OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1399
PPB_Type::SHPR2
__IO uint32_t SHPR2
Definition: XMC4800.h:470
DAC_GLOBAL_TypeDef::DAC1PATL
__IO uint32_t DAC1PATL
Definition: XMC4800.h:2222
GPDMA0_CH2_7_Type::CFGH
__IO uint32_t CFGH
Definition: XMC4800.h:664
ETH_GLOBAL_TypeDef::MAC_ADDRESS1_HIGH
__IO uint32_t MAC_ADDRESS1_HIGH
Definition: XMC4800.h:1325
SDMMC_GLOBAL_TypeDef::FORCE_EVENT_ERR_STATUS
__O uint16_t FORCE_EVENT_ERR_STATUS
Definition: XMC4800.h:1234
SDMMC_GLOBAL_TypeDef::COMMAND
__IO uint16_t COMMAND
Definition: XMC4800.h:1207
SCU_GENERAL_TypeDef::RMACR
__IO uint32_t RMACR
Definition: XMC4800.h:1021
CCU4_CC4_TypeDef::PSC
__IO uint32_t PSC
Definition: XMC4800.h:2268
ECAT_Type::DC_ACT_STAT
__I uint8_t DC_ACT_STAT
Definition: XMC4800.h:1620
GPDMA0_GLOBAL_TypeDef::RESERVED19
__I uint32_t RESERVED19
Definition: XMC4800.h:586
PORT9_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2669
ECAT0_FMMU_Type::FMMU_P_START_ADR
__I uint16_t FMMU_P_START_ADR
Definition: XMC4800.h:1667
USIC2_3_IRQn
@ USIC2_3_IRQn
Definition: XMC4800.h:170
FCE_GLOBAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:776
ETH_GLOBAL_TypeDef::TX_128TO255OCTETS_FRAMES_GOOD_BAD
__I uint32_t TX_128TO255OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1346
ECAT_Type::WD_STAT_PDATA
__I uint16_t WD_STAT_PDATA
Definition: XMC4800.h:1584
ETH_GLOBAL_TypeDef::RXTCP_GOOD_FRAMES
__I uint32_t RXTCP_GOOD_FRAMES
Definition: XMC4800.h:1428
ETH_GLOBAL_TypeDef::RX_CRC_ERROR_FRAMES
__I uint32_t RX_CRC_ERROR_FRAMES
Definition: XMC4800.h:1385
PORT14_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2702
ETH_GLOBAL_TypeDef::DEBUG
__I uint32_t DEBUG
Definition: XMC4800.h:1317
ECAT_Type::DC_LATCH0_CONT
__IO uint8_t DC_LATCH0_CONT
Definition: XMC4800.h:1628
USB0_GLOBAL_TypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: XMC4800.h:1768
GPDMA1_GLOBAL_TypeDef::DMACFGREG
__IO uint32_t DMACFGREG
Definition: XMC4800.h:732
PORT2_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2481
FLASH0_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:828
ECAT_Type::WD_COUNT_PDI
__I uint8_t WD_COUNT_PDI
Definition: XMC4800.h:1586
PPB_Type::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:403
WDT_GLOBAL_TypeDef::WLB
__IO uint32_t WLB
Definition: XMC4800.h:885
DAC_GLOBAL_TypeDef::DAC0CFG1
__IO uint32_t DAC0CFG1
Definition: XMC4800.h:2214
USIC_CH_TypeDef::PSR
__IO uint32_t PSR
Definition: XMC4800.h:1933
CCU4_CC4_TypeDef::CRS
__IO uint32_t CRS
Definition: XMC4800.h:2274
ECAT_Type::FEATURE
__I uint16_t FEATURE
Definition: XMC4800.h:1514
ETH_GLOBAL_TypeDef::TX_LATE_COLLISION_FRAMES
__I uint32_t TX_LATE_COLLISION_FRAMES
Definition: XMC4800.h:1366
CAN0_5_IRQn
@ CAN0_5_IRQn
Definition: XMC4800.h:152
SCU_CLK_TypeDef::CCUCLKCR
__IO uint32_t CCUCLKCR
Definition: XMC4800.h:933
USB0_0_IRQn
@ USB0_0_IRQn
Definition: XMC4800.h:177
CCU8_GLOBAL_TypeDef::GCSC
__O uint32_t GCSC
Definition: XMC4800.h:2305
PPB_Type::NVIC_ISER0
__IO uint32_t NVIC_ISER0
Definition: XMC4800.h:409
USIC_CH_TypeDef::BYPCR
__IO uint32_t BYPCR
Definition: XMC4800.h:1947
DLR_GLOBAL_TypeDef::OVRCLR
__O uint32_t OVRCLR
Definition: XMC4800.h:513
ECAT_Type::RAM_SIZE
__I uint8_t RAM_SIZE
Definition: XMC4800.h:1512
CCU4_CC4_TypeDef::CMC
__IO uint32_t CMC
Definition: XMC4800.h:2260
ETH_GLOBAL_TypeDef::HW_FEATURE
__IO uint32_t HW_FEATURE
Definition: XMC4800.h:1477
PPB_Type::NVIC_IPR15
__IO uint32_t NVIC_IPR15
Definition: XMC4800.h:449
USIC_CH_TypeDef::DX2CR
__IO uint32_t DX2CR
Definition: XMC4800.h:1912
ECAT_Type::WD_DIVIDE
__IO uint16_t WD_DIVIDE
Definition: XMC4800.h:1578
ETH_GLOBAL_TypeDef::MMC_IPC_RECEIVE_INTERRUPT_MASK
__IO uint32_t MMC_IPC_RECEIVE_INTERRUPT_MASK
Definition: XMC4800.h:1413
SCU_CLK_TypeDef::CGATSET3
__O uint32_t CGATSET3
Definition: XMC4800.h:951
SCU_GENERAL_TypeDef::SDMMCDEL
__IO uint32_t SDMMCDEL
Definition: XMC4800.h:1017
DAC_GLOBAL_TypeDef::DAC1DATA
__IO uint32_t DAC1DATA
Definition: XMC4800.h:2218
VADC_G_TypeDef::SEFCLR
__O uint32_t SEFCLR
Definition: XMC4800.h:2115
VADC0_G3_0_IRQn
@ VADC0_G3_0_IRQn
Definition: XMC4800.h:105
IRQn_Type
IRQn_Type
Definition: XMC4800.h:64
SCU_POWER_TypeDef::PWRSET
__O uint32_t PWRSET
Definition: XMC4800.h:1116
PORT6_Type
Port 6 (PORT6)
Definition: XMC4800.h:2583
LEDTS0_GLOBAL_TypeDef::LINE0
__IO uint32_t LINE0
Definition: XMC4800.h:1169
GPDMA1_GLOBAL_TypeDef::STATUSSRCTRAN
__I uint32_t STATUSSRCTRAN
Definition: XMC4800.h:692
GPDMA1_GLOBAL_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:689
ETH_GLOBAL_TypeDef::TX_64OCTETS_FRAMES_GOOD_BAD
__I uint32_t TX_64OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1342
SCU_PLL_TypeDef
System Control Unit (SCU_PLL)
Definition: XMC4800.h:982
USIC_CH_TypeDef::PSCR
__O uint32_t PSCR
Definition: XMC4800.h:1936
USIC_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:1889
DAC_GLOBAL_TypeDef::DAC0DATA
__IO uint32_t DAC0DATA
Definition: XMC4800.h:2217
ECAT_Type::PORT_DESC
__I uint8_t PORT_DESC
Definition: XMC4800.h:1513
PPB_Type
Cortex-M4 Private Peripheral Block (PPB)
Definition: XMC4800.h:400
USB0_GLOBAL_TypeDef::GNPTXFSIZ_DEVICEMODE
__IO uint32_t GNPTXFSIZ_DEVICEMODE
Definition: XMC4800.h:1731
ETH0_CON_GLOBAL_TypeDef::CON
__IO uint32_t CON
Definition: XMC4800.h:1294
DSD0_A_4_IRQn
@ DSD0_A_4_IRQn
Definition: XMC4800.h:113
GPDMA0_CH2_7_Type::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:657
GPDMA1_GLOBAL_TypeDef::RESERVED7
__I uint32_t RESERVED7
Definition: XMC4800.h:693
PORT2_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2468
ECAT0_SM_Type
EtherCAT 0 (ECAT0_SM)
Definition: XMC4800.h:1683
SDMMC_GLOBAL_TypeDef::RESPONSE2
__I uint32_t RESPONSE2
Definition: XMC4800.h:1209
SCU_GENERAL_TypeDef::CCUCON
__IO uint32_t CCUCON
Definition: XMC4800.h:1012
ETH_GLOBAL_TypeDef::RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS
__I uint32_t RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS
Definition: XMC4800.h:1437
PPB_Type::NVIC_IPR3
__IO uint32_t NVIC_IPR3
Definition: XMC4800.h:437
USB0_EP0_TypeDef::DTXFSTS0
__I uint32_t DTXFSTS0
Definition: XMC4800.h:1794
DSD_CH_TypeDef::FCFGA
__IO uint32_t FCFGA
Definition: XMC4800.h:2182
USB0_EP0_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:1803
SCU_HIBERNATE_TypeDef::HDCR
__IO uint32_t HDCR
Definition: XMC4800.h:1097
VADC0_G2_0_IRQn
@ VADC0_G2_0_IRQn
Definition: XMC4800.h:101
ETH_GLOBAL_TypeDef::SUB_SECOND_INCREMENT
__IO uint32_t SUB_SECOND_INCREMENT
Definition: XMC4800.h:1449
SCU_INTERRUPT_TypeDef::SRMSK
__IO uint32_t SRMSK
Definition: XMC4800.h:1038
PPB_Type::AFSR
__IO uint32_t AFSR
Definition: XMC4800.h:478
CCU8_GLOBAL_TypeDef::GSTAT
__I uint32_t GSTAT
Definition: XMC4800.h:2301
PORT5_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2558
ECAT_Type::FMMU_NUM
__I uint8_t FMMU_NUM
Definition: XMC4800.h:1510
ETH_GLOBAL_TypeDef::RXUDP_GOOD_OCTETS
__I uint32_t RXUDP_GOOD_OCTETS
Definition: XMC4800.h:1441
GPDMA1_GLOBAL_TypeDef::RESERVED28
__I uint32_t RESERVED28
Definition: XMC4800.h:735
ECAT_Type::DC_SYS_TIME_FIL_DEPTH
__IO uint8_t DC_SYS_TIME_FIL_DEPTH
Definition: XMC4800.h:1614
ETH_GLOBAL_TypeDef::RXICMP_GOOD_OCTETS
__I uint32_t RXICMP_GOOD_OCTETS
Definition: XMC4800.h:1445
POSIF0_0_IRQn
@ POSIF0_0_IRQn
Definition: XMC4800.h:143
ECAT_Type::RESERVED9
__I uint16_t RESERVED9
Definition: XMC4800.h:1545
VADC_G_TypeDef::RESERVED15
__I uint32_t RESERVED15
Definition: XMC4800.h:2127
PORT6_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2585
PORT1_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2442
SCU_PLL_TypeDef::USBPLLSTAT
__I uint32_t USBPLLSTAT
Definition: XMC4800.h:987
ETH_GLOBAL_TypeDef::RX_PAUSE_FRAMES
__I uint32_t RX_PAUSE_FRAMES
Definition: XMC4800.h:1406
ECAT_Type::DC_SYNC0_CYC_TIME
__IO uint32_t DC_SYNC0_CYC_TIME
Definition: XMC4800.h:1626
GPDMA1_GLOBAL_TypeDef::MASKERR
__IO uint32_t MASKERR
Definition: XMC4800.h:706
GPDMA0_CH_TypeDef::CFGH
__IO uint32_t CFGH
Definition: XMC4800.h:639
GPDMA0_CH_TypeDef::LLP
__IO uint32_t LLP
Definition: XMC4800.h:626
GPDMA0_GLOBAL_TypeDef::VERSION
__I uint32_t VERSION
Definition: XMC4800.h:608
PORT2_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2478
CCU4_GLOBAL_TypeDef::GCSC
__O uint32_t GCSC
Definition: XMC4800.h:2242
GPDMA1_GLOBAL_TypeDef::MASKTFR
__IO uint32_t MASKTFR
Definition: XMC4800.h:698
GPDMA1_GLOBAL_TypeDef::RESERVED20
__I uint32_t RESERVED20
Definition: XMC4800.h:719
DAC_GLOBAL_TypeDef::DAC01DATA
__IO uint32_t DAC01DATA
Definition: XMC4800.h:2219
ECAT_Type::WR_REG_PROTECT
__I uint8_t WR_REG_PROTECT
Definition: XMC4800.h:1520
ETH_GLOBAL_TypeDef::MAC_ADDRESS2_HIGH
__IO uint32_t MAC_ADDRESS2_HIGH
Definition: XMC4800.h:1327
ETH_GLOBAL_TypeDef::TX_256TO511OCTETS_FRAMES_GOOD_BAD
__I uint32_t TX_256TO511OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1348
FCE_KE_TypeDef::STS
__IO uint32_t STS
Definition: XMC4800.h:794
ETH_GLOBAL_TypeDef::TX_UNDERFLOW_ERROR_FRAMES
__I uint32_t TX_UNDERFLOW_ERROR_FRAMES
Definition: XMC4800.h:1360
USB0_EP0_TypeDef::DIEPDMA0
__IO uint32_t DIEPDMA0
Definition: XMC4800.h:1793
SCU_PLL_TypeDef::PLLSTAT
__I uint32_t PLLSTAT
Definition: XMC4800.h:983
ETH_GLOBAL_TypeDef::MMC_TRANSMIT_INTERRUPT_MASK
__IO uint32_t MMC_TRANSMIT_INTERRUPT_MASK
Definition: XMC4800.h:1336
PPB_Type::NVIC_IPR27
__IO uint32_t NVIC_IPR27
Definition: XMC4800.h:461
ECAT_Type::DC_PDI_CNG_EV_TIME
__I uint32_t DC_PDI_CNG_EV_TIME
Definition: XMC4800.h:1645
USIC0_1_IRQn
@ USIC0_1_IRQn
Definition: XMC4800.h:156
PPB_Type::BFAR
__IO uint32_t BFAR
Definition: XMC4800.h:477
ECAT_Type::STATION_ALIAS
__IO uint16_t STATION_ALIAS
Definition: XMC4800.h:1517
ETH_GLOBAL_TypeDef::PMT_CONTROL_STATUS
__IO uint32_t PMT_CONTROL_STATUS
Definition: XMC4800.h:1319
ECAT_Type::DC_PDI_START_EV_TIME
__I uint32_t DC_PDI_START_EV_TIME
Definition: XMC4800.h:1644
PORT3_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2511
ETH_GLOBAL_TypeDef::MMC_TRANSMIT_INTERRUPT
__I uint32_t MMC_TRANSMIT_INTERRUPT
Definition: XMC4800.h:1334
USIC_CH_TypeDef::TRBSCR
__O uint32_t TRBSCR
Definition: XMC4800.h:1952
USIC_CH_TypeDef::TRBSR
__IO uint32_t TRBSR
Definition: XMC4800.h:1951
POSIF_GLOBAL_TypeDef::MCM
__I uint32_t MCM
Definition: XMC4800.h:2381
SCU_OSC_TypeDef
System Control Unit (SCU_OSC)
Definition: XMC4800.h:965
GPDMA0_CH_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:625
PPB_Type::NVIC_IPR6
__IO uint32_t NVIC_IPR6
Definition: XMC4800.h:440
PPB_Type::CPUID
__I uint32_t CPUID
Definition: XMC4800.h:463
SCU_PLL_TypeDef::PLLCON0
__IO uint32_t PLLCON0
Definition: XMC4800.h:984
PORT7_Type
Port 7 (PORT7)
Definition: XMC4800.h:2610
ETH_GLOBAL_TypeDef::RXIPV4_HEADER_ERROR_FRAMES
__I uint32_t RXIPV4_HEADER_ERROR_FRAMES
Definition: XMC4800.h:1418
VADC_GLOBAL_TypeDef::GLOBTF
__IO uint32_t GLOBTF
Definition: XMC4800.h:2047
ECAT_Type::MII_PHY_ADR
__IO uint8_t MII_PHY_ADR
Definition: XMC4800.h:1594
DSD0_M_2_IRQn
@ DSD0_M_2_IRQn
Definition: XMC4800.h:111
PPB_Type::NVIC_ISER1
__IO uint32_t NVIC_ISER1
Definition: XMC4800.h:410
PORT1_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2439
PORT5_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2555
PORT3_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2506
USB0_GLOBAL_TypeDef::DAINT
__I uint32_t DAINT
Definition: XMC4800.h:1765
GPDMA0_CH_TypeDef::RESERVED6
__I uint32_t RESERVED6
Definition: XMC4800.h:637
ETH_GLOBAL_TypeDef::TX_BROADCAST_FRAMES_GOOD
__I uint32_t TX_BROADCAST_FRAMES_GOOD
Definition: XMC4800.h:1340
VADC_G_TypeDef::CEFLAG
__IO uint32_t CEFLAG
Definition: XMC4800.h:2109
VADC_G_TypeDef::QCTRL0
__IO uint32_t QCTRL0
Definition: XMC4800.h:2094
PORT0_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2418
VADC_G_TypeDef::BFL
__IO uint32_t BFL
Definition: XMC4800.h:2089
CCU40_3_IRQn
@ CCU40_3_IRQn
Definition: XMC4800.h:122
ECAT_Type::ESC_CONFIG
__I uint8_t ESC_CONFIG
Definition: XMC4800.h:1552
SCU_PARITY_TypeDef::PERSTEN
__IO uint32_t PERSTEN
Definition: XMC4800.h:1058
ECAT_Type::WD_TIME_PDATA
__IO uint16_t WD_TIME_PDATA
Definition: XMC4800.h:1582
GPDMA0_GLOBAL_TypeDef::MASKBLOCK
__IO uint32_t MASKBLOCK
Definition: XMC4800.h:569
SCU_HIBERNATE_TypeDef::HDCLR
__O uint32_t HDCLR
Definition: XMC4800.h:1095
GPDMA1_GLOBAL_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:685
GPDMA0_GLOBAL_TypeDef::STATUSINT
__I uint32_t STATUSINT
Definition: XMC4800.h:587
EBU_Type::ADDRSEL0
__IO uint32_t ADDRSEL0
Definition: XMC4800.h:1257
FCE_GLOBAL_TypeDef::CLC
__IO uint32_t CLC
Definition: XMC4800.h:775
USIC_CH_TypeDef::CCR
__IO uint32_t CCR
Definition: XMC4800.h:1926
PORT14_Type::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:2705
GPDMA1_GLOBAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:679
PORT0_Type::IOCR12
__IO uint32_t IOCR12
Definition: XMC4800.h:2414
ETH_GLOBAL_TypeDef::GMII_DATA
__IO uint32_t GMII_DATA
Definition: XMC4800.h:1313
GPDMA1_GLOBAL_TypeDef::RAWERR
__IO uint32_t RAWERR
Definition: XMC4800.h:686
USB0_CH_TypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: XMC4800.h:1860
SCU_CLK_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:940
PORT8_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2647
SCU_PLL_TypeDef::CLKMXSTAT
__I uint32_t CLKMXSTAT
Definition: XMC4800.h:990
PORT8_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2649
ETH_GLOBAL_TypeDef::RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES
__I uint32_t RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES
Definition: XMC4800.h:1421
DAC_GLOBAL_TypeDef::DAC0PATL
__IO uint32_t DAC0PATL
Definition: XMC4800.h:2220
ETH_GLOBAL_TypeDef::OPERATION_MODE
__IO uint32_t OPERATION_MODE
Definition: XMC4800.h:1466
CCU8_CC8_TypeDef::DTC
__IO uint32_t DTC
Definition: XMC4800.h:2342
USB0_GLOBAL_TypeDef::GUID
__IO uint32_t GUID
Definition: XMC4800.h:1736
USB0_EP_TypeDef::DOEPCTL_INTBULK
__IO uint32_t DOEPCTL_INTBULK
Definition: XMC4800.h:1833
ECAT_Type::DC_ACT
__IO uint8_t DC_ACT
Definition: XMC4800.h:1618
ETH_GLOBAL_TypeDef::CURRENT_HOST_TRANSMIT_DESCRIPTOR
__I uint32_t CURRENT_HOST_TRANSMIT_DESCRIPTOR
Definition: XMC4800.h:1473
DSD_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:2152
DSD_CH_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:2185
FCE_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:777
CCU8_CC8_TypeDef::PRS
__IO uint32_t PRS
Definition: XMC4800.h:2336
LEDTS0_GLOBAL_TypeDef::TSCMP1
__IO uint32_t TSCMP1
Definition: XMC4800.h:1174
CCU4_CC4_TypeDef::ECRD0
__I uint32_t ECRD0
Definition: XMC4800.h:2285
SCU_GENERAL_TypeDef::IDCHIP
__I uint32_t IDCHIP
Definition: XMC4800.h:1005
ETH_GLOBAL_TypeDef::RXIPV4_FRAGMENTED_OCTETS
__I uint32_t RXIPV4_FRAGMENTED_OCTETS
Definition: XMC4800.h:1436
PORT9_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2683
GPDMA1_GLOBAL_TypeDef::RESERVED24
__I uint32_t RESERVED24
Definition: XMC4800.h:727
WDT_GLOBAL_TypeDef::CTR
__IO uint32_t CTR
Definition: XMC4800.h:882
PORT4_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2532
CCU41_3_IRQn
@ CCU41_3_IRQn
Definition: XMC4800.h:126
CCU4_GLOBAL_TypeDef::GCST
__I uint32_t GCST
Definition: XMC4800.h:2243
ETH_GLOBAL_TypeDef::MAC_CONFIGURATION
__IO uint32_t MAC_CONFIGURATION
Definition: XMC4800.h:1308
ERU1_1_IRQn
@ ERU1_1_IRQn
Definition: XMC4800.h:85
CCU43_3_IRQn
@ CCU43_3_IRQn
Definition: XMC4800.h:134
ECAT_Type::PDI_CONTROL
__I uint8_t PDI_CONTROL
Definition: XMC4800.h:1551
ECAT_Type::WR_REG_ENABLE
__I uint8_t WR_REG_ENABLE
Definition: XMC4800.h:1519
ECAT0_SM_Type::SM_ACT
__I uint8_t SM_ACT
Definition: XMC4800.h:1688
CCU4_CC4_TypeDef::TCSET
__O uint32_t TCSET
Definition: XMC4800.h:2262
CAN_GLOBAL_TypeDef::CLC
__IO uint32_t CLC
Definition: XMC4800.h:1970
ECAT_Type::DC_SYS_TIME_DELAY
__IO uint32_t DC_SYS_TIME_DELAY
Definition: XMC4800.h:1610
PORT0_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2409
GPDMA0_GLOBAL_TypeDef::MASKDSTTRAN
__IO uint32_t MASKDSTTRAN
Definition: XMC4800.h:573
ECAT_Type::RESERVED32
__I uint32_t RESERVED32
Definition: XMC4800.h:1643
PORT9_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2676
POSIF_GLOBAL_TypeDef
Position Interface 0 (POSIF)
Definition: XMC4800.h:2369
GPDMA1_CH_TypeDef::SAR
__IO uint32_t SAR
Definition: XMC4800.h:753
PORT0_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2423
ETH_GLOBAL_TypeDef::MMC_RECEIVE_INTERRUPT_MASK
__IO uint32_t MMC_RECEIVE_INTERRUPT_MASK
Definition: XMC4800.h:1335
ETH_GLOBAL_TypeDef::CURRENT_HOST_RECEIVE_DESCRIPTOR
__I uint32_t CURRENT_HOST_RECEIVE_DESCRIPTOR
Definition: XMC4800.h:1474
EBU_Type::BUSRCON3
__IO uint32_t BUSRCON3
Definition: XMC4800.h:1273
GPDMA1_GLOBAL_TypeDef::RESERVED23
__I uint32_t RESERVED23
Definition: XMC4800.h:725
USB0_GLOBAL_TypeDef::GRXSTSR_HOSTMODE
__I uint32_t GRXSTSR_HOSTMODE
Definition: XMC4800.h:1721
GPDMA1_GLOBAL_TypeDef::RESERVED12
__I uint32_t RESERVED12
Definition: XMC4800.h:703
USB0_EP0_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1789
ETH_GLOBAL_TypeDef::INTERRUPT_ENABLE
__IO uint32_t INTERRUPT_ENABLE
Definition: XMC4800.h:1467
PORT2_Type::IOCR4
__IO uint32_t IOCR4
Definition: XMC4800.h:2472
GPDMA0_GLOBAL_TypeDef
General Purpose DMA Unit 0 (GPDMA0)
Definition: XMC4800.h:546
POSIF_GLOBAL_TypeDef::MCMC
__O uint32_t MCMC
Definition: XMC4800.h:2384
FCE_KE_TypeDef::CHECK
__IO uint32_t CHECK
Definition: XMC4800.h:796
USB0_GLOBAL_TypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: XMC4800.h:1707
FLASH0_GLOBAL_TypeDef::PROCON0
__I uint32_t PROCON0
Definition: XMC4800.h:834
ETH_GLOBAL_TypeDef::MAC_ADDRESS3_LOW
__IO uint32_t MAC_ADDRESS3_LOW
Definition: XMC4800.h:1330
VADC_G_TypeDef::CEFCLR
__O uint32_t CEFCLR
Definition: XMC4800.h:2113
GPDMA1_GLOBAL_TypeDef::VERSION
__I uint32_t VERSION
Definition: XMC4800.h:739
GPDMA1_GLOBAL_TypeDef::SGLREQDSTREG
__IO uint32_t SGLREQDSTREG
Definition: XMC4800.h:726
RTC_GLOBAL_TypeDef
Real Time Clock (RTC)
Definition: XMC4800.h:901
SCU_POWER_TypeDef::PWRSTAT
__I uint32_t PWRSTAT
Definition: XMC4800.h:1115
DSD_GLOBAL_TypeDef::GLOBRC
__IO uint32_t GLOBRC
Definition: XMC4800.h:2158
PORT8_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2640
GPDMA0_GLOBAL_TypeDef::RESERVED9
__I uint32_t RESERVED9
Definition: XMC4800.h:566
PORT0_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2424
ETH_GLOBAL_TypeDef::RXIPV4_GOOD_OCTETS
__I uint32_t RXIPV4_GOOD_OCTETS
Definition: XMC4800.h:1433
GPDMA1_GLOBAL_TypeDef::RESERVED13
__I uint32_t RESERVED13
Definition: XMC4800.h:705
ECAT_Type::DC_SYNC0_STAT
__I uint8_t DC_SYNC0_STAT
Definition: XMC4800.h:1622
USB0_EP0_TypeDef::RESERVED4
__I uint32_t RESERVED4
Definition: XMC4800.h:1800
ETH_GLOBAL_TypeDef::TX_EXCESSIVE_DEFERRAL_ERROR
__I uint32_t TX_EXCESSIVE_DEFERRAL_ERROR
Definition: XMC4800.h:1374
PORT2_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2483
VADC_G_TypeDef::ARBPR
__IO uint32_t ARBPR
Definition: XMC4800.h:2078
USB0_CH_TypeDef
Universal Serial Bus (USB_CH)
Definition: XMC4800.h:1859
ERU1_0_IRQn
@ ERU1_0_IRQn
Definition: XMC4800.h:84
PORT2_Type
Port 2 (PORT2)
Definition: XMC4800.h:2467
VADC0_G3_1_IRQn
@ VADC0_G3_1_IRQn
Definition: XMC4800.h:106
GPDMA0_GLOBAL_TypeDef::SGLREQSRCREG
__IO uint32_t SGLREQSRCREG
Definition: XMC4800.h:593
PORT5_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2569
ECAT0_FMMU_Type::FMMU_P_START_BIT
__I uint8_t FMMU_P_START_BIT
Definition: XMC4800.h:1668
PPB_Type::SYST_CVR
__IO uint32_t SYST_CVR
Definition: XMC4800.h:406
SCU_CLK_TypeDef::CLKSTAT
__I uint32_t CLKSTAT
Definition: XMC4800.h:925
PORT4_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2529
GPDMA1_GLOBAL_TypeDef::STATUSBLOCK
__I uint32_t STATUSBLOCK
Definition: XMC4800.h:690
PPB_Type::NVIC_IPR25
__IO uint32_t NVIC_IPR25
Definition: XMC4800.h:459
EBU_Type::BUSRAP2
__IO uint32_t BUSRAP2
Definition: XMC4800.h:1270
ECAT_Type::MII_ECAT_ACS_STATE
__I uint8_t MII_ECAT_ACS_STATE
Definition: XMC4800.h:1597
USB0_CH_TypeDef::HCINT
__IO uint32_t HCINT
Definition: XMC4800.h:1862
DLR_GLOBAL_TypeDef
DMA Line Router (DLR)
Definition: XMC4800.h:511
PORT14_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2703
SDMMC_GLOBAL_TypeDef::TIMEOUT_CTRL
__IO uint8_t TIMEOUT_CTRL
Definition: XMC4800.h:1219
PORT0_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2421
ECAT_Type::ESC_RESET_ECAT_WRITEMode
__I uint8_t ESC_RESET_ECAT_WRITEMode
Definition: XMC4800.h:1528
PORT9_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2678
CCU8_CC8_TypeDef::TIMER
__IO uint32_t TIMER
Definition: XMC4800.h:2346
CCU4_GLOBAL_TypeDef::GCSS
__O uint32_t GCSS
Definition: XMC4800.h:2241
GPDMA0_GLOBAL_TypeDef::CLEARTFR
__O uint32_t CLEARTFR
Definition: XMC4800.h:577
DSD_GLOBAL_TypeDef::GLOBCFG
__IO uint32_t GLOBCFG
Definition: XMC4800.h:2156
SDMMC_GLOBAL_TypeDef::RESPONSE4
__I uint32_t RESPONSE4
Definition: XMC4800.h:1210
USB0_EP0_TypeDef::DIEPINT0
__IO uint32_t DIEPINT0
Definition: XMC4800.h:1790
GPDMA0_GLOBAL_TypeDef::SGLREQDSTREG
__IO uint32_t SGLREQDSTREG
Definition: XMC4800.h:595
GPDMA0_GLOBAL_TypeDef::RESERVED26
__I uint32_t RESERVED26
Definition: XMC4800.h:600
ETH_GLOBAL_TypeDef::RX_64OCTETS_FRAMES_GOOD_BAD
__I uint32_t RX_64OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1391
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: XMC4800.h:67
POSIF_GLOBAL_TypeDef::PRUNC
__O uint32_t PRUNC
Definition: XMC4800.h:2373
SCU_RESET_TypeDef::PRSTAT3
__I uint32_t PRSTAT3
Definition: XMC4800.h:1148
PPB_Type::NVIC_IPR26
__IO uint32_t NVIC_IPR26
Definition: XMC4800.h:460
FLASH0_GLOBAL_TypeDef::PROCON2
__I uint32_t PROCON2
Definition: XMC4800.h:838
VADC0_G2_2_IRQn
@ VADC0_G2_2_IRQn
Definition: XMC4800.h:103
VADC_G_TypeDef::BFLNP
__IO uint32_t BFLNP
Definition: XMC4800.h:2092
USB0_GLOBAL_TypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: XMC4800.h:1766
DSD_GLOBAL_TypeDef::EVFLAG
__IO uint32_t EVFLAG
Definition: XMC4800.h:2162
ECAT_Type::MII_PHY_REG_ADR
__IO uint8_t MII_PHY_REG_ADR
Definition: XMC4800.h:1595
VADC_GLOBAL_TypeDef::GLOBEVNP
__IO uint32_t GLOBEVNP
Definition: XMC4800.h:2045
PORT8_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2641
ETH_GLOBAL_TypeDef::RXIPV6_GOOD_FRAMES
__I uint32_t RXIPV6_GOOD_FRAMES
Definition: XMC4800.h:1423
ETH_GLOBAL_TypeDef::RECEIVE_INTERRUPT_WATCHDOG_TIMER
__IO uint32_t RECEIVE_INTERRUPT_WATCHDOG_TIMER
Definition: XMC4800.h:1469
PPB_Type::NVIC_IPR11
__IO uint32_t NVIC_IPR11
Definition: XMC4800.h:445
USIC_CH_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:1905
VADC_GLOBAL_TypeDef::GLOBBOUND
__IO uint32_t GLOBBOUND
Definition: XMC4800.h:2041
POSIF_GLOBAL_TypeDef::MCMF
__I uint32_t MCMF
Definition: XMC4800.h:2385
USB0_GLOBAL_TypeDef::HFLBADDR
__IO uint32_t HFLBADDR
Definition: XMC4800.h:1755
PORT3_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2498
USIC_CH_TypeDef
Universal Serial Interface Controller 0 (USIC_CH)
Definition: XMC4800.h:1902
GPDMA0_GLOBAL_TypeDef::RESERVED20
__I uint32_t RESERVED20
Definition: XMC4800.h:588
FLASH0_GLOBAL_TypeDef::MARP
__IO uint32_t MARP
Definition: XMC4800.h:832
VADC0_G1_0_IRQn
@ VADC0_G1_0_IRQn
Definition: XMC4800.h:97
DSD_CH_TypeDef::RESM
__I uint32_t RESM
Definition: XMC4800.h:2188
USB0_EP_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:1845
USIC_CH_TypeDef::PSR_ASCMode
__IO uint32_t PSR_ASCMode
Definition: XMC4800.h:1934
DSD_CH_TypeDef::RESA
__I uint32_t RESA
Definition: XMC4800.h:2192
VADC_GLOBAL_TypeDef::GLOBRCR
__IO uint32_t GLOBRCR
Definition: XMC4800.h:2056
PPB_Type::ICSR
__IO uint32_t ICSR
Definition: XMC4800.h:464
USB0_GLOBAL_TypeDef::GINTMSK_DEVICEMODE
__IO uint32_t GINTMSK_DEVICEMODE
Definition: XMC4800.h:1715
SCU_INTERRUPT_TypeDef::SRSTAT
__I uint32_t SRSTAT
Definition: XMC4800.h:1036
PORT5_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2565
CCU8_CC8_TypeDef::DITS
__IO uint32_t DITS
Definition: XMC4800.h:2331
ETH_GLOBAL_TypeDef::TX_65TO127OCTETS_FRAMES_GOOD_BAD
__I uint32_t TX_65TO127OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1344
ECAT_Type::AL_CONTROL
__I uint16_t AL_CONTROL
Definition: XMC4800.h:1542
SCU_CLK_TypeDef::CGATSET1
__O uint32_t CGATSET1
Definition: XMC4800.h:945
ETH_GLOBAL_TypeDef::TX_EXCESSIVE_COLLISION_FRAMES
__I uint32_t TX_EXCESSIVE_COLLISION_FRAMES
Definition: XMC4800.h:1368
VADC_G_TypeDef::ASSEL
__IO uint32_t ASSEL
Definition: XMC4800.h:2106
PPB_Type::MPU_RASR_A1
__IO uint32_t MPU_RASR_A1
Definition: XMC4800.h:488
USB0_GLOBAL_TypeDef::HFIR
__IO uint32_t HFIR
Definition: XMC4800.h:1749
VADC_G_TypeDef::EMUXCTR
__IO uint32_t EMUXCTR
Definition: XMC4800.h:2126
PPB_Type::NVIC_IPR21
__IO uint32_t NVIC_IPR21
Definition: XMC4800.h:455
USB0_GLOBAL_TypeDef::DIEPTXF2
__IO uint32_t DIEPTXF2
Definition: XMC4800.h:1742
CCU8_CC8_TypeDef::INS
__IO uint32_t INS
Definition: XMC4800.h:2323
CAN_NODE_TypeDef::NFCR
__IO uint32_t NFCR
Definition: XMC4800.h:2003
SCU_CLK_TypeDef::CGATSTAT2
__I uint32_t CGATSTAT2
Definition: XMC4800.h:947
PORT3_Type
Port 3 (PORT3)
Definition: XMC4800.h:2497
SDMMC_GLOBAL_TypeDef::DATA_BUFFER
__IO uint32_t DATA_BUFFER
Definition: XMC4800.h:1212
VADC0_G0_0_IRQn
@ VADC0_G0_0_IRQn
Definition: XMC4800.h:93
PORT14_Type
Port 14 (PORT14)
Definition: XMC4800.h:2697
VADC_G_TypeDef::REFLAG
__IO uint32_t REFLAG
Definition: XMC4800.h:2110
SCU_CLK_TypeDef::USBCLKCR
__IO uint32_t USBCLKCR
Definition: XMC4800.h:931
PORT0_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2416
PORT2_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2476
USIC0_5_IRQn
@ USIC0_5_IRQn
Definition: XMC4800.h:160
GPDMA1_GLOBAL_TypeDef::RESERVED25
__I uint32_t RESERVED25
Definition: XMC4800.h:729
PPB_Type::NVIC_IPR14
__IO uint32_t NVIC_IPR14
Definition: XMC4800.h:448
CCU43_1_IRQn
@ CCU43_1_IRQn
Definition: XMC4800.h:132
CCU4_CC4_TypeDef::INTS
__I uint32_t INTS
Definition: XMC4800.h:2279
USB0_GLOBAL_TypeDef::HFNUM
__IO uint32_t HFNUM
Definition: XMC4800.h:1750
SCU_GENERAL_TypeDef::DTSCON
__IO uint32_t DTSCON
Definition: XMC4800.h:1014
FLASH0_GLOBAL_TypeDef::FCON
__IO uint32_t FCON
Definition: XMC4800.h:831
CCU42_1_IRQn
@ CCU42_1_IRQn
Definition: XMC4800.h:128
DAC_GLOBAL_TypeDef::DAC0PATH
__IO uint32_t DAC0PATH
Definition: XMC4800.h:2221
GPDMA1_GLOBAL_TypeDef::RESERVED9
__I uint32_t RESERVED9
Definition: XMC4800.h:697
VADC_G_TypeDef::SEFLAG
__IO uint32_t SEFLAG
Definition: XMC4800.h:2111
LEDTS0_GLOBAL_TypeDef::LDCMP0
__IO uint32_t LDCMP0
Definition: XMC4800.h:1171
PMU0_GLOBAL_TypeDef
Program Management Unit (PMU)
Definition: XMC4800.h:866
VADC_GLOBAL_TypeDef::OCS
__IO uint32_t OCS
Definition: XMC4800.h:2035
GPDMA1_CH_TypeDef::CFGH
__IO uint32_t CFGH
Definition: XMC4800.h:761
LEDTS0_GLOBAL_TypeDef::TSCMP0
__IO uint32_t TSCMP0
Definition: XMC4800.h:1173
GPDMA1_GLOBAL_TypeDef::RAWTFR
__IO uint32_t RAWTFR
Definition: XMC4800.h:678
PORT7_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2623
SCU_PARITY_TypeDef::PEEN
__IO uint32_t PEEN
Definition: XMC4800.h:1055
LEDTS0_GLOBAL_TypeDef::GLOBCTL
__IO uint32_t GLOBCTL
Definition: XMC4800.h:1165
ECAT_Type::DC_CYC_CONT
__I uint8_t DC_CYC_CONT
Definition: XMC4800.h:1617
USB0_GLOBAL_TypeDef::DCTL
__IO uint32_t DCTL
Definition: XMC4800.h:1760
PORT1_Type
Port 1 (PORT1)
Definition: XMC4800.h:2437
SCU_RESET_TypeDef::PRSET3
__O uint32_t PRSET3
Definition: XMC4800.h:1149
SDMMC_GLOBAL_TypeDef
SD and Multimediacard Interface (SDMMC)
Definition: XMC4800.h:1201
RTC_GLOBAL_TypeDef::RAWSTAT
__I uint32_t RAWSTAT
Definition: XMC4800.h:904
EBU_Type::ADDRSEL2
__IO uint32_t ADDRSEL2
Definition: XMC4800.h:1259
CCU8_CC8_TypeDef::CR1
__I uint32_t CR1
Definition: XMC4800.h:2337
CCU8_GLOBAL_TypeDef::GPCHK
__IO uint32_t GPCHK
Definition: XMC4800.h:2307
DSD_CH_TypeDef::MODCFG
__IO uint32_t MODCFG
Definition: XMC4800.h:2177
GPDMA1_GLOBAL_TypeDef::STATUSINT
__I uint32_t STATUSINT
Definition: XMC4800.h:718
EBU_Type::BUSRCON0
__IO uint32_t BUSRCON0
Definition: XMC4800.h:1261
EBU_Type::ADDRSEL1
__IO uint32_t ADDRSEL1
Definition: XMC4800.h:1258
PORT15_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2726
CCU8_CC8_TypeDef::CR1S
__IO uint32_t CR1S
Definition: XMC4800.h:2338
DSD_CH_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:2178
CAN_NODE_TypeDef::NBTR
__IO uint32_t NBTR
Definition: XMC4800.h:2001
PORT8_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2655
POSIF_GLOBAL_TypeDef::PFLGE
__IO uint32_t PFLGE
Definition: XMC4800.h:2390
PORT1_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2443
CCU8_CC8_TypeDef::PSL
__IO uint32_t PSL
Definition: XMC4800.h:2329
SCU_RESET_TypeDef::PRCLR0
__O uint32_t PRCLR0
Definition: XMC4800.h:1141
ETH_GLOBAL_TypeDef::MMC_CONTROL
__IO uint32_t MMC_CONTROL
Definition: XMC4800.h:1332
PPB_Type::MPU_RASR_A2
__IO uint32_t MPU_RASR_A2
Definition: XMC4800.h:490
ECAT_Type::DC_RCV_TIME_PORT1
__I uint32_t DC_RCV_TIME_PORT1
Definition: XMC4800.h:1601
CCU80_3_IRQn
@ CCU80_3_IRQn
Definition: XMC4800.h:138
GPDMA0_CH_TypeDef::DSTAT
__IO uint32_t DSTAT
Definition: XMC4800.h:632
DSD_GLOBAL_TypeDef::OCS
__IO uint32_t OCS
Definition: XMC4800.h:2154
CAN_MO_TypeDef::MOSTAT
__I uint32_t MOSTAT
Definition: XMC4800.h:385
USIC_CH_TypeDef::DX0CR
__IO uint32_t DX0CR
Definition: XMC4800.h:1910
USIC1_2_IRQn
@ USIC1_2_IRQn
Definition: XMC4800.h:163
CCU4_CC4_TypeDef::DITS
__IO uint32_t DITS
Definition: XMC4800.h:2267
GPDMA0_GLOBAL_TypeDef::RESERVED5
__I uint32_t RESERVED5
Definition: XMC4800.h:558
ECAT_Type::EEP_STATE
__IO uint8_t EEP_STATE
Definition: XMC4800.h:1589
SCU_GENERAL_TypeDef::RMDATA
__IO uint32_t RMDATA
Definition: XMC4800.h:1022
ECAT_Type::RX_ERR_COUNT1
__I uint16_t RX_ERR_COUNT1
Definition: XMC4800.h:1567
RTC_GLOBAL_TypeDef::ATIM0
__IO uint32_t ATIM0
Definition: XMC4800.h:908
ETH_GLOBAL_TypeDef::TRANSMIT_DESCRIPTOR_LIST_ADDRESS
__IO uint32_t TRANSMIT_DESCRIPTOR_LIST_ADDRESS
Definition: XMC4800.h:1464
ETH_GLOBAL_TypeDef::TX_MULTICAST_FRAMES_GOOD
__I uint32_t TX_MULTICAST_FRAMES_GOOD
Definition: XMC4800.h:1341
USB0_CH_TypeDef::HCDMAB
__I uint32_t HCDMAB
Definition: XMC4800.h:1875
GPDMA0_CH_TypeDef::SSTAT
__IO uint32_t SSTAT
Definition: XMC4800.h:630
SCU_OSC_TypeDef::OSCHPCTRL
__IO uint32_t OSCHPCTRL
Definition: XMC4800.h:967
ETH_GLOBAL_TypeDef::RX_VLAN_FRAMES_GOOD_BAD
__I uint32_t RX_VLAN_FRAMES_GOOD_BAD
Definition: XMC4800.h:1408
USIC1_5_IRQn
@ USIC1_5_IRQn
Definition: XMC4800.h:166
GPDMA0_GLOBAL_TypeDef::STATUSERR
__I uint32_t STATUSERR
Definition: XMC4800.h:565
POSIF_GLOBAL_TypeDef::MCSM
__IO uint32_t MCSM
Definition: XMC4800.h:2382
GPDMA1_GLOBAL_TypeDef::RESERVED10
__I uint32_t RESERVED10
Definition: XMC4800.h:699
ECAT_Type::PDI_ERR_COUNT
__I uint8_t PDI_ERR_COUNT
Definition: XMC4800.h:1573
CCU80_0_IRQn
@ CCU80_0_IRQn
Definition: XMC4800.h:135
SDMMC_GLOBAL_TypeDef::CLOCK_CTRL
__IO uint16_t CLOCK_CTRL
Definition: XMC4800.h:1218
CCU8_CC8_TypeDef::TCCLR
__O uint32_t TCCLR
Definition: XMC4800.h:2327
CCU8_CC8_TypeDef::DC1R
__IO uint32_t DC1R
Definition: XMC4800.h:2343
USIC_CH_TypeDef::PCR
__IO uint32_t PCR
Definition: XMC4800.h:1923
PPB_Type::NVIC_ISER2
__IO uint32_t NVIC_ISER2
Definition: XMC4800.h:411
PORT14_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2701
USIC_CH_TypeDef::PCR_IICMode
__IO uint32_t PCR_IICMode
Definition: XMC4800.h:1920
PORT2_Type::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:2475
CAN0_7_IRQn
@ CAN0_7_IRQn
Definition: XMC4800.h:154
USB0_EP0_TypeDef
Universal Serial Bus (USB0_EP0)
Definition: XMC4800.h:1787
POSIF1_0_IRQn
@ POSIF1_0_IRQn
Definition: XMC4800.h:145
GPDMA0_GLOBAL_TypeDef::REQSRCREG
__IO uint32_t REQSRCREG
Definition: XMC4800.h:589
USB0_GLOBAL_TypeDef::GINTSTS_HOSTMODE
__IO uint32_t GINTSTS_HOSTMODE
Definition: XMC4800.h:1711
DSD_GLOBAL_TypeDef
Delta Sigma Demodulator (DSD)
Definition: XMC4800.h:2149
USB0_GLOBAL_TypeDef::DCFG
__IO uint32_t DCFG
Definition: XMC4800.h:1759
PPB_Type::MPU_RBAR_A2
__IO uint32_t MPU_RBAR_A2
Definition: XMC4800.h:489
ECAT_Type::ESC_RESET_PDI_READMode
__I uint8_t ESC_RESET_PDI_READMode
Definition: XMC4800.h:1532
EBU_Type::ADDRSEL3
__IO uint32_t ADDRSEL3
Definition: XMC4800.h:1260
ECAT_Type::DC_SYNC1_STAT
__I uint8_t DC_SYNC1_STAT
Definition: XMC4800.h:1623
USIC2_2_IRQn
@ USIC2_2_IRQn
Definition: XMC4800.h:169
USB0_EP_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:1825
ECAT0_CON_Type::CONP0
__IO uint32_t CONP0
Definition: XMC4800.h:1492
ERU0_1_IRQn
@ ERU0_1_IRQn
Definition: XMC4800.h:81
EBU_Type
External Bus Unit (EBU)
Definition: XMC4800.h:1251
PPB_Type::NVIC_IPR19
__IO uint32_t NVIC_IPR19
Definition: XMC4800.h:453
PendSV_IRQn
@ PendSV_IRQn
Definition: XMC4800.h:76
ETH_GLOBAL_TypeDef::RXIPV6_HEADER_ERROR_FRAMES
__I uint32_t RXIPV6_HEADER_ERROR_FRAMES
Definition: XMC4800.h:1424
SCU_CLK_TypeDef::SLEEPCR
__IO uint32_t SLEEPCR
Definition: XMC4800.h:937
CAN_GLOBAL_TypeDef::MCR
__IO uint32_t MCR
Definition: XMC4800.h:1982
CCU4_CC4_TypeDef::PSL
__IO uint32_t PSL
Definition: XMC4800.h:2265
SCU_INTERRUPT_TypeDef::NMIREQEN
__IO uint32_t NMIREQEN
Definition: XMC4800.h:1041
GPDMA1_GLOBAL_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:683
DSD_GLOBAL_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:2157
USB0_EP0_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:1798
USB0_CH_TypeDef::HCDMA_SCATGATHER
__IO uint32_t HCDMA_SCATGATHER
Definition: XMC4800.h:1871
SCU_INTERRUPT_TypeDef::SRRAW
__I uint32_t SRRAW
Definition: XMC4800.h:1037
LEDTS0_GLOBAL_TypeDef
LED and Touch Sense Unit 0 (LEDTS)
Definition: XMC4800.h:1163
ETH_GLOBAL_TypeDef::RECEIVE_DESCRIPTOR_LIST_ADDRESS
__IO uint32_t RECEIVE_DESCRIPTOR_LIST_ADDRESS
Definition: XMC4800.h:1463
USB0_GLOBAL_TypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: XMC4800.h:1754
CCU4_CC4_TypeDef::SWR
__O uint32_t SWR
Definition: XMC4800.h:2283
ETH_GLOBAL_TypeDef::GMII_ADDRESS
__IO uint32_t GMII_ADDRESS
Definition: XMC4800.h:1312
PPB_Type::NVIC_IABR2
__IO uint32_t NVIC_IABR2
Definition: XMC4800.h:431
PORT1_Type::IN
__I uint32_t IN
Definition: XMC4800.h:2446
ETH_GLOBAL_TypeDef::TX_OCTET_COUNT_GOOD
__I uint32_t TX_OCTET_COUNT_GOOD
Definition: XMC4800.h:1372
SCU_GENERAL_TypeDef::IDMANUF
__I uint32_t IDMANUF
Definition: XMC4800.h:1006
SDMMC_GLOBAL_TypeDef::HOST_CTRL
__IO uint8_t HOST_CTRL
Definition: XMC4800.h:1214
USB0_GLOBAL_TypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: XMC4800.h:1705
PORT9_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2670
USB0_EP_TypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: XMC4800.h:1837
ECAT_Type::PHYSICAL_RW_OFFSET
__I uint16_t PHYSICAL_RW_OFFSET
Definition: XMC4800.h:1538
PORT2_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2484
GPDMA1_GLOBAL_TypeDef::CLEARBLOCK
__O uint32_t CLEARBLOCK
Definition: XMC4800.h:710
DSD_CH_TypeDef::DICFG
__IO uint32_t DICFG
Definition: XMC4800.h:2179
WDT_GLOBAL_TypeDef::WDTSTS
__I uint32_t WDTSTS
Definition: XMC4800.h:887
ETH_GLOBAL_TypeDef::TX_MULTIPLE_COLLISION_GOOD_FRAMES
__I uint32_t TX_MULTIPLE_COLLISION_GOOD_FRAMES
Definition: XMC4800.h:1363
DSD_GLOBAL_TypeDef::CLC
__IO uint32_t CLC
Definition: XMC4800.h:2150
Reset_IRQn
@ Reset_IRQn
Definition: XMC4800.h:66
PORT5_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2567
DSD_CH_TypeDef::RESERVED6
__I uint32_t RESERVED6
Definition: XMC4800.h:2191
USB0_EP0_TypeDef::DOEPDMA0
__IO uint32_t DOEPDMA0
Definition: XMC4800.h:1802
USB0_CH_TypeDef::HCDMA_BUFFERMODE
__IO uint32_t HCDMA_BUFFERMODE
Definition: XMC4800.h:1872
GPDMA0_GLOBAL_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:550
ETH_GLOBAL_TypeDef::REMOTE_WAKE_UP_FRAME_FILTER
__IO uint32_t REMOTE_WAKE_UP_FRAME_FILTER
Definition: XMC4800.h:1318
USB0_GLOBAL_TypeDef::RESERVED9
__I uint32_t RESERVED9
Definition: XMC4800.h:1770
SCU_TRAP_TypeDef::TRAPRAW
__I uint32_t TRAPRAW
Definition: XMC4800.h:1077
FCE0_0_IRQn
@ FCE0_0_IRQn
Definition: XMC4800.h:174
EBU_Type::MODCON
__IO uint32_t MODCON
Definition: XMC4800.h:1253
WDT_GLOBAL_TypeDef::SRV
__O uint32_t SRV
Definition: XMC4800.h:883
ERU1_2_IRQn
@ ERU1_2_IRQn
Definition: XMC4800.h:86
USIC0_0_IRQn
@ USIC0_0_IRQn
Definition: XMC4800.h:155
GPDMA0_GLOBAL_TypeDef::RESERVED12
__I uint32_t RESERVED12
Definition: XMC4800.h:572
ETH_GLOBAL_TypeDef::STATUS
__IO uint32_t STATUS
Definition: XMC4800.h:1465
PORT14_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2699
GPDMA0_GLOBAL_TypeDef::RAWDSTTRAN
__IO uint32_t RAWDSTTRAN
Definition: XMC4800.h:553
USB0_EP_TypeDef::DOEPTSIZ_CONTROL
__IO uint32_t DOEPTSIZ_CONTROL
Definition: XMC4800.h:1841
ECAT0_SM_Type::SM_PDI_CTR
__IO uint8_t SM_PDI_CTR
Definition: XMC4800.h:1689
EBU_Type::BUSWCON3
__IO uint32_t BUSWCON3
Definition: XMC4800.h:1275
PPB_Type::NVIC_IPR5
__IO uint32_t NVIC_IPR5
Definition: XMC4800.h:439
USB0_EP_TypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: XMC4800.h:1826
PORT7_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2626
ECAT_Type::STATUS
__I uint32_t STATUS
Definition: XMC4800.h:1649
ECAT_Type::MII_PHY_DATA
__IO uint16_t MII_PHY_DATA
Definition: XMC4800.h:1596
USB0_GLOBAL_TypeDef::HCFG
__IO uint32_t HCFG
Definition: XMC4800.h:1748
PORT1_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2454
PREF_GLOBAL_TypeDef
Prefetch Unit (PREF)
Definition: XMC4800.h:852
ETH_GLOBAL_TypeDef::TARGET_TIME_SECONDS
__IO uint32_t TARGET_TIME_SECONDS
Definition: XMC4800.h:1455
PORT8_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2643
CAN_MO_TypeDef::MOFGPR
__IO uint32_t MOFGPR
Definition: XMC4800.h:377
PORT7_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2625
SCU_POWER_TypeDef::EVRVADCSTAT
__I uint32_t EVRVADCSTAT
Definition: XMC4800.h:1120
VADC_G_TypeDef::QMR0
__IO uint32_t QMR0
Definition: XMC4800.h:2095
GPDMA1_CH_TypeDef::CTLL
__IO uint32_t CTLL
Definition: XMC4800.h:757
GPDMA0_GLOBAL_TypeDef::RAWERR
__IO uint32_t RAWERR
Definition: XMC4800.h:555
FLASH0_GLOBAL_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:833
USB0_EP0_TypeDef::DOEPCTL0
__IO uint32_t DOEPCTL0
Definition: XMC4800.h:1797
ECAT_Type::BUILD
__I uint16_t BUILD
Definition: XMC4800.h:1509
CCU8_GLOBAL_TypeDef::GCSS
__O uint32_t GCSS
Definition: XMC4800.h:2304
PPB_Type::MMFAR
__IO uint32_t MMFAR
Definition: XMC4800.h:476
GPDMA1_GLOBAL_TypeDef::MASKBLOCK
__IO uint32_t MASKBLOCK
Definition: XMC4800.h:700
PPB_Type::NVIC_IPR13
__IO uint32_t NVIC_IPR13
Definition: XMC4800.h:447
PORT3_Type::IOCR8
__IO uint32_t IOCR8
Definition: XMC4800.h:2503
USB0_EP0_TypeDef::DIEPDMAB0
__I uint32_t DIEPDMAB0
Definition: XMC4800.h:1795
GPDMA0_GLOBAL_TypeDef::RESERVED21
__I uint32_t RESERVED21
Definition: XMC4800.h:590
USIC_CH_TypeDef::PSR_IICMode
__IO uint32_t PSR_IICMode
Definition: XMC4800.h:1930
SDMMC_GLOBAL_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:1232
ECAT_Type::ESC_WR_PROTECT
__I uint8_t ESC_WR_PROTECT
Definition: XMC4800.h:1523
ECAT_Type::DC_SYS_TIME_DIFF
__I uint32_t DC_SYS_TIME_DIFF
Definition: XMC4800.h:1611
GPDMA0_GLOBAL_TypeDef::LSTDSTREG
__IO uint32_t LSTDSTREG
Definition: XMC4800.h:599
VADC_G_TypeDef::BFLC
__IO uint32_t BFLC
Definition: XMC4800.h:2091
EBU_Type::BUSRAP1
__IO uint32_t BUSRAP1
Definition: XMC4800.h:1266
CCU4_CC4_TypeDef::TC
__IO uint32_t TC
Definition: XMC4800.h:2264
GPDMA1_GLOBAL_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:681
CAN_GLOBAL_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1971
GPDMA1_GLOBAL_TypeDef::RESERVED21
__I uint32_t RESERVED21
Definition: XMC4800.h:721
PORT8_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2650
VADC_G_TypeDef::Q0R0
__I uint32_t Q0R0
Definition: XMC4800.h:2097
PPB_Type::NVIC_ICPR1
__IO uint32_t NVIC_ICPR1
Definition: XMC4800.h:425
DSD_CH_TypeDef::IWCTR
__IO uint32_t IWCTR
Definition: XMC4800.h:2184
SCU_INTERRUPT_TypeDef
System Control Unit (SCU_INTERRUPT)
Definition: XMC4800.h:1035
CCU41_0_IRQn
@ CCU41_0_IRQn
Definition: XMC4800.h:123
CCU4_CC4_TypeDef::FPCS
__IO uint32_t FPCS
Definition: XMC4800.h:2270
SDMMC_GLOBAL_TypeDef::CAPABILITIES_HI
__I uint32_t CAPABILITIES_HI
Definition: XMC4800.h:1230
USB0_CH_TypeDef::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:1874
PPB_Type::NVIC_IPR20
__IO uint32_t NVIC_IPR20
Definition: XMC4800.h:454
DAC0_0_IRQn
@ DAC0_0_IRQn
Definition: XMC4800.h:117
FCE_KE_TypeDef::LENGTH
__IO uint32_t LENGTH
Definition: XMC4800.h:795
ERU0_2_IRQn
@ ERU0_2_IRQn
Definition: XMC4800.h:82
ECAT_Type::LOST_LINK_COUNT1
__I uint8_t LOST_LINK_COUNT1
Definition: XMC4800.h:1576
USB0_EP0_TypeDef::DOEPTSIZ0
__IO uint32_t DOEPTSIZ0
Definition: XMC4800.h:1801
SCU_PLL_TypeDef::PLLCON2
__IO uint32_t PLLCON2
Definition: XMC4800.h:986
PPB_Type::NVIC_ICPR0
__IO uint32_t NVIC_ICPR0
Definition: XMC4800.h:424
SDMMC_GLOBAL_TypeDef::ARGUMENT1
__IO uint32_t ARGUMENT1
Definition: XMC4800.h:1205
SDMMC_GLOBAL_TypeDef::BLOCK_COUNT
__IO uint16_t BLOCK_COUNT
Definition: XMC4800.h:1204
SCU_POWER_TypeDef
System Control Unit (SCU_POWER)
Definition: XMC4800.h:1114
GPDMA0_GLOBAL_TypeDef::RAWSRCTRAN
__IO uint32_t RAWSRCTRAN
Definition: XMC4800.h:551
SCU_CLK_TypeDef::CGATCLR1
__O uint32_t CGATCLR1
Definition: XMC4800.h:946
USIC_CH_TypeDef::FDR
__IO uint32_t FDR
Definition: XMC4800.h:1907
ECAT_Type::EEP_ADR
__IO uint32_t EEP_ADR
Definition: XMC4800.h:1591
SVCall_IRQn
@ SVCall_IRQn
Definition: XMC4800.h:74
ETH_GLOBAL_TypeDef::TX_FRAME_COUNT_GOOD
__I uint32_t TX_FRAME_COUNT_GOOD
Definition: XMC4800.h:1373
PORT0_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2408
ECAT_Type::ID
__I uint32_t ID
Definition: XMC4800.h:1647
SDMMC_GLOBAL_TypeDef::CAPABILITIES
__I uint32_t CAPABILITIES
Definition: XMC4800.h:1229
USIC_CH_TypeDef::RBCTR
__IO uint32_t RBCTR
Definition: XMC4800.h:1949
USB0_GLOBAL_TypeDef::DSTS
__I uint32_t DSTS
Definition: XMC4800.h:1761
USB0_CH_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1861
FLASH0_GLOBAL_TypeDef::PROCON1
__I uint32_t PROCON1
Definition: XMC4800.h:836
GPDMA0_CH_TypeDef::DAR
__IO uint32_t DAR
Definition: XMC4800.h:624
GPDMA1_CH_TypeDef
General Purpose DMA Unit 1 (GPDMA1_CH)
Definition: XMC4800.h:752
USIC1_0_IRQn
@ USIC1_0_IRQn
Definition: XMC4800.h:161
VADC0_G1_1_IRQn
@ VADC0_G1_1_IRQn
Definition: XMC4800.h:98
SCU_CLK_TypeDef::SYSCLKCR
__IO uint32_t SYSCLKCR
Definition: XMC4800.h:928
GPDMA1_GLOBAL_TypeDef::STATUSERR
__I uint32_t STATUSERR
Definition: XMC4800.h:696
USIC_CH_TypeDef::INPR
__IO uint32_t INPR
Definition: XMC4800.h:1909
PPB_Type::NVIC_IPR16
__IO uint32_t NVIC_IPR16
Definition: XMC4800.h:450
SCU_GENERAL_TypeDef::MIRRSTS
__I uint32_t MIRRSTS
Definition: XMC4800.h:1020
ECAT_Type::DC_LATCH0_STAT
__I uint8_t DC_LATCH0_STAT
Definition: XMC4800.h:1631
CCU80_1_IRQn
@ CCU80_1_IRQn
Definition: XMC4800.h:136
EBU_Type::BUSWAP2
__IO uint32_t BUSWAP2
Definition: XMC4800.h:1272
CCU8_CC8_TypeDef::SWR
__O uint32_t SWR
Definition: XMC4800.h:2353
USIC_CH_TypeDef::OUTDR
__I uint32_t OUTDR
Definition: XMC4800.h:1954
LEDTS0_0_IRQn
@ LEDTS0_0_IRQn
Definition: XMC4800.h:173
GPDMA1_GLOBAL_TypeDef::CLEARTFR
__O uint32_t CLEARTFR
Definition: XMC4800.h:708
EBU_Type::BUSWCON2
__IO uint32_t BUSWCON2
Definition: XMC4800.h:1271
ETH_GLOBAL_TypeDef::RX_OUT_OF_RANGE_TYPE_FRAMES
__I uint32_t RX_OUT_OF_RANGE_TYPE_FRAMES
Definition: XMC4800.h:1405
WDT_GLOBAL_TypeDef::ID
__I uint32_t ID
Definition: XMC4800.h:881
PPB_Type::MPU_RASR_A3
__IO uint32_t MPU_RASR_A3
Definition: XMC4800.h:492
VADC_G_TypeDef::ASMR
__IO uint32_t ASMR
Definition: XMC4800.h:2105
ETH_GLOBAL_TypeDef::RX_RUNT_ERROR_FRAMES
__I uint32_t RX_RUNT_ERROR_FRAMES
Definition: XMC4800.h:1387
PBA_GLOBAL_TypeDef::STS
__IO uint32_t STS
Definition: XMC4800.h:812
ETH_GLOBAL_TypeDef::RX_JABBER_ERROR_FRAMES
__I uint32_t RX_JABBER_ERROR_FRAMES
Definition: XMC4800.h:1388
PPB_Type::NVIC_ISER3
__IO uint32_t NVIC_ISER3
Definition: XMC4800.h:412
DSD_GLOBAL_TypeDef::CGCFG
__IO uint32_t CGCFG
Definition: XMC4800.h:2160
VADC0_C0_0_IRQn
@ VADC0_C0_0_IRQn
Definition: XMC4800.h:89
SCU_HIBERNATE_TypeDef::OSCULSTAT
__I uint32_t OSCULSTAT
Definition: XMC4800.h:1100
PPB_Type::NVIC_IPR4
__IO uint32_t NVIC_IPR4
Definition: XMC4800.h:438
USIC_CH_TypeDef::RBUF01SR
__I uint32_t RBUF01SR
Definition: XMC4800.h:1942
ECAT0_FMMU_Type::FMMU_TYPE
__I uint8_t FMMU_TYPE
Definition: XMC4800.h:1669
ECAT_Type::DC_LATCH1_CONT
__IO uint8_t DC_LATCH1_CONT
Definition: XMC4800.h:1629
GPDMA0_GLOBAL_TypeDef::RESERVED18
__I uint32_t RESERVED18
Definition: XMC4800.h:584
ECAT_Type::AL_STATUS
__IO uint16_t AL_STATUS
Definition: XMC4800.h:1544
EBU_Type::BUSWAP0
__IO uint32_t BUSWAP0
Definition: XMC4800.h:1264
PPB_Type::NVIC_IPR7
__IO uint32_t NVIC_IPR7
Definition: XMC4800.h:441
CAN_MO_TypeDef::MOAMR
__IO uint32_t MOAMR
Definition: XMC4800.h:379
CCU81_1_IRQn
@ CCU81_1_IRQn
Definition: XMC4800.h:140
GPDMA1_GLOBAL_TypeDef::RESERVED27
__I uint32_t RESERVED27
Definition: XMC4800.h:733
GPDMA1_GLOBAL_TypeDef::RESERVED16
__I uint32_t RESERVED16
Definition: XMC4800.h:711
GPDMA1_GLOBAL_TypeDef::CLEARDSTTRAN
__O uint32_t CLEARDSTTRAN
Definition: XMC4800.h:714
ECAT_Type::WD_TIME_PDI
__IO uint16_t WD_TIME_PDI
Definition: XMC4800.h:1580
CCU8_CC8_TypeDef::SWS
__O uint32_t SWS
Definition: XMC4800.h:2352
SCU_CLK_TypeDef::CGATSTAT0
__I uint32_t CGATSTAT0
Definition: XMC4800.h:941
ETH_GLOBAL_TypeDef::RX_OCTET_COUNT_GOOD
__I uint32_t RX_OCTET_COUNT_GOOD
Definition: XMC4800.h:1382
ECAT_Type::TYPE
__I uint8_t TYPE
Definition: XMC4800.h:1507
FCE_KE_TypeDef
Flexible CRC Engine (FCE_KE)
Definition: XMC4800.h:790
PORT5_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2570
SCU_PARITY_TypeDef::RESERVED
__I uint32_t RESERVED
Definition: XMC4800.h:1059
PORT1_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2441
GPDMA0_GLOBAL_TypeDef::RESERVED8
__I uint32_t RESERVED8
Definition: XMC4800.h:564
PORT5_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2556
PORT0_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2419
EBU_Type::BUSWCON1
__IO uint32_t BUSWCON1
Definition: XMC4800.h:1267
USIC_CH_TypeDef::PCR_IISMode
__IO uint32_t PCR_IISMode
Definition: XMC4800.h:1921
ETH_GLOBAL_TypeDef::RXIPV4_NO_PAYLOAD_FRAMES
__I uint32_t RXIPV4_NO_PAYLOAD_FRAMES
Definition: XMC4800.h:1419
GPDMA0_CH_TypeDef::RESERVED7
__I uint32_t RESERVED7
Definition: XMC4800.h:641
VADC_G_TypeDef::RESERVED3
__I uint32_t RESERVED3
Definition: XMC4800.h:2084
CAN_MO_TypeDef
Definition: XMC4800.h:375
PORT14_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2711
SCU_GENERAL_TypeDef::STCON
__IO uint32_t STCON
Definition: XMC4800.h:1008
EBU_Type::USERCON
__IO uint32_t USERCON
Definition: XMC4800.h:1255
CAN_GLOBAL_TypeDef::MITR
__O uint32_t MITR
Definition: XMC4800.h:1983
CCU4_CC4_TypeDef::FPC
__IO uint32_t FPC
Definition: XMC4800.h:2269
SCU_RESET_TypeDef::RSTSTAT
__I uint32_t RSTSTAT
Definition: XMC4800.h:1136
VADC0_G2_3_IRQn
@ VADC0_G2_3_IRQn
Definition: XMC4800.h:104
PORT15_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2725
CCU4_CC4_TypeDef::TIMER
__IO uint32_t TIMER
Definition: XMC4800.h:2276
SCU_PARITY_TypeDef
System Control Unit (SCU_PARITY)
Definition: XMC4800.h:1054
PORT6_Type::PDISC
__I uint32_t PDISC
Definition: XMC4800.h:2594
CCU4_GLOBAL_TypeDef::GIDLC
__O uint32_t GIDLC
Definition: XMC4800.h:2240
GPDMA0_GLOBAL_TypeDef::MASKTFR
__IO uint32_t MASKTFR
Definition: XMC4800.h:567
ETH_GLOBAL_TypeDef::RX_OCTET_COUNT_GOOD_BAD
__I uint32_t RX_OCTET_COUNT_GOOD_BAD
Definition: XMC4800.h:1381
PORT15_Type::HWSEL
__IO uint32_t HWSEL
Definition: XMC4800.h:2738
ETH_GLOBAL_TypeDef::RXIPV6_GOOD_OCTETS
__I uint32_t RXIPV6_GOOD_OCTETS
Definition: XMC4800.h:1438
VADC_G_TypeDef::REFCLR
__O uint32_t REFCLR
Definition: XMC4800.h:2114
GPDMA0_GLOBAL_TypeDef::RESERVED25
__I uint32_t RESERVED25
Definition: XMC4800.h:598
ETH_GLOBAL_TypeDef::MAC_ADDRESS2_LOW
__IO uint32_t MAC_ADDRESS2_LOW
Definition: XMC4800.h:1328
DSD_CH_TypeDef
Delta Sigma Demodulator (DSD_CH)
Definition: XMC4800.h:2176
USB0_GLOBAL_TypeDef::GRXSTSP_DEVICEMODE
__I uint32_t GRXSTSP_DEVICEMODE
Definition: XMC4800.h:1726
GPDMA0_CH2_7_Type
General Purpose DMA Unit 0 (GPDMA0_CH2_7)
Definition: XMC4800.h:655
PORT7_Type::IOCR0
__IO uint32_t IOCR0
Definition: XMC4800.h:2614
VADC_GLOBAL_TypeDef::CLC
__IO uint32_t CLC
Definition: XMC4800.h:2031
CCU42_3_IRQn
@ CCU42_3_IRQn
Definition: XMC4800.h:130
ECAT_Type::RESERVED19
__I uint16_t RESERVED19
Definition: XMC4800.h:1571
RTC_GLOBAL_TypeDef::TIM0
__IO uint32_t TIM0
Definition: XMC4800.h:910
CCU8_GLOBAL_TypeDef::GCST
__I uint32_t GCST
Definition: XMC4800.h:2306
ETH_GLOBAL_TypeDef::SYSTEM_TIME_NANOSECONDS
__I uint32_t SYSTEM_TIME_NANOSECONDS
Definition: XMC4800.h:1451
VADC_G_TypeDef::RESERVED13
__I uint32_t RESERVED13
Definition: XMC4800.h:2123
VADC_GLOBAL_TypeDef::BRSCTRL
__IO uint32_t BRSCTRL
Definition: XMC4800.h:2053
USIC_CH_TypeDef::DX3CR
__IO uint32_t DX3CR
Definition: XMC4800.h:1913
PORT0_Type::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:2415
SDMMC_GLOBAL_TypeDef::BLOCK_GAP_CTRL
__IO uint8_t BLOCK_GAP_CTRL
Definition: XMC4800.h:1216
EBU_Type::BUSRCON2
__IO uint32_t BUSRCON2
Definition: XMC4800.h:1269
ECAT_Type::ESC_DL_STATUS
__I uint16_t ESC_DL_STATUS
Definition: XMC4800.h:1540
GPDMA0_GLOBAL_TypeDef::CLEARBLOCK
__O uint32_t CLEARBLOCK
Definition: XMC4800.h:579
PORT7_Type::OMR
__O uint32_t OMR
Definition: XMC4800.h:2612
CCU4_CC4_TypeDef::TCCLR
__O uint32_t TCCLR
Definition: XMC4800.h:2263
USIC_CH_TypeDef::BYP
__IO uint32_t BYP
Definition: XMC4800.h:1946
CAN_MO_CLUSTER_Type
Controller Area Networks (CAN_MO_CLUSTER)
Definition: XMC4800.h:2016
EBU_Type::SDRMCON
__IO uint32_t SDRMCON
Definition: XMC4800.h:1277
WDT_GLOBAL_TypeDef::WDTCLR
__O uint32_t WDTCLR
Definition: XMC4800.h:888
PORT6_Type::PPS
__IO uint32_t PPS
Definition: XMC4800.h:2596
USB0_GLOBAL_TypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: XMC4800.h:1703
VADC_G_TypeDef::BOUND
__IO uint32_t BOUND
Definition: XMC4800.h:2085
ERU_GLOBAL_TypeDef::EXISEL
__IO uint32_t EXISEL
Definition: XMC4800.h:530
DAC0_1_IRQn
@ DAC0_1_IRQn
Definition: XMC4800.h:118
CCU81_0_IRQn
@ CCU81_0_IRQn
Definition: XMC4800.h:139
SCU_RESET_TypeDef::RSTCLR
__O uint32_t RSTCLR
Definition: XMC4800.h:1138
CAN_MO_TypeDef::MOIPR
__IO uint32_t MOIPR
Definition: XMC4800.h:378
CCU4_CC4_TypeDef::ECRD1
__I uint32_t ECRD1
Definition: XMC4800.h:2286
CCU8_CC8_TypeDef::SRS
__IO uint32_t SRS
Definition: XMC4800.h:2351
DSD_CH_TypeDef::RESERVED2
__I uint32_t RESERVED2
Definition: XMC4800.h:2183
VADC0_G1_2_IRQn
@ VADC0_G1_2_IRQn
Definition: XMC4800.h:99
USIC_CH_TypeDef::OUTR
__I uint32_t OUTR
Definition: XMC4800.h:1953
SCU_HIBERNATE_TypeDef::HDSET
__O uint32_t HDSET
Definition: XMC4800.h:1096
PORT3_Type::PDR1
__IO uint32_t PDR1
Definition: XMC4800.h:2509
PORT0_Type
Port 0 (PORT0)
Definition: XMC4800.h:2407
PORT1_Type::RESERVED1
__I uint32_t RESERVED1
Definition: XMC4800.h:2445
VADC_G_TypeDef::RESERVED10
__I uint32_t RESERVED10
Definition: XMC4800.h:2116
POSIF_GLOBAL_TypeDef::MCMS
__O uint32_t MCMS
Definition: XMC4800.h:2383
CCU4_CC4_TypeDef::SRS
__IO uint32_t SRS
Definition: XMC4800.h:2281
PPB_Type::NVIC_IPR8
__IO uint32_t NVIC_IPR8
Definition: XMC4800.h:442
DSD_CH_TypeDef::RESERVED9
__I uint32_t RESERVED9
Definition: XMC4800.h:2197
PORT14_Type::OUT
__IO uint32_t OUT
Definition: XMC4800.h:2698
PORT5_Type::PDR0
__IO uint32_t PDR0
Definition: XMC4800.h:2564
ECAT0_SM_Type::SM_STATUS
__I uint8_t SM_STATUS
Definition: XMC4800.h:1687
ETH_GLOBAL_TypeDef::CURRENT_HOST_RECEIVE_BUFFER_ADDRESS
__I uint32_t CURRENT_HOST_RECEIVE_BUFFER_ADDRESS
Definition: XMC4800.h:1476
CAN_MO_TypeDef::MOCTR
__O uint32_t MOCTR
Definition: XMC4800.h:386
CAN_GLOBAL_TypeDef::MSIMASK
__IO uint32_t MSIMASK
Definition: XMC4800.h:1980
ETH_GLOBAL_TypeDef::RX_256TO511OCTETS_FRAMES_GOOD_BAD
__I uint32_t RX_256TO511OCTETS_FRAMES_GOOD_BAD
Definition: XMC4800.h:1397
ETH_GLOBAL_TypeDef::MAC_ADDRESS1_LOW
__IO uint32_t MAC_ADDRESS1_LOW
Definition: XMC4800.h:1326
GPDMA0_GLOBAL_TypeDef::LSTSRCREG
__IO uint32_t LSTSRCREG
Definition: XMC4800.h:597
GPDMA1_GLOBAL_TypeDef::RESERVED17
__I uint32_t RESERVED17
Definition: XMC4800.h:713
PPB_Type::NVIC_IABR1
__IO uint32_t NVIC_IABR1
Definition: XMC4800.h:430
ECAT_Type
EtherCAT 0 (ECAT)
Definition: XMC4800.h:1506
USIC_CH_TypeDef::RBUFD
__I uint32_t RBUFD
Definition: XMC4800.h:1939
__IO
#define __IO
Definition: core_cm4.h:222
ECAT_Type::STATION_ADR
__I uint16_t STATION_ADR
Definition: XMC4800.h:1516
USIC0_3_IRQn
@ USIC0_3_IRQn
Definition: XMC4800.h:158
EBU_Type::BUSRAP3
__IO uint32_t BUSRAP3
Definition: XMC4800.h:1274
SCU_CLK_TypeDef::CGATCLR0
__O uint32_t CGATCLR0
Definition: XMC4800.h:943
CAN0_0_IRQn
@ CAN0_0_IRQn
Definition: XMC4800.h:147
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